def __init__(self): if not hasattr(self, "cpu"): raise ValueError("Platform SoC must be initialized first") self.submodules.kernel_cpu = KernelCPU(self.platform) self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram) self.csr_devices.append("kernel_cpu") self.submodules.mailbox = Mailbox(size=3) self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i1) self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i2) self.add_memory_region("mailbox", self.mem_map["mailbox"] | 0x80000000, 4)
def __init__(self, *args, ethmac_nrxslots=2, ethmac_ntxslots=2, **kwargs): BaseSoC.__init__(self, *args, **kwargs) self.csr_devices += ["ethphy", "ethmac"] self.interrupt_devices.append("ethmac") eth_clocks = self.platform.request("eth_clocks") self.submodules.ethphy = LiteEthPHY(eth_clocks, self.platform.request("eth"), clk_freq=self.clk_freq) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", nrxslots=ethmac_nrxslots, ntxslots=ethmac_ntxslots) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, (ethmac_nrxslots + ethmac_ntxslots) * 0x800) self.crg.cd_sys.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") # period constraints are required here because of vivado self.platform.add_period_constraint(self.crg.cd_sys.clk, 8.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_tx.clk, eth_clocks.rx)
def __init__(self, *args, **kwargs): BaseSoC.__init__(self, *args, **kwargs) platform = self.platform if platform.name == "mixxeo": self.submodules.leds = gpio.GPIOOut(platform.request("user_led")) self.csr_devices.append("leds") if platform.name == "m1": self.submodules.buttons = gpio.GPIOIn( Cat(platform.request("user_btn", 0), platform.request("user_btn", 2))) self.submodules.leds = gpio.GPIOOut( Cat(platform.request("user_led", i) for i in range(2))) self.csr_devices += ["buttons", "leds"] self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.csr_devices += ["ethphy", "ethmac"] self.interrupt_devices.append("ethmac")
def add_rtio(self, rtio_channels): self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk) self.submodules.rtio = rtio.RTIO(rtio_channels) self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) if isinstance(self.platform.toolchain, XilinxVivadoToolchain): self.platform.add_platform_command(""" create_clock -name rsys_clk -period 8.0 [get_nets {rsys_clk}] create_clock -name rio_clk -period 8.0 [get_nets {rio_clk}] set_false_path -from [get_clocks rsys_clk] -to [get_clocks rio_clk] set_false_path -from [get_clocks rio_clk] -to [get_clocks rsys_clk] """, rsys_clk=self.rtio.cd_rsys.clk, rio_clk=self.rtio.cd_rio.clk) if isinstance(self.platform.toolchain, XilinxISEToolchain): self.platform.add_platform_command(""" NET "sys_clk" TNM_NET = "GRPrsys_clk"; NET "{rio_clk}" TNM_NET = "GRPrio_clk"; TIMESPEC "TSfix_cdc1" = FROM "GRPrsys_clk" TO "GRPrio_clk" TIG; TIMESPEC "TSfix_cdc2" = FROM "GRPrio_clk" TO "GRPrsys_clk" TIG; """, rio_clk=self.rtio_crg.cd_rtio.clk) rtio_csrs = self.rtio.get_csrs() self.submodules.rtiowb = wishbone.CSRBank(rtio_csrs) self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus) self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32, rtio_csrs) self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio, self.get_native_sdram_if())
def register_kernel_cpu_csrdevice(self, name): csrs = getattr(self, name).get_csrs() bank = wishbone.CSRBank(csrs) self.submodules += bank self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map[name]), bank.bus) self.add_csr_region(name, self.mem_map[name] | 0x80000000, 32, csrs)
def register_kernel_cpu_csrdevice(self, name): # make sure the device is not getting connected to the comms-CPU already assert self.csr_map[name] is None csrs = getattr(self, name).get_csrs() bank = wishbone.CSRBank(csrs) self.submodules += bank self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map[name]), bank.bus) self.add_csr_region(name, self.mem_map[name] | 0x80000000, 32, csrs)
def __init__(self): if not hasattr(self, "cpu"): raise ValueError("Platform SoC must be initialized first") if hasattr(self, "timer0"): raise ValueError("Timer already exists. " "Initialize platform SoC using with_timer=False") self.submodules.timer0 = timer.Timer(width=64) self.submodules.kernel_cpu = amp.KernelCPU(self.platform) self.add_wb_sdram_if(self.kernel_cpu.wb_sdram) self.submodules.mailbox = amp.Mailbox() self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i1) self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i2) self.add_memory_region("mailbox", self.mem_map["mailbox"] | 0x80000000, 4)
def __init__(self): if not hasattr(self, "cpu"): raise ValueError("Platform SoC must be initialized first") if hasattr(self, "timer0"): raise ValueError("Timer already exists. " "Initialize platform SoC using with_timer=False") self.submodules.timer0 = timer.Timer(width=64) self.submodules.kernel_cpu = amp.KernelCPU(self.platform) self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram) self.submodules.mailbox = amp.Mailbox() self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i1) self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i2) self.add_memory_region("mailbox", self.mem_map["mailbox"] | 0x80000000, 4) self.submodules.timer_kernel = timer.Timer() self.register_kernel_cpu_csrdevice("timer_kernel")
def __init__(self, *args, **kwargs): BaseSoC.__init__(self, *args, **kwargs) platform = self.platform if platform.name == "mixxeo": self.submodules.leds = gpio.GPIOOut(platform.request("user_led")) if platform.name == "m1": self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0), platform.request("user_btn", 2))) self.submodules.leds = gpio.GPIOOut(Cat(platform.request("user_led", i) for i in range(2))) self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
def __init__(self, *args, **kwargs): BaseSoC.__init__(self, *args, **kwargs) self.csr_devices += ["ethphy", "ethmac"] self.interrupt_devices.append("ethmac") eth_clocks = self.platform.request("eth_clocks") self.submodules.ethphy = LiteEthPHY(eth_clocks, self.platform.request("eth"), clk_freq=self.clk_freq) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.crg.cd_sys.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") # period constraints are required here because of vivado self.platform.add_period_constraint(self.crg.cd_sys.clk, 8.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_tx.clk, eth_clocks.rx)
def __init__(self, platform, exec_address=0x42000000, main_mem_origin=0x40000000, l2_size=8192): self._reset = CSRStorage(reset=1) # # # self._wb_slaves = [] # CPU core self.clock_domains.cd_sys_kernel = ClockDomain() self.comb += [ self.cd_sys_kernel.clk.eq(ClockSignal()), self.cd_sys_kernel.rst.eq(self._reset.storage) ] self.submodules.cpu = ClockDomainsRenamer("sys_kernel")( mor1kx.MOR1KX(platform, exec_address)) # DRAM access self.wb_sdram = wishbone.Interface() self.add_wb_slave(mem_decoder(main_mem_origin), self.wb_sdram)
def __init__(self, platform, exec_address=0x40400000, main_mem_origin=0x40000000, l2_size=8192): self._reset = CSRStorage(reset=1) # # # self._wb_slaves = [] # CPU core self.clock_domains.cd_sys_kernel = ClockDomain() self.comb += [ self.cd_sys_kernel.clk.eq(ClockSignal()), self.cd_sys_kernel.rst.eq(self._reset.storage) ] self.submodules.cpu = ClockDomainsRenamer("sys_kernel")(mor1kx.MOR1KX( platform, exec_address)) # DRAM access self.wb_sdram = wishbone.Interface() self.add_wb_slave(mem_decoder(main_mem_origin), self.wb_sdram)
def __init__(self, cpu_type="or1k", **kwargs): BaseSoC.__init__(self, cpu_type=cpu_type, l2_size=64*1024, with_timer=False, ident=artiq_version, **kwargs) AMPSoC.__init__(self) platform = self.platform platform.toolchain.ise_commands += """ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd {build_name}.pcf """ platform.add_extension(nist_qc1.papilio_adapter_io) self.submodules.leds = gpio.GPIOOut(platform.request("user_led", 4)) self.comb += [ platform.request("ttl_l_tx_en").eq(1), platform.request("ttl_h_tx_en").eq(1) ] self.submodules.rtio_crg = _RTIOCRG(platform, self.clk_freq) # RTIO channels rtio_channels = [] # pmt1 can run on a 8x serdes if pmt0 is not used for i in range(2): phy = ttl_serdes_spartan6.Inout_4X(platform.request("pmt", i), self.rtio_crg.rtiox4_stb) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512, ofifo_depth=4)) # ttl2 can run on a 8x serdes if xtrig is not used for i in range(15): if i in (0, 1): phy = ttl_serdes_spartan6.Output_4X(platform.request("ttl", i), self.rtio_crg.rtiox4_stb) elif i in (2,): phy = ttl_serdes_spartan6.Output_8X(platform.request("ttl", i), self.rtio_crg.rtiox8_stb) else: phy = ttl_simple.Output(platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=256)) phy = ttl_simple.Output(platform.request("ext_led", 0)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4)) for led_number in range(4): phy = ttl_simple.Output(platform.request("user_led", led_number)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4)) self.add_constant("RTIO_REGULAR_TTL_COUNT", len(rtio_channels)) phy = ttl_simple.ClockGen(platform.request("ttl", 15)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels)) self.add_constant("DDS_CHANNEL_COUNT", 8) self.add_constant("DDS_AD9858") dds_pins = platform.request("dds") self.comb += dds_pins.p.eq(0) phy = dds.AD9858(dds_pins, 8) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=512, ififo_depth=4)) # RTIO core self.submodules.rtio = rtio.RTIO(rtio_channels) self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width) self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) # CPU connections rtio_csrs = self.rtio.get_csrs() self.submodules.rtiowb = wishbone.CSRBank(rtio_csrs) self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus) self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32, rtio_csrs)
def __init__(self, cfg, **kwargs): MiniSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", l2_size=128 * 1024, ident=artiq_version, ethmac_nrxslots=4, ethmac_ntxslots=4, **kwargs) AMPSoC.__init__(self) platform = self.platform self.comb += platform.request("sfp_tx_disable_n").eq(1) tx_pads = platform.request("sfp_tx") rx_pads = platform.request("sfp_rx") if cfg == "simple_gbe": # GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock # simple TTLs self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10( clock_pads=platform.request("sgmii_clock"), tx_pads=tx_pads, rx_pads=rx_pads, sys_clk_freq=self.clk_freq, clock_div2=True) elif cfg == "sawg_3g": # 3Gb link, 150MHz RTIO clock # with SAWG on local RTIO and AD9154-FMC-EBZ platform.add_extension(ad9154_fmc_ebz) self.submodules.transceiver = gtx_7series.GTX_3G( clock_pads=platform.request("ad9154_refclk"), tx_pads=tx_pads, rx_pads=rx_pads, sys_clk_freq=self.clk_freq) ad9154_spi = platform.request("ad9154_spi") self.comb += ad9154_spi.en.eq(1) self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi) self.csr_devices.append("converter_spi") self.config["CONVERTER_SPI_DAC_CS"] = 0 self.config["CONVERTER_SPI_CLK_CS"] = 1 self.config["HAS_AD9516"] = None else: raise ValueError self.submodules.drtio = DRTIOMaster(self.transceiver) self.csr_devices.append("drtio") self.add_wb_slave(mem_decoder(self.mem_map["drtio_aux"]), self.drtio.aux_controller.bus) self.add_memory_region("drtio_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800) self.comb += [ platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx")), platform.request("user_sma_clock_n").eq(ClockSignal("rtio")) ] rtio_clk_period = 1e9 / self.transceiver.rtio_clk_freq platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period) platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.transceiver.txoutclk, self.transceiver.rxoutclk) rtio_channels = [] for i in range(8): phy = ttl_simple.Output(platform.request("user_led", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for sma in "user_sma_gpio_p", "user_sma_gpio_n": phy = ttl_simple.Inout(platform.request(sma)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.submodules.rtio_core = rtio.Core(rtio_channels, 3) self.csr_devices.append("rtio_core") self.submodules.rtio = rtio.KernelInitiator() self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if()) self.register_kernel_cpu_csrdevice("rtio") self.register_kernel_cpu_csrdevice("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( [self.rtio.cri, self.rtio_dma.cri], [self.drtio.cri, self.rtio_core.cri])
def __init__(self, cfg, **kwargs): BaseSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", l2_size=128*1024, ident=artiq_version, **kwargs) platform = self.platform rtio_channels = [] for i in range(8): phy = ttl_simple.Output(platform.request("user_led", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for sma in "user_sma_gpio_p", "user_sma_gpio_n": phy = ttl_simple.Inout(platform.request(sma)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.comb += platform.request("sfp_tx_disable_n").eq(1) if cfg == "simple_gbe": # GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock # simple TTLs transceiver = gtx_7series.GTX_1000BASE_BX10 elif cfg == "sawg_3g": # 3Gb link, 150MHz RTIO clock # with SAWG on local RTIO and AD9154-FMC-EBZ platform.add_extension(ad9154_fmc_ebz) ad9154_spi = platform.request("ad9154_spi") self.comb += ad9154_spi.en.eq(1) self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi) self.csr_devices.append("converter_spi") self.config["CONVERTER_SPI_DAC_CS"] = 0 self.config["CONVERTER_SPI_CLK_CS"] = 1 self.config["HAS_AD9516"] = None transceiver = gtx_7series.GTX_3G else: raise ValueError self.submodules.transceiver = transceiver( clock_pads=platform.request("si5324_clkout"), tx_pads=platform.request("sfp_tx"), rx_pads=platform.request("sfp_rx"), sys_clk_freq=self.clk_freq) self.submodules.rx_synchronizer = gtx_7series.RXSynchronizer( self.transceiver.rtio_clk_freq, initial_phase=180.0) self.submodules.drtio = DRTIOSatellite( self.transceiver, rtio_channels, self.rx_synchronizer) self.csr_devices.append("rx_synchronizer") self.csr_devices.append("drtio") self.add_wb_slave(mem_decoder(self.mem_map["drtio_aux"]), self.drtio.aux_controller.bus) self.add_memory_region("drtio_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800) self.config["RTIO_FREQUENCY"] = str(self.transceiver.rtio_clk_freq/1e6) si5324_clkin = platform.request("si5324_clkin") self.specials += \ Instance("OBUFDS", i_I=ClockSignal("rtio_rx"), o_O=si5324_clkin.p, o_OB=si5324_clkin.n ) self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None self.comb += [ platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx")), platform.request("user_sma_clock_n").eq(ClockSignal("rtio")) ] rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period) platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( platform.lookup_request("clk200"), self.transceiver.txoutclk, self.transceiver.rxoutclk)