def __init__(self, dw, nrxslots=2, ntxslots=2, endianness="big"): self.sink = stream.Endpoint(eth_phy_layout(dw)) self.source = stream.Endpoint(eth_phy_layout(dw)) self.bus = wishbone.Interface(data_width=dw, adr_width=32-log2_int(dw//8)) # # # # storage in SRAM sram_depth = eth_mtu//(dw//8) self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots, endianness) self.comb += [ self.sink.connect(self.sram.sink), self.sram.source.connect(self.source) ] # Wishbone interface wb_rx_sram_ifs = [wishbone.SRAM(self.sram.writer.mems[n], read_only=True, data_width=dw) for n in range(nrxslots)] # TODO: FullMemoryWE should move to Mibuild wb_tx_sram_ifs = [FullMemoryWE()(wishbone.SRAM(self.sram.reader.mems[n], read_only=False, data_width=dw)) for n in range(ntxslots)] wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs wb_slaves = [] decoderoffset = log2_int(sram_depth, need_pow2=False) decoderbits = log2_int(len(wb_sram_ifs)) for n, wb_sram_if in enumerate(wb_sram_ifs): def slave_filter(a, v=n): return a[decoderoffset:decoderoffset+decoderbits] == v wb_slaves.append((slave_filter, wb_sram_if.bus)) self.submodules += wb_sram_if wb_con = wishbone.Decoder(self.bus, wb_slaves, register=True) self.submodules += wb_con
def __init__(self): self.sink = sink = stream.Endpoint( etherbone_packet_user_description(32)) self.source = source = stream.Endpoint( etherbone_packet_user_description(32)) # # # # receive record, decode it and generate mmap stream self.submodules.depacketizer = depacketizer = _EtherboneRecordDepacketizer( ) self.submodules.receiver = receiver = _EtherboneRecordReceiver() self.comb += [ sink.connect(depacketizer.sink), depacketizer.source.connect(receiver.sink) ] # receive mmap stream, encode it and send records self.submodules.sender = sender = _EtherboneRecordSender() self.submodules.packetizer = packetizer = _EtherboneRecordPacketizer() self.comb += [ sender.source.connect(packetizer.sink), packetizer.source.connect(source), source.length.eq(etherbone_record_header.length + (sender.source.wcount != 0) * 4 + sender.source.wcount * 4 + (sender.source.rcount != 0) * 4 + sender.source.rcount * 4) ]
def __init__(self, bus=None): if bus is None: bus = wishbone.Interface self.bus = bus aw = len(bus.adr) dw = len(bus.dat_w) self.sink = stream.Endpoint([("address", aw)]) self.source = stream.Endpoint([("data", dw)]) # # # bus_stb = Signal() data_reg_loaded = Signal() self.comb += [ bus_stb.eq(self.sink.stb & (~data_reg_loaded | self.source.ack)), bus.cyc.eq(bus_stb), bus.stb.eq(bus_stb), bus.adr.eq(self.sink.address), self.sink.ack.eq(bus.ack), self.source.stb.eq(data_reg_loaded), ] self.sync += [ If(self.source.ack, data_reg_loaded.eq(0)), If(bus.ack, data_reg_loaded.eq(1), self.source.data.eq(bus.dat_r), self.source.eop.eq(self.sink.eop)) ]
def __init__(self, sink_description, source_description, header): self.sink = sink = stream.Endpoint(sink_description) self.source = source = stream.Endpoint(source_description) self.header = Signal(header.length * 8) # # # dw = len(self.sink.data) header_reg = Signal(header.length * 8, reset_less=True) header_words = (header.length * 8) // dw load = Signal() shift = Signal() counter = Signal(max=max(header_words, 2)) counter_reset = Signal() counter_ce = Signal() self.sync += \ If(counter_reset, counter.eq(0) ).Elif(counter_ce, counter.eq(counter + 1) ) self.comb += header.encode(sink, self.header) if header_words == 1: self.sync += [If(load, header_reg.eq(self.header))] else: self.sync += [ If(load, header_reg.eq(self.header)).Elif( shift, header_reg.eq(Cat(header_reg[dw:], Signal(dw)))) ] fsm = FSM(reset_state="IDLE") self.submodules += fsm if header_words == 1: idle_next_state = "COPY" else: idle_next_state = "SEND_HEADER" fsm.act( "IDLE", sink.ack.eq(1), counter_reset.eq(1), If( sink.stb, sink.ack.eq(0), source.stb.eq(1), source.eop.eq(0), source.data.eq(self.header[:dw]), If(source.stb & source.ack, load.eq(1), NextState(idle_next_state)))) if header_words != 1: fsm.act( "SEND_HEADER", source.stb.eq(1), source.eop.eq(0), source.data.eq(header_reg[dw:2 * dw]), If(source.stb & source.ack, shift.eq(1), counter_ce.eq(1), If(counter == header_words - 2, NextState("COPY")))) if hasattr(sink, "error"): self.comb += source.error.eq(sink.error) fsm.act( "COPY", source.stb.eq(sink.stb), source.eop.eq(sink.eop), source.data.eq(sink.data), If(source.stb & source.ack, sink.ack.eq(1), If(source.eop, NextState("IDLE"))))
def __init__(self, dw, ack_on_gap=False): self.sink = sink = stream.Endpoint(eth_phy_layout(dw)) self.source = source = stream.Endpoint(eth_phy_layout(dw)) # # # gap = math.ceil(eth_interpacket_gap/(dw//8)) counter = Signal(max=gap) counter_reset = Signal() counter_ce = Signal() self.sync += \ If(counter_reset, counter.eq(0) ).Elif(counter_ce, counter.eq(counter + 1) ) self.submodules.fsm = fsm = FSM(reset_state="COPY") fsm.act("COPY", counter_reset.eq(1), sink.connect(source), If(sink.stb & sink.eop & sink.ack, NextState("GAP") ) ) fsm.act("GAP", counter_ce.eq(1), sink.ack.eq(int(ack_on_gap)), If(counter == (gap-1), NextState("COPY") ) )
def __init__(self): self.sink = sink = stream.Endpoint(eth_phy_layout(8)) self.source = source = stream.Endpoint(eth_phy_layout(8)) # # # self.comb += [sink.connect(source), source.last_be.eq(sink.eop)]
def __init__(self, dw): assert dw == 8 self.sink = sink = stream.Endpoint(eth_phy_layout(dw)) self.source = source = stream.Endpoint(eth_phy_layout(dw)) self.error = Signal() # # # fsm = FSM(reset_state="IDLE") self.submodules += fsm fsm.act( "IDLE", sink.ack.eq(1), If(sink.stb & ~sink.eop & (sink.data == eth_preamble >> 56), NextState("COPY")), If(sink.stb & sink.eop, self.error.eq(1))) self.comb += [ source.data.eq(sink.data), source.last_be.eq(sink.last_be) ] fsm.act("COPY", sink.connect(source, omit={"data", "last_be"}), If( source.stb & source.eop & source.ack, NextState("IDLE"), ))
def __init__(self, enable=True): self.sink = sink = stream.Endpoint([("d", 32), ("k", 4)]) self.source = source = stream.Endpoint([("data", 32)]) # # # if enable: # descrambler descrambler = _Scrambler(32) self.submodules += descrambler self.comb += descrambler.i.eq(sink.d) # detect K29.7 and synchronize descrambler self.comb += [ descrambler.reset.eq(0), If((sink.k[0] == 1) & (sink.d[:8] == K(29, 7)), sink.ack.eq(1), descrambler.reset.eq(1)).Else(sink.ack.eq(source.ack), source.stb.eq(sink.stb), source.data.eq(descrambler.o)) ] else: self.comb += [ sink.connect(source, omit={"d", "k"}), source.data.eq(sink.d) ]
def __init__(self, sync_interval=1024, enable=True): self.sink = sink = stream.Endpoint([("data", 32)]) self.source = source = stream.Endpoint([("d", 32), ("k", 4)]) # # # if enable: # scrambler scrambler = _Scrambler(32) self.submodules += scrambler self.comb += scrambler.i.eq(sink.data) # insert K.29.7 as sync character # every sync_interval cycles count = Signal(max=sync_interval) self.sync += count.eq(count + 1) self.comb += [ If(count == 0, scrambler.reset.eq(1), source.stb.eq(1), source.k[0].eq(1), source.d[:8].eq(K(29, 7))).Else(sink.ack.eq(source.ack), source.stb.eq(sink.stb), source.d.eq(scrambler.o)) ] else: self.comb += [ sink.connect(source, omit={"data"}), source.k.eq(0b0000), source.d.eq(sink.data) ]
def __init__(self): self.sink = sink = stream.Endpoint( etherbone_packet_user_description(32)) self.source = source = stream.Endpoint(user_description(32)) # # # self.submodules.packetizer = packetizer = _EtherbonePacketPacketizer() self.comb += [ packetizer.sink.stb.eq(sink.stb), packetizer.sink.eop.eq(sink.eop), sink.ack.eq(packetizer.sink.ack), packetizer.sink.magic.eq(etherbone_magic), packetizer.sink.port_size.eq(32 // 8), packetizer.sink.addr_size.eq(32 // 8), packetizer.sink.nr.eq(sink.nr), packetizer.sink.version.eq(etherbone_version), packetizer.sink.data.eq(sink.data) ] self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act( "IDLE", packetizer.source.ack.eq(1), If(packetizer.source.stb, packetizer.source.ack.eq(0), NextState("SEND"))) fsm.act("SEND", packetizer.source.connect(source), source.length.eq(sink.length + etherbone_packet_header.length), If(source.stb & source.eop & source.ack, NextState("IDLE")))
def __init__(self): self.sink = sink = stream.Endpoint(user_description(32)) self.source = source = stream.Endpoint( etherbone_packet_user_description(32)) # # # self.submodules.depacketizer = depacketizer = _EtherbonePacketDepacketizer( ) self.comb += sink.connect(depacketizer.sink) self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act( "IDLE", depacketizer.source.ack.eq(1), If(depacketizer.source.stb, depacketizer.source.ack.eq(0), NextState("CHECK"))) stb = Signal() self.sync += stb.eq(depacketizer.source.stb & (depacketizer.source.magic == etherbone_magic)) fsm.act("CHECK", If(stb, NextState("PRESENT")).Else(NextState("DROP"))) self.comb += [ source.eop.eq(depacketizer.source.eop), source.nr.eq(depacketizer.source.nr), source.data.eq(depacketizer.source.data), source.length.eq(sink.length - etherbone_packet_header.length) ] fsm.act("PRESENT", source.stb.eq(depacketizer.source.stb), depacketizer.source.ack.eq(source.ack), If(source.stb & source.eop & source.ack, NextState("IDLE"))) fsm.act( "DROP", depacketizer.source.ack.eq(1), If( depacketizer.source.stb & depacketizer.source.eop & depacketizer.source.ack, NextState("IDLE")))
def __init__(self, syncword): self.sink = stream.Endpoint([ ("data", 8), ]) self.source = stream.Endpoint([ ("data", 8), ]) ### self.submodules.fsm = FSM(reset_state="DATA") self.fsm.act( "DATA", self.source.payload.data.eq(self.sink.payload.data), self.source.stb.eq(self.sink.stb), self.sink.ack.eq(self.source.ack), If( self.sink.stb & self.sink.ack & self.sink.eop, NextState("SYNC"), ), ) self.fsm.act( "SYNC", self.source.payload.data.eq(syncword), self.source.stb.eq(1), self.sink.ack.eq(0), If( self.source.stb & self.source.ack, NextState("DATA"), ), )
def __init__(self, dw, padding): self.sink = sink = stream.Endpoint(eth_phy_layout(dw)) self.source = source = stream.Endpoint(eth_phy_layout(dw)) # # # padding_limit = math.ceil(padding / (dw / 8)) - 1 counter = Signal(16, reset=1) counter_done = Signal() counter_reset = Signal() counter_ce = Signal() self.sync += \ If(counter_reset, counter.eq(0) ).Elif(counter_ce, counter.eq(counter + 1) ) self.comb += counter_done.eq(counter >= padding_limit) self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act( "IDLE", sink.connect(source), If( source.stb & source.ack, counter_ce.eq(1), If( sink.eop, If(~counter_done, source.eop.eq(0), NextState("PADDING")).Else(counter_reset.eq(1))))) fsm.act( "PADDING", source.stb.eq(1), source.eop.eq(counter_done), source.data.eq(0), If(source.stb & source.ack, counter_ce.eq(1), If(counter_done, counter_reset.eq(1), NextState("IDLE"))))
def __init__(self): self.sink = sink = stream.Endpoint(etherbone_mmap_description(32)) self.source = source = stream.Endpoint(etherbone_mmap_description(32)) self.bus = bus = wishbone.Interface() # # # data = Signal(32) data_update = Signal() self.sync += If(data_update, data.eq(bus.dat_r)) self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act( "IDLE", sink.ack.eq(1), If( sink.stb, sink.ack.eq(0), If(sink.we, NextState("WRITE_DATA")).Else(NextState("READ_DATA")))) fsm.act( "WRITE_DATA", bus.adr.eq(sink.addr), bus.dat_w.eq(sink.data), bus.sel.eq(sink.be), bus.stb.eq(sink.stb), bus.we.eq(1), bus.cyc.eq(1), If(bus.stb & bus.ack, sink.ack.eq(1), If(sink.eop, NextState("IDLE")))) fsm.act( "READ_DATA", bus.adr.eq(sink.addr), bus.sel.eq(sink.be), bus.stb.eq(sink.stb), bus.cyc.eq(1), If(bus.stb & bus.ack, data_update.eq(1), NextState("SEND_DATA"))) fsm.act( "SEND_DATA", source.stb.eq(sink.stb), source.eop.eq(sink.eop), source.base_addr.eq(sink.base_addr), source.addr.eq(sink.addr), source.count.eq(sink.count), source.be.eq(sink.be), source.we.eq(1), source.data.eq(data), If(source.stb & source.ack, sink.ack.eq(1), If(source.eop, NextState("IDLE")).Else(NextState("READ_DATA"))))
def __init__(self): self.enable = Signal() self.sink = sink = stream.Endpoint([("d", 32), ("k", 4)]) self.source = source = stream.Endpoint([("data", 32)]) # # # # descrambler self.submodules.descrambler = descrambler = _Scrambler(32) self.comb += descrambler.i.eq(sink.d) # detect K29.7 and synchronize descrambler self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="DISABLE")) self.comb += fsm.reset.eq(~self.enable) fsm.act("DISABLE", sink.connect(source, omit={"d", "k"}), source.data.eq(sink.d), NextState("SYNC_DATA") ) fsm.act("SYNC_DATA", If((sink.k[0] == 1) & (sink.d[:8] == K(29,7)), sink.ack.eq(1), descrambler.reset.eq(1) ).Else( sink.ack.eq(source.ack), source.stb.eq(sink.stb), source.data.eq(descrambler.o), If(source.stb & source.ack, descrambler.ce.eq(1) ) ) )
def __init__(self): self.sink = sink = stream.Endpoint([("d", 32), ("k", 4)]) self.source = source = stream.Endpoint([("data", 32)]) # # # # Descrambler self.submodules.descrambler = descrambler = _Scrambler(32) self.comb += descrambler.i.eq(sink.d) # Detect K29.7 SYNC character and synchronize Descrambler self.comb += \ If(sink.stb, If((sink.k == 0b1) & (sink.d == K(29,7)), sink.ack.eq(1), descrambler.reset.eq(1) ).Else( source.stb.eq(1), source.data.eq(descrambler.o), If(source.ack, sink.ack.eq(1), descrambler.ce.eq(1) ) ) )
def __init__(self, device, pads, mode="master", init_timeout=2**16): self.sink = sink = stream.Endpoint([("data", 32)]) self.source = source = stream.Endpoint([("data", 32)]) assert mode in ["master", "slave"] self.submodules.serdes = _Serdes(pads, mode) if mode == "master": self.submodules.init = _SerdesMasterInit(self.serdes, init_timeout) else: self.submodules.init = _SerdesSlaveInit(self.serdes, init_timeout) self.submodules.control = _SerdesControl(self.serdes, self.init, mode) # tx/rx dataflow self.comb += [ If(self.init.ready, If( sink.stb, sink.connect(self.serdes.tx.sink), ), self.serdes.rx.source.connect(source)).Else( self.serdes.rx.source.ack.eq(1)), self.serdes.tx.sink.stb.eq(1) # always transmitting ] # For PRBS test we are using the scrambler/descrambler as PRBS, # sending 0 to the scrambler and checking that descrambler # output is always 0. self.comb += self.control.prbs_error.eq(source.stb & source.ack & (source.data != 0))
def __init__(self, buffer_depth=256): self.sink = sink = stream.Endpoint(etherbone_mmap_description(32)) self.source = source = stream.Endpoint( etherbone_record_description(32)) # # # pbuffer = stream.SyncFIFO(etherbone_mmap_description(32), buffer_depth, buffered=True) self.submodules += pbuffer self.comb += sink.connect(pbuffer.sink) self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act( "IDLE", pbuffer.source.ack.eq(1), If(pbuffer.source.stb, pbuffer.source.ack.eq(0), NextState("SEND_BASE_ADDRESS"))) self.comb += [ source.byte_enable.eq(pbuffer.source.be), If(pbuffer.source.we, source.wcount.eq(pbuffer.source.count)).Else( source.rcount.eq(pbuffer.source.count)) ] fsm.act("SEND_BASE_ADDRESS", source.stb.eq(pbuffer.source.stb), source.eop.eq(0), source.data.eq(pbuffer.source.base_addr), If(source.ack, NextState("SEND_DATA"))) fsm.act( "SEND_DATA", source.stb.eq(pbuffer.source.stb), source.eop.eq(pbuffer.source.eop), source.data.eq(pbuffer.source.data), If(source.stb & source.ack, pbuffer.source.ack.eq(1), If(source.eop, NextState("IDLE"))))
def __init__(self, buffer_depth=256): self.sink = sink = stream.Endpoint(etherbone_record_description(32)) self.source = source = stream.Endpoint(etherbone_mmap_description(32)) # # # fifo = stream.SyncFIFO(etherbone_record_description(32), buffer_depth, buffered=True) self.submodules += fifo self.comb += sink.connect(fifo.sink) base_addr = Signal(32) base_addr_update = Signal() self.sync += If(base_addr_update, base_addr.eq(fifo.source.data)) counter = Signal(max=512) counter_reset = Signal() counter_ce = Signal() self.sync += \ If(counter_reset, counter.eq(0) ).Elif(counter_ce, counter.eq(counter + 1) ) self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act( "IDLE", fifo.source.ack.eq(1), counter_reset.eq(1), If( fifo.source.stb, base_addr_update.eq(1), If(fifo.source.wcount, NextState("RECEIVE_WRITES")).Elif( fifo.source.rcount, NextState("RECEIVE_READS")))) fsm.act( "RECEIVE_WRITES", source.stb.eq(fifo.source.stb), source.eop.eq(counter == fifo.source.wcount - 1), source.count.eq(fifo.source.wcount), source.be.eq(fifo.source.byte_enable), source.addr.eq(base_addr[2:] + counter), source.we.eq(1), source.data.eq(fifo.source.data), fifo.source.ack.eq(source.ack), If( source.stb & source.ack, counter_ce.eq(1), If( source.eop, If(fifo.source.rcount, NextState("RECEIVE_BASE_RET_ADDR")).Else( NextState("IDLE"))))) fsm.act( "RECEIVE_BASE_RET_ADDR", counter_reset.eq(1), If(fifo.source.stb, base_addr_update.eq(1), NextState("RECEIVE_READS"))) fsm.act( "RECEIVE_READS", source.stb.eq(fifo.source.stb), source.eop.eq(counter == fifo.source.rcount - 1), source.count.eq(fifo.source.rcount), source.base_addr.eq(base_addr), source.addr.eq(fifo.source.data[2:]), fifo.source.ack.eq(source.ack), If(source.stb & source.ack, counter_ce.eq(1), If(source.eop, NextState("IDLE"))))
def __init__(self, crc_class, layout): self.sink = sink = stream.Endpoint(layout) self.source = source = stream.Endpoint(layout) # # # dw = len(sink.data) crc = crc_class(dw) self.submodules += crc ratio = crc.width//dw fifo = ResetInserter()(stream.SyncFIFO(layout, ratio + 1)) self.submodules += fifo fsm = FSM(reset_state="RESET") self.submodules += fsm fifo_in = Signal() fifo_out = Signal() fifo_full = Signal() self.comb += [ fifo_full.eq(fifo.fifo.level == ratio), fifo_in.eq(sink.stb & (~fifo_full | fifo_out)), fifo_out.eq(source.stb & source.ack), sink.connect(fifo.sink), fifo.sink.stb.eq(fifo_in), self.sink.ack.eq(fifo_in), source.stb.eq(sink.stb & fifo_full), source.eop.eq(sink.eop), fifo.source.ack.eq(fifo_out), source.payload.eq(fifo.source.payload), source.error.eq(sink.error | crc.error), ] fsm.act("RESET", crc.reset.eq(1), fifo.reset.eq(1), NextState("IDLE"), ) self.comb += crc.data.eq(sink.data) fsm.act("IDLE", If(sink.stb & sink.ack, crc.ce.eq(1), NextState("COPY") ) ) fsm.act("COPY", If(sink.stb & sink.ack, crc.ce.eq(1), If(sink.eop, NextState("RESET") ) ) )
def __init__(self, dw, packet_min_length): self.sink = sink = stream.Endpoint(eth_phy_layout(dw)) self.source = source = stream.Endpoint(eth_phy_layout(dw)) # # # # TODO: see if we should drop the packet when # payload size < minimum ethernet payload size self.comb += sink.connect(source)
def __init__(self, crc_class, layout): self.sink = sink = stream.Endpoint(layout) self.source = source = stream.Endpoint(layout) # # # dw = len(sink.data) crc = crc_class(dw) fsm = FSM(reset_state="IDLE") self.submodules += crc, fsm fsm.act("IDLE", crc.reset.eq(1), sink.ack.eq(1), If(sink.stb, sink.ack.eq(0), NextState("COPY"), ) ) fsm.act("COPY", crc.ce.eq(sink.stb & source.ack), crc.data.eq(sink.data), sink.connect(source), source.eop.eq(0), If(sink.stb & sink.eop & source.ack, NextState("INSERT"), ) ) ratio = crc.width//dw if ratio > 1: cnt = Signal(max=ratio, reset=ratio-1) cnt_done = Signal() fsm.act("INSERT", source.stb.eq(1), chooser(crc.value, cnt, source.data, reverse=True), If(cnt_done, source.eop.eq(1), If(source.ack, NextState("IDLE")) ) ) self.comb += cnt_done.eq(cnt == 0) self.sync += \ If(fsm.ongoing("IDLE"), cnt.eq(cnt.reset) ).Elif(fsm.ongoing("INSERT") & ~cnt_done, cnt.eq(cnt - source.ack) ) else: fsm.act("INSERT", source.stb.eq(1), source.eop.eq(1), source.data.eq(crc.value), If(source.ack, NextState("IDLE")) )
def __init__(self, device, pads, mode="master", init_timeout=2**14): self.sink = sink = stream.Endpoint([("data", 32)]) self.source = source = stream.Endpoint([("data", 32)]) assert mode in ["master", "slave"] if device[:4] == "xcku": taps = 512 self.submodules.serdes = KUSSerdes(pads, mode) elif device[:4] == "xc7a": taps = 32 self.submodules.serdes = S7Serdes(pads, mode) else: raise NotImplementedError if mode == "master": self.submodules.init = _SerdesMasterInit(self.serdes, taps, init_timeout) else: self.submodules.init = _SerdesSlaveInit(self.serdes, taps, init_timeout) self.submodules.control = _SerdesControl(self.serdes, self.init, mode) # scrambling scrambler = Scrambler() descrambler = Descrambler() self.submodules += scrambler, descrambler self.comb += [ scrambler.enable.eq(self.control.scrambling_enable.storage), descrambler.enable.eq(self.control.scrambling_enable.storage) ] # tx dataflow self.comb += \ If(self.init.ready, sink.connect(scrambler.sink), scrambler.source.ack.eq(self.serdes.tx_ce), If(scrambler.source.stb, self.serdes.tx_d.eq(scrambler.source.d), self.serdes.tx_k.eq(scrambler.source.k) ) ) # rx dataflow self.comb += [ If(self.init.ready, descrambler.sink.stb.eq(self.serdes.rx_ce), descrambler.sink.d.eq(self.serdes.rx_d), descrambler.sink.k.eq(self.serdes.rx_k), descrambler.source.connect(source)), # For PRBS test we are using the scrambler/descrambler as PRBS, # sending 0 to the scrambler and checking that descrambler # output is always 0. self.control.prbs_error.eq(descrambler.source.stb & descrambler.source.ack & (descrambler.source.data != 0)) ]
def __init__(self, clk_freq, timeout=10): self.sink = sink = stream.Endpoint(phy_description(32)) self.source = source = stream.Endpoint(user_description(32)) # # # count = Signal(len(source.length)) length = Signal(len(source.length)) # Packet description # - preamble : 4 bytes # - length : 4 bytes # - payload fsm = FSM(reset_state="PREAMBLE") self.submodules += fsm timer = WaitTimer(clk_freq*timeout) self.submodules += timer fsm.act("PREAMBLE", sink.ack.eq(1), If(sink.stb & (sink.data == 0x5aa55aa5), NextState("LENGTH") ) ) fsm.act("LENGTH", sink.ack.eq(1), If(sink.stb, NextValue(count, 0), NextValue(length, sink.data), NextState("DATA") ), timer.wait.eq(1) ) fsm.act("DATA", source.stb.eq(sink.stb), source.eop.eq(count == (length[2:] - 1)), source.length.eq(length), source.data.eq(sink.data), sink.ack.eq(source.ack), If(timer.done, NextState("PREAMBLE") ).Elif(source.stb & source.ack, NextValue(count, count + 1), If(source.eop, NextState("PREAMBLE") ) ), timer.wait.eq(1) )
def __init__(self, dw): self.sink = stream.Endpoint(eth_phy_layout(dw)) self.source = stream.Endpoint(eth_phy_layout(dw)) # # # preamble = Signal(64, reset=eth_preamble) cnt_max = (64//dw)-1 cnt = Signal(max=cnt_max+1) clr_cnt = Signal() inc_cnt = Signal() self.sync += \ If(clr_cnt, cnt.eq(0) ).Elif(inc_cnt, cnt.eq(cnt+1) ) fsm = FSM(reset_state="IDLE") self.submodules += fsm fsm.act("IDLE", self.sink.ack.eq(1), clr_cnt.eq(1), If(self.sink.stb, self.sink.ack.eq(0), NextState("INSERT"), ) ) fsm.act("INSERT", self.source.stb.eq(1), chooser(preamble, cnt, self.source.data), If(cnt == cnt_max, If(self.source.ack, NextState("COPY")) ).Else( inc_cnt.eq(self.source.ack) ) ) self.comb += [ self.source.data.eq(self.sink.data), self.source.last_be.eq(self.sink.last_be) ] fsm.act("COPY", self.sink.connect(self.source, leave_out=set(["data", "last_be"])), If(self.sink.stb & self.sink.eop & self.source.ack, NextState("IDLE"), ) )
def __init__(self, lasmim, fifo_depth=None): self.address = stream.Endpoint([("a", lasmim.aw)]) self.data = stream.Endpoint([("d", lasmim.dw)]) self.busy = Signal() ### if fifo_depth is None: fifo_depth = lasmim.req_queue_size + lasmim.read_latency + 2 # request issuance request_enable = Signal() request_issued = Signal() self.comb += [ lasmim.we.eq(0), lasmim.stb.eq(self.address.stb & request_enable), lasmim.adr.eq(self.address.a), self.address.ack.eq(lasmim.req_ack & request_enable), request_issued.eq(lasmim.stb & lasmim.req_ack) ] # FIFO reservation level counter # incremented when data is planned to be queued # decremented when data is dequeued data_dequeued = Signal() rsv_level = Signal(max=fifo_depth + 1) self.sync += [ If(request_issued, If(~data_dequeued, rsv_level.eq(rsv_level + 1))).Elif( data_dequeued, rsv_level.eq(rsv_level - 1)) ] self.comb += [ self.busy.eq(rsv_level != 0), request_enable.eq(rsv_level != fifo_depth) ] # FIFO fifo = SyncFIFO(lasmim.dw, fifo_depth) self.submodules += fifo self.comb += [ fifo.din.eq(lasmim.dat_r), fifo.we.eq(lasmim.dat_r_ack), self.data.stb.eq(fifo.readable), fifo.re.eq(self.data.ack), self.data.d.eq(fifo.dout), data_dequeued.eq(self.data.stb & self.data.ack) ]
def __init__(self, clk_freq, timeout=10): self.sink = sink = stream.Endpoint(phy_description(32)) self.source = source = stream.Endpoint(user_description(32)) # # # # Packet description # - preamble : 4 bytes # - length : 4 bytes # - payload fsm = FSM(reset_state="IDLE") self.submodules += fsm self.submodules.timer = WaitTimer(clk_freq*timeout) self.comb += self.timer.wait.eq(~fsm.ongoing("IDLE")) fsm.act("IDLE", sink.ack.eq(1), If(sink.stb & (sink.data == 0x5aa55aa5), NextState("RECEIVE_LENGTH") ) ) fsm.act("RECEIVE_LENGTH", sink.ack.eq(1), If(sink.stb, NextValue(source.length, sink.data), NextState("COPY") ) ) eop = Signal() cnt = Signal(32) fsm.act("COPY", source.stb.eq(sink.stb), source.eop.eq(eop), source.data.eq(sink.data), sink.ack.eq(source.ack), If((source.stb & source.ack & eop) | self.timer.done, NextState("IDLE") ) ) self.sync += \ If(fsm.ongoing("IDLE"), cnt.eq(0) ).Elif(source.stb & source.ack, cnt.eq(cnt + 1) ) self.comb += eop.eq(cnt == source.length[2:] - 1)
def __init__(self, pads, mode): self.source = source = stream.Endpoint(eth_phy_layout(8)) # # # pads_d = Record(rx_pads_layout) self.sync += [ pads_d.rx_dv.eq(pads.rx_dv), pads_d.rx_data.eq(pads.rx_data) ] gmii_rx = LiteEthPHYGMIIRX(pads_d) self.submodules += gmii_rx mii_rx = LiteEthPHYMIIRX(pads_d) self.submodules += mii_rx mux = stream.Multiplexer(eth_phy_layout(8), 2) self.submodules += mux self.comb += [ mux.sel.eq(mode == modes["MII"]), gmii_rx.source.connect(mux.sink0), mii_rx.source.connect(mux.sink1), mux.source.connect(source) ]
def __init__(self, pads, mode): self.sink = sink = stream.Endpoint(eth_phy_layout(8)) # # # gmii_tx_pads = Record(tx_pads_layout) gmii_tx = LiteEthPHYGMIITX(gmii_tx_pads) self.submodules += gmii_tx mii_tx_pads = Record(tx_pads_layout) mii_tx = LiteEthPHYMIITX(mii_tx_pads) self.submodules += mii_tx demux = stream.Demultiplexer(eth_phy_layout(8), 2) self.submodules += demux self.comb += [ demux.sel.eq(mode == modes["MII"]), sink.connect(demux.sink), demux.source0.connect(gmii_tx.sink), demux.source1.connect(mii_tx.sink), ] if hasattr(pads, "tx_er"): self.comb += pads.tx_er.eq(0) self.sync += [ If( mode == modes["MII"], pads.tx_en.eq(mii_tx_pads.tx_en), pads.tx_data.eq(mii_tx_pads.tx_data), ).Else( pads.tx_en.eq(gmii_tx_pads.tx_en), pads.tx_data.eq(gmii_tx_pads.tx_data), ) ]
def __init__(self, pads): self.sink = sink = stream.Endpoint(eth_phy_layout(8)) # # # self.specials += Instance( "ODDR2", p_DDR_ALIGNMENT="C0", p_INIT=0, p_SRTYPE="ASYNC", i_C0=ClockSignal("eth_tx"), i_C1=~ClockSignal("eth_tx"), i_CE=1, i_S=0, i_R=0, i_D0=sink.stb, i_D1=sink.stb, o_Q=pads.tx_ctl, ) for i in range(4): self.specials += Instance( "ODDR2", p_DDR_ALIGNMENT="C0", p_INIT=0, p_SRTYPE="ASYNC", i_C0=ClockSignal("eth_tx"), i_C1=~ClockSignal("eth_tx"), i_CE=1, i_S=0, i_R=0, i_D0=sink.data[i], i_D1=sink.data[4 + i], o_Q=pads.tx_data[i], ) self.comb += sink.ack.eq(1)