def __init__(self, lasmim):
self._magic = CSRStatus(16)
self._reset = CSR()
self._shoot = CSR()
self.submodules._dma = DMAWriteController(dma_lasmi.Writer(lasmim),
MODE_EXTERNAL)
###
self.comb += self._magic.status.eq(memtest_magic)
lfsr = LFSR(lasmim.dw)
self.submodules += lfsr
self.comb += lfsr.reset.eq(self._reset.re)
en = Signal()
en_counter = Signal(lasmim.aw)
self.comb += en.eq(en_counter != 0)
self.sync += [
If(self._shoot.re, en_counter.eq(self._dma.length)).Elif(
lfsr.ce, en_counter.eq(en_counter - 1))
]
self.comb += [
self._dma.trigger.eq(self._shoot.re),
self._dma.data.stb.eq(en),
lfsr.ce.eq(en & self._dma.data.ack),
self._dma.data.d.eq(lfsr.o)
]
def __init__(self):
# sdram
sdram_module = MT48LC4M16(75 * 1000000)
sdram_phy_settings = sdram.PhySettings(memtype="SDR",
dfi_databits=1 * 16,
nphases=1,
rdphase=0,
wrphase=0,
rdcmdphase=0,
wrcmdphase=0,
cl=2,
read_latency=4,
write_latency=0)
self.submodules.sdram_phy = SDRAMPHYSim(sdram_module,
sdram_phy_settings)
self.submodules.sdram_core = SDRAMCore(
self.sdram_phy, sdram_module.geom_settings,
sdram_module.timing_settings, LASMIconSettings(with_refresh=False))
# dma writer
self.submodules.dma_writer = dma_lasmi.Writer(
self.sdram_core.crossbar.get_master())
# dma reader
self.submodules.dma_reader = EncoderDMAReader(
self.sdram_core.crossbar.get_master())
self.comb += self.dma_reader.source.ack.eq(1)
def __init__(self):
self.submodules.ctler = LASMIcon(sdram_phy, sdram_geom, sdram_timing)
self.submodules.xbar = lasmibus.Crossbar([self.ctler.lasmic], self.ctler.nrowbits)
self.submodules.logger = DFILogger(self.ctler.dfi)
self.submodules.writer = dma_lasmi.Writer(self.xbar.get_master())
self.comb += self.writer.address_data.stb.eq(1)
pl = self.writer.address_data.payload
pl.a.reset = 255
pl.d.reset = pl.a.reset*2
self.sync += If(self.writer.address_data.ack,
pl.a.eq(pl.a + 1),
pl.d.eq(pl.d + 2)
)
self.open_row = None
def __init__(self, lasmim):
self.sink = sink = Sink(user_description(8))
# Pack data
pack_factor = lasmim.dw // 8
pack = structuring.Pack(phy_description(8), pack_factor, reverse=True)
cast = structuring.Cast(pack.source.payload.layout, lasmim.dw)
# DMA
writer = dma_lasmi.Writer(lasmim)
self._reset = CSR()
self.dma = InsertReset(
spi.DMAWriteController(writer, mode=spi.MODE_SINGLE_SHOT))
self.comb += self.dma.reset.eq(self._reset.r & self._reset.re)
# Remove sop/eop/length/dst fields from payload
self.comb += [
pack.sink.stb.eq(sink.stb),
pack.sink.payload.eq(sink.payload),
sink.ack.eq(pack.sink.ack)
]
# Graph
g = DataFlowGraph()
g.add_pipeline(pack, cast, self.dma)
self.submodules += CompositeActor(g)
# IRQ
self.submodules.ev = EventManager()
self.ev.done = EventSourcePulse()
self.ev.finalize()
self.comb += self.ev.done.trigger.eq(sink.stb & sink.eop)
# CRC
self._crc_failed = CSRStatus()
self.sync += \
If(sink.stb & sink.eop,
self._crc_failed.status.eq(sink.error)
)
def __init__(self, pads, asmiport):
self.submodules.edid = EDID(pads)
self.submodules.clocking = Clocking(pads)
invert = False
try:
s = getattr(pads, "data0")
except AttributeError:
s = getattr(pads, "data0_n")
invert = True
self.submodules.data0_cap = DataCapture(8, invert)
self.comb += [
self.data0_cap.pad.eq(s),
self.data0_cap.serdesstrobe.eq(self.clocking.serdesstrobe)
]
fifo = RenameClockDomains(AsyncFIFO(10, 256), {
"write": "pix",
"read": "sys"
})
self.submodules += fifo
self.comb += [fifo.din.eq(self.data0_cap.d), fifo.we.eq(1)]
pack_factor = asmiport.hub.dw // 16
self.submodules.packer = structuring.Pack([("word", 10), ("pad", 6)],
pack_factor)
self.submodules.cast = structuring.Cast(
self.packer.source.payload.layout, asmiport.hub.dw)
self.submodules.dma = spi.DMAWriteController(dma_lasmi.Writer(lasmim),
spi.MODE_SINGLE_SHOT)
self.comb += [
self.packer.sink.stb.eq(fifo.readable),
fifo.re.eq(self.packer.sink.ack),
self.packer.sink.word.eq(fifo.dout),
self.packer.source.connect_flat(self.cast.sink),
self.cast.source.connect_flat(self.dma.data)
]
def __init__(self, lasmim, nslots):
bus_aw = lasmim.aw
bus_dw = lasmim.dw
alignment_bits = bits_for(bus_dw//8) - 1
fifo_word_width = 24*bus_dw//32
self.frame = Sink([("sof", 1), ("pixels", fifo_word_width)])
self._frame_size = CSRStorage(bus_aw + alignment_bits, alignment_bits=alignment_bits)
self.submodules._slot_array = _SlotArray(nslots, bus_aw, alignment_bits)
self.ev = self._slot_array.ev
###
# address generator + maximum memory word count to prevent DMA buffer overrun
reset_words = Signal()
count_word = Signal()
last_word = Signal()
current_address = Signal(bus_aw)
mwords_remaining = Signal(bus_aw)
self.comb += [
self._slot_array.address_reached.eq(current_address),
last_word.eq(mwords_remaining == 1)
]
self.sync += [
If(reset_words,
current_address.eq(self._slot_array.address),
mwords_remaining.eq(self._frame_size.storage)
).Elif(count_word,
current_address.eq(current_address + 1),
mwords_remaining.eq(mwords_remaining - 1)
)
]
# 24bpp -> 32bpp
memory_word = Signal(bus_dw)
pixbits = []
for i in range(bus_dw//32):
for j in range(3):
b = (i*3+j)*8
pixbits.append(self.frame.pixels[b+6:b+8])
pixbits.append(self.frame.pixels[b:b+8])
pixbits.append(0)
pixbits.append(0)
self.comb += memory_word.eq(Cat(*pixbits))
# bus accessor
self.submodules._bus_accessor = dma_lasmi.Writer(lasmim)
self.comb += [
self._bus_accessor.address_data.a.eq(current_address),
self._bus_accessor.address_data.d.eq(memory_word)
]
# control FSM
fsm = FSM()
self.submodules += fsm
fsm.act("WAIT_SOF",
reset_words.eq(1),
self.frame.ack.eq(~self._slot_array.address_valid | ~self.frame.sof),
If(self._slot_array.address_valid & self.frame.sof & self.frame.stb, NextState("TRANSFER_PIXELS"))
)
fsm.act("TRANSFER_PIXELS",
self.frame.ack.eq(self._bus_accessor.address_data.ack),
If(self.frame.stb,
self._bus_accessor.address_data.stb.eq(1),
If(self._bus_accessor.address_data.ack,
count_word.eq(1),
If(last_word, NextState("EOF"))
)
)
)
fsm.act("EOF",
If(~self._bus_accessor.busy,
self._slot_array.address_done.eq(1),
NextState("WAIT_SOF")
)
)