def __init__(self, platform,
firmware_ram_size=0xa000,
firmware_filename=None,
**kwargs):
clk_freq = 80*1000000
SDRAMSoC.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
sdram_controller_settings=LASMIconSettings(with_bandwidth=True),
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.submodules.dna = dna.DNA()
self.submodules.git_info = git_info.GitInfo()
self.submodules.platform_info = platform_info.PlatformInfo("minispartan6"[:8], self.__class__.__name__[:8])
if not self.integrated_main_ram_size:
self.submodules.ddrphy = gensdrphy.GENSDRPHY(platform.request("sdram"),
AS4C16M16(clk_freq))
self.register_sdram_phy(self.ddrphy)
self.submodules.spiflash = spiflash.SpiFlash(
platform.request("spiflash2x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size
self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.gateware_size)
def __init__(self,
platform,
sdram_controller_settings=LASMIconSettings(),
clk_freq=(83 + Fraction(1, 3)) * 1000 * 1000,
**kwargs):
SDRAMSoC.__init__(
self,
platform,
clk_freq,
cpu_reset_address=0x170000, # 1.5 MB
sdram_controller_settings=sdram_controller_settings,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(
platform.request("ddram"),
MT46H32M16(self.clk_freq),
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.register_sdram_phy(self.ddrphy)
if not self.integrated_rom_size:
self.submodules.spiflash = spiflash.SpiFlash(
platform.request("spiflash4x"), dummy=10, div=4)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.flash_boot_address = 0x180000
self.register_rom(self.spiflash.bus, 0x1000000)
def __init__(self, platform,
firmware_ram_size=0xa000,
firmware_filename=None,
**kwargs):
clk_freq = 50*1000000
SDRAMSoC.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
sdram_controller_settings=LASMIconSettings(l2_size=32, with_bandwidth=True),
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.submodules.i2c = i2c.I2C(platform.request("i2c"))
self.submodules.firmware_ram = wishbone.SRAM(firmware_ram_size, init=_get_firmware_data(firmware_filename))
self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size)
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"])
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY(platform.request("ddram"),
MT41J128M16(self.clk_freq),
rd_bitslip=0,
wr_bitslip=4,
dqs_ddr_alignment="C0")
self.comb += [
self.ddrphy.clk8x_wr_strb.eq(self.crg.clk8x_wr_strb),
self.ddrphy.clk8x_rd_strb.eq(self.crg.clk8x_rd_strb),
]
self.register_sdram_phy(self.ddrphy)
self.specials += Keep(self.crg.cd_sys.clk)
platform.add_platform_command("""
NET "{sys_clk}" TNM_NET = "GRPsys_clk";
""", sys_clk=self.crg.cd_sys.clk)
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
SDRAMSoC.__init__(self, platform,
clk_freq=(83 + Fraction(1, 3))*1000000,
cpu_reset_address=0x00180000,
sdram_controller_settings=sdram_controller_settings,
**kwargs)
self.submodules.crg = _MXCRG(_MXClockPads(platform), self.clk_freq)
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(platform.request("ddram"),
MT46V32M16(self.clk_freq),
rd_bitslip=0,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.register_sdram_phy(self.ddrphy)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
]
if not self.integrated_rom_size:
clk_period_ns = 1000000000/self.clk_freq
self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
ceil(110/clk_period_ns), ceil(50/clk_period_ns))
self.flash_boot_address = 0x001a0000
self.register_rom(self.norflash.bus)
platform.add_platform_command("""
INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
""")
platform.add_source(os.path.join("misoclib", "mxcrg.v"))
def __init__(self, platform,
firmware_ram_size=0x10000,
firmware_filename=None,
**kwargs):
clk_freq = 75*1000000
SDRAMSoC.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
sdram_controller_settings=LASMIconSettings(l2_size=32, with_bandwidth=True),
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.submodules.dna = dna.DNA()
self.submodules.git_info = git_info.GitInfo()
self.submodules.platform_info = platform_info.PlatformInfo("atlys", self.__class__.__name__[:8])
self.submodules.firmware_ram = firmware.FirmwareROM(firmware_ram_size, firmware_filename)
self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size)
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"])
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(platform.request("ddram"),
P3R1GE4JGF(self.clk_freq),
rd_bitslip=0,
wr_bitslip=4,
dqs_ddr_alignment="C0")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.register_sdram_phy(self.ddrphy)
self.specials += Keep(self.crg.cd_sys.clk)
platform.add_platform_command("""
NET "{sys_clk}" TNM_NET = "GRPsys_clk";
""", sys_clk=self.crg.cd_sys.clk)
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(),
clk_freq=(83 + Fraction(1, 3))*1000*1000, **kwargs):
SDRAMSoC.__init__(self, platform, clk_freq,
cpu_reset_address=0x170000, # 1.5 MB
sdram_controller_settings=sdram_controller_settings,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"),
MT46H32M16(self.clk_freq),
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.register_sdram_phy(self.ddrphy)
if not self.integrated_rom_size:
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"),
dummy=10, div=4)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.flash_boot_address = 0x180000
self.register_rom(self.spiflash.bus, 0x1000000)
def __init__(self, platform,
firmware_ram_size=0x10000,
firmware_filename=None,
**kwargs):
clk_freq = 75 * MHz
SDRAMSoC.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
sdram_controller_settings=LASMIconSettings(l2_size=32, with_bandwidth=True),
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.submodules.dna = dna.DNA()
self.submodules.git_info = git_info.GitInfo()
self.submodules.platform_info = platform_info.PlatformInfo("atlys", self.__class__.__name__[:8])
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
self.submodules.firmware_ram = firmware.FirmwareROM(firmware_ram_size, firmware_filename)
self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size)
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"])
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
P3R1GE4JGF(self.clk_freq),
rd_bitslip=0,
wr_bitslip=4,
dqs_ddr_alignment="C0",
)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.register_sdram_phy(self.ddrphy)
self.submodules.spiflash = spiflash.SpiFlash(
platform.request("spiflash4x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size
self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.gateware_size)
self.specials += Keep(self.crg.cd_sys.clk)
self.specials += Keep(self.crg.cd_periph.clk)
platform.add_platform_command("""
# Separate TMNs for FROM:TO TIG constraints
NET "{sys_clk}" TNM_NET = "TIGsys_clk";
NET "{periph_clk}" TNM_NET = "TIGperiph_clk";
NET "{encoder_clk}" TNM_NET = "TIGencoder_clk";
TIMESPEC "TSsys_to_periph" = FROM "TIGsys_clk" TO "TIGperiph_clk" TIG;
TIMESPEC "TSperiph_to_sys" = FROM "TIGperiph_clk" TO "TIGsys_clk" TIG;
TIMESPEC "TSsys_to_encoder" = FROM "TIGsys_clk" TO "TIGencoder_clk" TIG;
TIMESPEC "TSencoder_to_sys" = FROM "TIGencoder_clk" TO "TIGsys_clk" TIG;
""",
sys_clk=self.crg.cd_sys.clk,
periph_clk=self.crg.cd_periph.clk,
encoder_clk=self.crg.cd_encoder.clk,
)
def __init__(self,
platform,
firmware_ram_size=0x10000,
firmware_filename=None,
**kwargs):
clk_freq = 75 * 1000000
SDRAMSoC.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
sdram_controller_settings=LASMIconSettings(
l2_size=32, with_bandwidth=True),
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.submodules.dna = dna.DNA()
self.submodules.git_info = git_info.GitInfo()
self.submodules.platform_info = platform_info.PlatformInfo(
"atlys", self.__class__.__name__[:8])
self.submodules.firmware_ram = firmware.FirmwareROM(
firmware_ram_size, firmware_filename)
self.register_mem("firmware_ram", self.mem_map["firmware_ram"],
self.firmware_ram.bus, firmware_ram_size)
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"])
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
P3R1GE4JGF(self.clk_freq),
rd_bitslip=0,
wr_bitslip=4,
dqs_ddr_alignment="C0")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.register_sdram_phy(self.ddrphy)
self.submodules.spiflash = spiflash.SpiFlash(
platform.request("spiflash4x"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.gateware_size)
self.specials += Keep(self.crg.cd_sys.clk)
platform.add_platform_command("""
NET "{sys_clk}" TNM_NET = "GRPsys_clk";
""",
sys_clk=self.crg.cd_sys.clk)
def __init__(self, platform,
firmware_ram_size=0x10000,
firmware_filename=None,
**kwargs):
clk_freq = 50*1000000
SDRAMSoC.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
sdram_controller_settings=LASMIconSettings(l2_size=32, with_bandwidth=True),
with_uart=False,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.submodules.dna = dna.DNA()
self.submodules.git_info = git_info.GitInfo()
self.submodules.platform_info = platform_info.PlatformInfo("opsis", self.__class__.__name__[:8])
fx2_uart_pads = platform.request("serial_fx2")
sd_card_uart_pads = platform.request("serial_sd_card")
uart_pads = UARTSharedPads()
self.comb += [
# TX
fx2_uart_pads.tx.eq(uart_pads.tx),
sd_card_uart_pads.tx.eq(uart_pads.tx),
# RX
uart_pads.rx.eq(fx2_uart_pads.rx & sd_card_uart_pads.rx)
]
self.submodules.uart_phy = UARTPHY(uart_pads, self.clk_freq, 115200)
self.submodules.uart = uart.UART(self.uart_phy)
# self.submodules.opsis_eeprom_i2c = i2c.I2C(platform.request("opsis_eeprom"))
self.submodules.fx2_reset = gpio.GPIOOut(platform.request("fx2_reset"))
self.submodules.fx2_hack = i2c_hack.I2CShiftReg(platform.request("opsis_eeprom"))
self.submodules.tofe_eeprom_i2c = i2c.I2C(platform.request("tofe_eeprom"))
self.submodules.firmware_ram = firmware.FirmwareROM(firmware_ram_size, firmware_filename)
self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size)
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"])
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY(platform.request("ddram"),
MT41J128M16(self.clk_freq),
rd_bitslip=0,
wr_bitslip=4,
dqs_ddr_alignment="C0")
self.comb += [
self.ddrphy.clk8x_wr_strb.eq(self.crg.clk8x_wr_strb),
self.ddrphy.clk8x_rd_strb.eq(self.crg.clk8x_rd_strb),
]
self.register_sdram_phy(self.ddrphy)
self.specials += Keep(self.crg.cd_sys.clk)
platform.add_platform_command("""
NET "{sys_clk}" TNM_NET = "GRPsys_clk";
""", sys_clk=self.crg.cd_sys.clk)
def __init__(self,
platform,
firmware_ram_size=0xa000,
firmware_filename=None,
**kwargs):
clk_freq = (83 + Fraction(1, 3)) * 1000 * 1000
SDRAMSoC.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
sdram_controller_settings=LASMIconSettings(
l2_size=32, with_bandwidth=True),
**kwargs)
platform.add_extension(PipistrelloCustom)
self.submodules.crg = _CRG(platform, clk_freq)
self.submodules.dna = dna.DNA()
self.submodules.git_info = git_info.GitInfo()
self.submodules.platform_info = platform_info.PlatformInfo(
"pipistrello"[:8], self.__class__.__name__[:8])
self.submodules.fx2_reset = gpio.GPIOOut(platform.request("fx2_reset"))
self.submodules.fx2_hack = i2c_hack.I2CShiftReg(
platform.request("fx2_hack"))
self.submodules.firmware_ram = firmware.FirmwareROM(
firmware_ram_size, firmware_filename)
self.register_mem("firmware_ram", self.mem_map["firmware_ram"],
self.firmware_ram.bus, firmware_ram_size)
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"])
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
MT46H32M16(self.clk_freq),
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.register_sdram_phy(self.ddrphy)
self.submodules.spiflash = spiflash.SpiFlash(
platform.request("spiflash4x"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.gateware_size)
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
clk_freq = 80*1000000
SDRAMSoC.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
sdram_controller_settings=sdram_controller_settings,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"),
AS4C16M16(clk_freq))
self.register_sdram_phy(self.sdrphy)
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
SDRAMSoC.__init__(self, platform,
clk_freq=100*1000000,
integrated_rom_size=0x8000,
sdram_controller_settings=sdram_controller_settings,
**kwargs)
self.submodules.crg = _CRG(platform)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"),
IS42S16160(self.clk_freq))
self.register_sdram_phy(self.sdrphy)
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
clk_freq = 80*1000000
SDRAMSoC.__init__(self, platform, clk_freq,
cpu_reset_address=0x60000,
sdram_controller_settings=sdram_controller_settings,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"),
MT48LC4M16(clk_freq))
self.register_sdram_phy(self.sdrphy)
if not self.integrated_rom_size:
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"),
dummy=4, div=6)
self.flash_boot_address = 0x70000
self.register_rom(self.spiflash.bus)
def __init__(self, platform,
firmware_ram_size=0xa000,
firmware_filename=None,
**kwargs):
clk_freq = (83 + Fraction(1, 3)) * MHz
SDRAMSoC.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
sdram_controller_settings=LASMIconSettings(l2_size=32, with_bandwidth=True),
**kwargs)
platform.add_extension(PipistrelloCustom)
self.submodules.crg = _CRG(platform, clk_freq)
self.submodules.dna = dna.DNA()
self.submodules.git_info = git_info.GitInfo()
self.submodules.platform_info = platform_info.PlatformInfo("pipistrello"[:8], self.__class__.__name__[:8])
self.submodules.fx2_reset = gpio.GPIOOut(platform.request("fx2_reset"))
self.submodules.fx2_hack = i2c_hack.I2CShiftReg(platform.request("fx2_hack"))
self.submodules.firmware_ram = firmware.FirmwareROM(firmware_ram_size, firmware_filename)
self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size)
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"])
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
MT46H32M16(self.clk_freq),
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1",
)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.register_sdram_phy(self.ddrphy)
self.submodules.spiflash = spiflash.SpiFlash(
platform.request("spiflash4x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size
self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.gateware_size)
def __init__(self, platform, clk_freq=(83 + Fraction(1, 3))*1000*1000,
sdram_controller_settings=LASMIconSettings(l2_size=32,
with_bandwidth=True),
firmware_ram_size=0xa000, firmware_filename=None, **kwargs):
SDRAMSoC.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
sdram_controller_settings=sdram_controller_settings,
**kwargs)
platform.add_extension(PipistrelloCustom)
self.submodules.crg = _CRG(platform, clk_freq)
self.submodules.dna = dna.DNA()
self.submodules.git_info = git_info.GitInfo()
self.submodules.platform_info = platform_info.PlatformInfo("pipistrello"[:8], self.__class__.__name__[:8])
self.submodules.fx2_reset = gpio.GPIOOut(platform.request("fx2_reset"))
self.submodules.fx2_hack = i2c_hack.I2CShiftReg(platform.request("fx2_hack"))
self.submodules.firmware_ram = firmware.FirmwareROM(firmware_ram_size, firmware_filename)
self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size)
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"])
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(platform.request("ddram"),
MT46H32M16(self.clk_freq),
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.register_sdram_phy(self.ddrphy)
if not self.integrated_rom_size:
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"),
dummy=10, div=4)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.flash_boot_address = 0x180000
self.register_rom(self.spiflash.bus, 0x1000000)
platform.add_platform_command("""PIN "hdmi_out_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
SDRAMSoC.__init__(self, platform,
clk_freq=125*1000000, cpu_reset_address=0xaf0000,
sdram_controller_settings=sdram_controller_settings,
**kwargs)
self.submodules.crg = _CRG(platform)
if not self.integrated_main_ram_size:
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"),
MT8JTF12864(self.clk_freq))
self.register_sdram_phy(self.ddrphy)
if not self.integrated_rom_size:
spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads, dummy=11, div=2)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.flash_boot_address = 0xb00000
self.register_rom(self.spiflash.bus)
def __init__(self, platform, clk_freq=(83 + Fraction(1, 3))*1000*1000,
sdram_controller_settings=LASMIconSettings(l2_size=32,
with_bandwidth=True),
firmware_ram_size=0xa000, firmware_filename=None, **kwargs):
SDRAMSoC.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
sdram_controller_settings=sdram_controller_settings,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.submodules.dna = dna.DNA()
self.submodules.firmware_ram = wishbone.SRAM(firmware_ram_size, init=_get_firmware_data(firmware_filename))
self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size)
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"])
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(platform.request("ddram"),
MT46H32M16(self.clk_freq),
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.register_sdram_phy(self.ddrphy)
if not self.integrated_rom_size:
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"),
dummy=10, div=4)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.flash_boot_address = 0x180000
self.register_rom(self.spiflash.bus, 0x1000000)
platform.add_platform_command("""PIN "hdmi_out_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
platform.add_platform_command("""INST "hdmi_out_pix_bufg" LOC = BUFGMUX_X2Y1;""")
def __init__(self, platform,
firmware_ram_size=0x10000,
firmware_filename=None,
**kwargs):
clk_freq = 50*1000000
SDRAMSoC.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
sdram_controller_settings=LASMIconSettings(l2_size=32, with_bandwidth=True),
with_uart=False,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.submodules.dna = dna.DNA()
self.submodules.git_info = git_info.GitInfo()
self.submodules.platform_info = platform_info.PlatformInfo("opsis", self.__class__.__name__[:8])
fx2_uart_pads = platform.request("serial_fx2")
sd_card_uart_pads = platform.request("serial_sd_card")
uart_pads = UARTSharedPads()
self.comb += [
# TX
fx2_uart_pads.tx.eq(uart_pads.tx),
sd_card_uart_pads.tx.eq(uart_pads.tx),
# RX
uart_pads.rx.eq(fx2_uart_pads.rx & sd_card_uart_pads.rx)
]
self.submodules.uart_phy = UARTPHY(uart_pads, self.clk_freq, 115200)
self.submodules.uart = uart.UART(self.uart_phy)
# self.submodules.opsis_eeprom_i2c = i2c.I2C(platform.request("opsis_eeprom"))
self.submodules.fx2_reset = gpio.GPIOOut(platform.request("fx2_reset"))
self.submodules.fx2_hack = i2c_hack.I2CShiftReg(platform.request("opsis_eeprom"))
self.submodules.tofe_eeprom_i2c = i2c.I2C(platform.request("tofe_eeprom"))
self.submodules.firmware_ram = firmware.FirmwareROM(firmware_ram_size, firmware_filename)
self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size)
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"])
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY(platform.request("ddram"),
MT41J128M16(self.clk_freq),
rd_bitslip=0,
wr_bitslip=4,
dqs_ddr_alignment="C0")
self.comb += [
self.ddrphy.clk8x_wr_strb.eq(self.crg.clk8x_wr_strb),
self.ddrphy.clk8x_rd_strb.eq(self.crg.clk8x_rd_strb),
]
self.register_sdram_phy(self.ddrphy)
self.submodules.spiflash = spiflash.SpiFlash(
platform.request("spiflash4x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size
self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.gateware_size)
self.specials += Keep(self.crg.cd_sys.clk)
platform.add_platform_command("""
NET "{sys_clk}" TNM_NET = "GRPsys_clk";
""", sys_clk=self.crg.cd_sys.clk)
def __init__(self, platform,
firmware_ram_size=0x10000,
firmware_filename=None,
**kwargs):
clk_freq = 50 * MHz
SDRAMSoC.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
sdram_controller_settings=LASMIconSettings(l2_size=32, with_bandwidth=True),
with_uart=False,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.submodules.dna = dna.DNA()
self.submodules.git_info = git_info.GitInfo()
self.submodules.platform_info = platform_info.PlatformInfo("opsis", self.__class__.__name__[:8])
fx2_uart_pads = platform.request("serial_fx2")
sd_card_uart_pads = platform.request("serial_sd_card")
uart_pads = UARTSharedPads()
self.comb += [
# TX
fx2_uart_pads.tx.eq(uart_pads.tx),
sd_card_uart_pads.tx.eq(uart_pads.tx),
# RX
uart_pads.rx.eq(fx2_uart_pads.rx & sd_card_uart_pads.rx)
]
self.submodules.uart_phy = UARTPHY(uart_pads, self.clk_freq, 115200)
self.submodules.uart = uart.UART(self.uart_phy)
# self.submodules.opsis_eeprom_i2c = i2c.I2C(platform.request("opsis_eeprom"))
self.submodules.fx2_reset = gpio.GPIOOut(platform.request("fx2_reset"))
self.submodules.fx2_hack = i2c_hack.I2CShiftReg(platform.request("opsis_eeprom"))
self.submodules.tofe_eeprom_i2c = i2c.I2C(platform.request("tofe_eeprom"))
self.submodules.firmware_ram = firmware.FirmwareROM(firmware_ram_size, firmware_filename)
self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size)
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"])
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY(
platform.request("ddram"),
MT41J128M16(self.clk_freq),
rd_bitslip=0,
wr_bitslip=4,
dqs_ddr_alignment="C0",
)
self.comb += [
self.ddrphy.clk8x_wr_strb.eq(self.crg.clk8x_wr_strb),
self.ddrphy.clk8x_rd_strb.eq(self.crg.clk8x_rd_strb),
]
self.register_sdram_phy(self.ddrphy)
self.submodules.spiflash = spiflash.SpiFlash(
platform.request("spiflash4x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size
self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.gateware_size)
self.specials += Keep(self.crg.cd_sys.clk)
self.specials += Keep(self.crg.cd_periph.clk)
platform.add_platform_command("""
# Separate TMNs for FROM:TO TIG constraints
NET "{sys_clk}" TNM_NET = "TIGsys_clk";
NET "{periph_clk}" TNM_NET = "TIGperiph_clk";
NET "{encoder_clk}" TNM_NET = "TIGencoder_clk";
TIMESPEC "TSsys_to_periph" = FROM "TIGsys_clk" TO "TIGperiph_clk" TIG;
TIMESPEC "TSperiph_to_sys" = FROM "TIGperiph_clk" TO "TIGsys_clk" TIG;
TIMESPEC "TSsys_to_encoder" = FROM "TIGsys_clk" TO "TIGencoder_clk" TIG;
TIMESPEC "TSencoder_to_sys" = FROM "TIGencoder_clk" TO "TIGsys_clk" TIG;
""",
sys_clk=self.crg.cd_sys.clk,
periph_clk=self.crg.cd_periph.clk,
encoder_clk=self.crg.cd_encoder.clk,
)
