def do_finalize(self):
if not self.integrated_main_ram_size:
if not self._sdram_phy_registered:
raise FinalizeError(
"Need to call SDRAMSoC.register_sdram_phy()")
# arbitrate wishbone interfaces to the DRAM
self.submodules.wb_sdram_con = wishbone.Arbiter(
self._wb_sdram_ifs, self._wb_sdram)
SoC.do_finalize(self)
