def _test_spi():
tb_dut = m_spi(clock,reset,regbus,fiforx,fifotx,spibus)
tb_ee = spiee.gen(clock,reset,spibus)
tb_clk = clock.gen(hticks=5)
@instance
def tb_stim():
yield reset.pulse(33)
yield regbus.read(0x400, rwd)
print(rwd)
raise StopSimulation
return tb_stim, tb_dut, tb_ee, tb_clk
def _test_spi():
tbdut = m_spi(glbl, regbus,
fiforx, fifotx, spibus,
base_address=base_address)
tbeep = spiee.gen(clock, reset, spibus)
tbclk = clock.gen(hticks=5)
# grab all the register file outputs
tbmap = regbus.m_per_outputs()
# get a reference to the SPI register file
rf = regbus.regfiles['SPI_000']
# dumpy the registers for the SPI peripheral
for name,reg in rf.registers.iteritems():
print("{0} {1:04X} {2:04X}".format(name, reg.addr, int(reg)))
@instance
def tbstim():
yield reset.pulse(33)
try:
#~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# loop through the registers and check the default
# values, these are the offset values.
for addr,sig in rf.roregs:
yield regbus.read(addr+ba)
assert regbus.readval == int(sig)
for addr,sig in rf.rwregs:
# need to skip the FIFO read / write
if addr in (0x68, 0x6C,):
pass
else:
yield regbus.read(addr+ba)
assert regbus.readval == int(sig)
#~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# enable the system
print(" enable the SPI core")
yield regbus.write(rf.spst.addr, 0x02) # register data drives fifo
yield regbus.write(rf.spcr.addr, 0x9A) # default plus enable (98 + 02)
print(" write to the transmit register")
yield regbus.write(rf.sptx.addr, 0x02)
yield regbus.write(rf.sptx.addr, 0x00)
yield regbus.write(rf.sptx.addr, 0x00)
yield regbus.write(rf.sptx.addr, 0x00)
yield regbus.write(rf.sptx.addr, 0x55)
yield regbus.read(rf.sptc.addr)
print(regbus.readval)
yield regbus.read(rf.sprc.addr)
print(regbus.readval)
yield delay(1000)
for ii in range(1000):
yield regbus.read(rf.sprc.addr)
if regbus.readval == 5:
break
yield delay(1000)
for ii in range(5):
yield regbus.read(rf.sprx.addr)
print("spi readback {0}".format(regbus.readval))
except Exception, err:
print("@W: exception {0}".format(err))
yield delay(100)
raise err
yield delay(100)
raise StopSimulation
def m_test_top(clock,reset,sck,mosi,miso,ss):
# @todo:
g_spi = m_spi()
def m_test_top(clock, reset, sck, mosi, miso, ss):
# @todo: create a top-level for conversion ...
g_spi = m_spi()
return g_spi
