def _create_test_regfile():
global regdef
regdef = collections.OrderedDict()
# --register 0--
reg = Register('control', 0x0018, 8, 'rw', 0)
reg.comment = "register 0"
reg.add_named_bits('enable', slice(1, 0)) # read-only namedbit
reg.add_named_bits('loop', slice(2, 1)) # read-only namedbit
regdef[reg.name] = reg
# -- more registers register --
for addr,default in zip((0x20, 0x40, 0x80),
(0xDE, 0xCA, 0xFB)):
reg = Register('reg%s' % (addr,), addr, 8, 'rw', default)
regdef[reg.name] = reg
# -- read only register --
reg = Register('regro', 0x100, 8, 'ro', 0xAA)
regdef[reg.name] = reg
# another read only register, with named bits
reg = Register('status', 0x200, 8, 'ro', 0)
reg.add_named_bits('error', slice(1, 0)) # bit 0, read-write namedbit
reg.add_named_bits('ok', slice(2, 1)) # bit 1, read-write namedbit
reg.add_named_bits('cnt', slice(8, 2)) # bits 7-2, read-write namedbit
regdef[reg.name] = reg
regfile = RegisterFile(regdef)
return regfile
def _create_test_regfile():
global regdef
regdef = OrderedDict()
# --register 0--
reg = Register('reg0',0x0018,8,'rw',0)
reg.comment = "register 0"
reg.add_bits('enable', slice(1,0))
reg.add_bits('loop', slice(2,1))
regdef[reg.name] = reg
# -- more registers register --
for addr,default in zip((0x20,0x40,0x80),
(0xDE,0xCA,0xFB)):
reg = Register('reg%s'%(addr),addr,8,'rw',default)
regdef[reg.name] = reg
# -- read only register --
reg = Register('regro',0x100,8,'ro',0xAA)
regdef[reg.name] = reg
regfile = RegisterFile(regdef)
return regfile
from collections import OrderedDict
from myhdl import *
from mn.system import RegisterFile, Register, RegisterBits
regfile = RegisterFile()
# -- a basic configuration register --
regcfg = Register('cfg', 0x00, 8, 'rw', 0)
regcfg.comment = "fifo ramp configuration register"
regcfg.add_named_bits('enable', slice(1, 0), "enable fifo ramp")
regfile.add_register(regcfg)
# -- division register 0 --
# 32-bit clock division register
for ii, regname in enumerate(('div3', 'div2', 'div1', 'div0')):
regdiv = Register(regname, 0x04 + ii, 8, 'rw', 0)
regdiv.comment = "division register most significant byte"
regdiv.add_named_bits('%sb' % (regname), slice(8, 0),
"rate control divisor")
regfile.add_register(regdiv)
# -- number of ramps completed --
# 32-bit
for ii, regname in enumerate(('cnt3', 'cnt2', 'cnt1', 'cnt0')):
regcnt = Register(regname, 0x08 + ii, 8, 'ro', 0)
regcnt.comment = "the number of ramp cycles completed"
regcnt.add_named_bits('%sb' % (regname), slice(8, 0), "count")
regfile.add_register(regcnt)
0x7C: SPXX SCK clock divisor (divides wb clk_i)
0 -- 2 divisor 24 MHz (usbp == 48MHz system clock)
"""
regfile = RegisterFile()
# -- SPI Setup Register
spst = Register('spst', 0x58, 8, 'rw', 0x00)
spst.add_named_bits('freeze', slice(1,0),
"freeze the core")
spst.add_named_bits('rdata', slice(2,1),
"1 : register file (memmap) feeds TX/RX FIFO")
regfile.add_register(spst)
# -- SPI Control Register (Control Register 0) --
spcr = Register('spcr', 0x60, 8, 'rw', 0x98)
spcr.comment = "SPI control register"
spcr.add_named_bits('loop', slice(1,0), "internal loopback")
spcr.add_named_bits('spe', slice(2,1), "system enable")
spcr.add_named_bits('cpol', slice(4,3), "clock polarity")
spcr.add_named_bits('cpha', slice(5,4), "clock phase")
spcr.add_named_bits('msse', slice(8,7), "manual slave select enable")
regfile.add_register(spcr)
# -- SPI status register --
spsr = Register('spsr', 0x64, 8, 'ro', 0)
spsr.add_named_bits('rxe', slice(1,0), "RX FIFO empty")
spsr.add_named_bits('rxf', slice(2,1), "RX FIFO full")
spsr.add_named_bits('txe', slice(3,2), "TX FIFO empty")
spsr.add_named_bits('txf', slice(4,3), "TX FIFO full")
spsr.add_named_bits('modf', slice(5,4), "SS line driven external fault")
regfile.add_register(spsr)
from collections import OrderedDict
from myhdl import *
from mn.system import RegisterFile, Register, RegisterBits
regfile = RegisterFile()
# -- a basic configuration register --
regcfg = Register('cfg',0x00,8,'rw',0)
regcfg.comment = "fifo ramp configuration register"
regcfg.add_named_bits('enable', slice(1,0), "enable fifo ramp")
regfile.add_register(regcfg)
# -- division register 0 --
# 32-bit clock division register
for ii,regname in enumerate(('div3','div2','div1','div0')):
regdiv = Register(regname,0x04+ii,8,'rw',0)
regdiv.comment = "division register most significant byte"
regdiv.add_named_bits('%sb'%(regname),slice(8,0),"rate control divisor")
regfile.add_register(regdiv)
# -- number of ramps completed --
# 32-bit
for ii,regname in enumerate(('cnt3','cnt2','cnt1','cnt0')):
regcnt = Register(regname,0x08+ii,8,'ro',0)
regcnt.comment = "the number of ramp cycles completed"
regcnt.add_named_bits('%sb'%(regname),slice(8,0),"count")
regfile.add_register(regcnt)
0x78: SPRC receive fifo count
0x7C: SPXX SCK clock divisor (divides wb clk_i)
0 -- 2 divisor 24 MHz (usbp == 48MHz system clock)
"""
regfile = RegisterFile()
# -- SPI Setup Register
spst = Register('spst', 0x58, 8, 'rw', 0x00)
spst.add_named_bits('freeze', slice(1, 0), "freeze the core")
spst.add_named_bits('rdata', slice(2, 1),
"1 : register file (memmap) feeds TX/RX FIFO")
regfile.add_register(spst)
# -- SPI Control Register (Control Register 0) --
spcr = Register('spcr', 0x60, 8, 'rw', 0x98)
spcr.comment = "SPI control register"
spcr.add_named_bits('loop', slice(1, 0), "internal loopback")
spcr.add_named_bits('spe', slice(2, 1), "system enable")
spcr.add_named_bits('cpol', slice(4, 3), "clock polarity")
spcr.add_named_bits('cpha', slice(5, 4), "clock phase")
spcr.add_named_bits('msse', slice(8, 7), "manual slave select enable")
regfile.add_register(spcr)
# -- SPI status register --
spsr = Register('spsr', 0x64, 8, 'ro', 0)
spsr.add_named_bits('rxe', slice(1, 0), "RX FIFO empty")
spsr.add_named_bits('rxf', slice(2, 1), "RX FIFO full")
spsr.add_named_bits('txe', slice(3, 2), "TX FIFO empty")
spsr.add_named_bits('txf', slice(4, 3), "TX FIFO full")
spsr.add_named_bits('modf', slice(5, 4), "SS line driven external fault")
regfile.add_register(spsr)