def test_SigAugmAssignUnsupported(): z = Signal(intbv(0)[8:]) a = Signal(intbv(0)[8:]) try: verify(sigAugmAssignUnsupported, z, a) except ConversionError, e: assert e.kind == _error.NotSupported
def test_modbvSigRange(): z = Signal(modbv(0, min=0, max=42)) a = Signal(intbv(0)[4:]) b = Signal(intbv(0)[4:]) try: verify(modbvSigRange, z, a, b) except ConversionError, e: assert e.kind == _error.ModbvRange
def test_modbvRange(): z = Signal(intbv(0)[8:]) a = Signal(intbv(0)[4:]) b = Signal(intbv(0)[4:]) try: verify(modbvRange(z, a, b)) except ConversionError as e: assert e.kind == _error.ModbvRange else: assert False
def test_adder_functional(): f = get_fileinfo() assert verify(adder_bench, functional_adder) == 0 if not kh_enabled: return u = updated_files(f) assert len(u) == 2 for m in ("adder_bench", "functional_adder"): assert file_check(u, m)
def test_unused4(): f = get_fileinfo() assert verify(unused4_bench, M_DEFAULT) == 0 if not kh_enabled: return u = updated_files(f) assert len(u) == 2 for m in ("unused4_bench", "and_operator4"): assert file_check(u, m)
def test_adder_structural(): f = get_fileinfo() assert verify(adder_bench, structural_adder) == 0 if not kh_enabled: return u = updated_files(f) assert len(u) == 3 for m in ("adder_bench", "structural_adder", "onebit_full_adder"): assert file_check(u, m)
def test_multiple_components_sc_mi_nc(): f = get_fileinfo() assert verify(multiple_comp_bench, multi_reg1, t_widths[:1]) == 0 if not kh_enabled: return u = updated_files(f) assert len(u) == 4 for m in ("multiple_comp_bench", "multi_reg1", "reg_noparam", "compare"): assert file_check(u, m)
def test_multiple_components_mc_mi_ci(): f = get_fileinfo() assert verify(multiple_comp_bench, multi_reg2, t_widths[:2]) == 0 if not kh_enabled: return u = updated_files(f) assert len(u) == 5 for m in ("multiple_comp_bench", "multi_reg2", "reg_width_0", "reg_width_1", "compare"): assert file_check(u, m)
def test_unused3b(): f = get_fileinfo() defval = random.randrange(2**M_DEFAULT) assert verify(unused3_bench, M_DEFAULT, defval) == 0 if not kh_enabled: return u = updated_files(f) assert len(u) == 2 for m in ("unused3_bench", "and_operator3"): assert file_check(u, m)
def test_disable_kh(): if not kh_enabled: return f = get_fileinfo() kh_convertor.maxdepth = 0 assert verify(adder_bench, structural_adder) == 0 # one file: adder_bench u = updated_files(f) assert len(u) == 1 assert file_check(u, "adder_bench")
def test_multiple_components_v(): f = get_fileinfo() assert verify(multiple_comp_bench, multi_reg4, t_widths) == 0 if not kh_enabled: return u = updated_files(f) f_check = [ "multiple_comp_bench", "multi_reg4", "reg_width_0", "reg_width_1", "reg_width_2", "reg_width_3", "compare_0", "compare_1", "compare_2" ] assert len(u) == len(f_check) for m in f_check: assert file_check(u, m)
def test_depth(): if not kh_enabled: return file_data = [("adder_bench", ), ("adder_bench", "structural_adder"), ("adder_bench", "structural_adder", "onebit_full_adder"), ("adder_bench", "structural_adder", "onebit_full_adder")] for i in range(4): f = get_fileinfo() kh_convertor.maxdepth = i assert verify(adder_bench, structural_adder) == 0 u = updated_files(f) assert len(u) == len(file_data[i]) for m in file_data[i]: assert file_check(u, m)
def checkUnaryOps(m): assert verify(unaryBench, m) == 0
def test_incReg(): assert verify(IncBench, incRef) == 0
def test_bug_1835797(): assert verify(bug_1835797) == 0
def test_name_conflicts_verify(): assert verify(c_testbench) == 0
def test(): assert verify(FSMBench, FramerCtrl, t_State_b) == 0
def test_bug_1740778 (): assert verify(bug_1740778) == 0
def test_fifo_sync_conversion(): # @todo: if the myhdl version is 1.0 or greater # use "iverilog" verify.simulator = "iverilog" args = Namespace(width=8, size=16, name='test') def bench(): reset = ResetSignal(0, active=1, async=True) clock = Signal(bool(0)) fbus = FIFOBus(width=args.width, size=args.size) tbdut = fifo_sync(clock, reset, fbus) @instance def tbclk(): clock.next = False while True: yield delay(5) clock.next = not clock @instance def tbstim(): print("start simulation") fbus.read.next = False fbus.write.next = False fbus.clear.next = False reset.next = True yield delay(20) reset.next = False yield clock.posedge print("r, w, e, f") print("%d, %d, %d, %d, should be empty" % ( fbus.read, fbus.write, fbus.empty, fbus.full, )) assert fbus.empty fbus.write.next = True fbus.write_data.next = 0xAA yield clock.posedge fbus.write.next = False yield clock.posedge print("%d, %d, %d, %d, should not be empty" % ( fbus.read, fbus.write, fbus.empty, fbus.full, )) assert not fbus.empty print("FIFO count %d (%d%d%d%d)" % (fbus.count, fbus.read, fbus.write, fbus.empty, fbus.full)) print("more writes") fbus.write.next = True fbus.write_data.next = 1 for ii in range(15): yield clock.posedge print( "FIFO count %d (%d%d%d%d)" % (fbus.count, fbus.read, fbus.write, fbus.empty, fbus.full)) fbus.write_data.next = ii + 2 fbus.write.next = False yield clock.posedge print("FIFO count %d (%d%d%d%d)" % (fbus.count, fbus.read, fbus.write, fbus.empty, fbus.full)) yield clock.posedge print("%d, %d, %d, %d, should be full" % ( fbus.read, fbus.write, fbus.empty, fbus.full, )) # assert fbus.full fbus.read.next = True assert fbus.read_data == 0xAA yield fbus.read_valid.posedge fbus.read.next = False yield delay(1) print("%d, %d, %d, %d" % ( fbus.read, fbus.write, fbus.empty, fbus.full, )) yield clock.posedge yield clock.posedge fbus.read.next = True for ii in range(15): print("FIFO count %d data %d (%d%d%d%d)" % (fbus.count, fbus.read_data, fbus.read, fbus.write, fbus.empty, fbus.full)) yield clock.posedge fbus.read.next = False yield clock.posedge print("%d, %d, %d, %d" % ( fbus.read, fbus.write, fbus.empty, fbus.full, )) print("end simulation") raise StopSimulation return tbdut, tbclk, tbstim myhdl.toVerilog.directory = None assert verify(bench) == 0
def test_one_level_verify(): assert verify(c_testbench_one) == 0
def testForLoop4(): assert verify(LoopBench, ForLoop4) == 0
def checkBinary(m, n): assert verify(binaryBench, m, n) == 0
def testWhileBreakLoop(): assert verify(LoopBench, WhileBreakLoop) == 0
def testNestedForLoop2(): assert verify(LoopBench, NestedForLoop2) == 0
def testForBreakLoop(): assert verify(LoopBench, ForBreakLoop) == 0
def testForLoop5(): assert verify(LoopBench, ForLoop5) == 0
def testPlain(): assert verify(HecBench, HecCalculatorPlain) == 0
def testForBreakContinueLoop(): assert verify(LoopBench, ForBreakContinueLoop) == 0
def test_hdlobjobj(): assert verify(ObjBench, HdlObjObj) == 0
def testWhileLoop(): assert verify(LoopBench, FunctionCall) == 0
def test_hdlobjattrsimple(): assert verify(ObjBench, HdlObjAttrSimple) == 0
def testWhileBreakContinueLoop(): assert verify(LoopBench, WhileBreakContinueLoop) == 0
def checkMultiOps(m, n, p): assert verify(multiBench, m, n, p) == 0
def checkAugmOps(m, n): assert verify(augmBench, m, n) == 0
clock = Signal(bool(0)) reset = ResetSignal(0, active=0, async=True) ia = MyIntf() ib = MyIntf() analyze(m_one_level, clock, reset, ia, ib) def test_one_level_verify(): assert verify(c_testbench_one) == 0 def test_two_level_analyze(): clock = Signal(bool(0)) reset = ResetSignal(0, active=0, async=True) ia = MyIntf() ib = MyIntf() analyze(m_two_level, clock, reset, ia, ib) def test_two_level_verify(): assert verify(c_testbench_two) == 0 if __name__ == '__main__': print(sys.argv[1]) verify.simulator = analyze.simulator = sys.argv[1] Simulation(c_testbench_one()).run() Simulation(c_testbench_two()).run() print(verify(c_testbench_one)) print(verify(c_testbench_two))
def test_two_level_verify(): assert verify(c_testbench_two) == 0
def test_issue_10_2(): assert verify(Logic, flags, position) == 0
def test_issue_122(): assert verify(tb_issue_122) == 0
def testDecRef(): assert verify(DecBench, decRef) == 0
for ii in range(17): print("a: x=%d y=%d z=%d" % (a.x, a.y, a.z)) print("b: x=%d y=%d z=%d" % (b.x, b.y, b.z)) print("c: x=%d y=%d z=%d" % (c.x, c.y, c.z)) yield clock.posedge raise StopSimulation return tb_dut, tb_clk, tb_stim def test_name_conflicts_analyze(): clock = Signal(bool(0)) reset = ResetSignal(0, active=0, async=False) a, b, c = ( Intf(), Intf(), Intf(), ) analyze(m_test_intf, clock, reset, a, b, c) def test_name_conflicts_verify(): assert verify(c_testbench) == 0 if __name__ == '__main__': verify.simulator = analyze.simulator = sys.argv[1] Simulation(c_testbench()).run() print(verify(c_testbench))
def testDecFunc(): assert verify(DecBench, decFunc) == 0
def test_bug_aj1s(): assert verify(dut) == 0
def testDecTask(): assert verify(DecBench, decTask) == 0
def testForLoop1(): assert verify(LoopBench, ForLoop1) == 0
def test_inc2(): assert verify(IncBench, inc2) == 0
def testForLoop2(): assert verify(LoopBench, ForLoop2) == 0