def myBench():
i_clk = self.signals['i_clk']
o_data_out = self.signals['o_data_out']
i_enable = self.signals['i_enable']
i_rst = self.signals['i_rst']
yield posedge(i_clk)
i_enable.next = False
i_rst.next = True
yield posedge(i_clk)
i_rst.next = False
yield posedge(i_clk)
yield posedge(i_clk)
self.assertEqual(o_data_out, 0)
i_enable.next = True
yield posedge(i_clk)
for x in range(2**(self.data_width + 1) + 8):
self.assertEqual(x & 0xFF, o_data_out)
yield posedge(i_clk)
i_enable.next = False
i_rst.next = True
yield posedge(i_clk)
i_rst.next = False
yield posedge(i_clk)
yield posedge(i_clk)
self.assertEqual(o_data_out, 0)
raise StopSimulation
def check(self, count, enable, clock, reset, n):
expect = 0
yield posedge(reset)
self.assertEqual(count, expect)
while 1:
yield posedge(clock)
if enable:
expect = (expect + 1) % n
yield delay(1)
# print "%d count %s expect %s" % (now(), count, expect)
self.assertEqual(count, expect)
def check(self, count, enable, clock, reset, n):
expect = 0
yield posedge(reset)
self.assertEqual(count, expect)
while 1:
yield posedge(clock)
if enable:
expect = (expect + 1) % n
yield delay(1)
# print "%d count %s expect %s" % (now(), count, expect)
self.assertEqual(count, expect)
def check(self, q, clk, reset):
yield posedge(reset)
v_Z = 0
first = 1
for v in self.vals:
yield posedge(clk)
if not first:
self.assertEqual(q, v_Z)
first = 0
yield delay(3)
self.assertEqual(q, v)
v_Z = v
def check(self, q, clk, reset):
yield posedge(reset)
v_Z = 0
first = 1
for v in self.vals:
yield posedge(clk)
if not first:
self.assertEqual(q, v_Z)
first = 0
yield delay(3)
self.assertEqual(q, v)
v_Z = v