def main():
print "\n\n## stimulus ##\n"
Simulation(stimulus()).run()
print "\n\n## test ##\n"
Simulation(test()).run()
print "\n\n## testTimeout ##\n"
Simulation(testTimeout()).run()
print "\n\n## testNoJoin ##\n"
Simulation(testNoJoin()).run()
print "\n\n## testJoin ##\n"
Simulation(testJoin()).run()
def test_memory():
"""
Memory: Test load and R/W operations.
"""
gen_test_file()
trace = False
if trace:
sim = Simulation(traceSignals(_testbench))
else:
sim = Simulation(_testbench())
sim.run()
def test_cache():
"""
Cache: Test loading from memory
"""
gen_test_file()
trace = False
if trace:
sim = Simulation(traceSignals(_testbench))
else:
sim = Simulation(_testbench())
sim.run()
def issue_104_multiple_instance():
sim1 = Simulation(test())
sim1.run(1000)
# sim1 is "puased"
# try and create a second, third, forth simulation instance
for ii in range(4):
with raises_kind(SimulationError, _error.MultipleSim):
another_sim = Simulation(test())
# generating more sims should have failed
sim1.run(1000)
sim1.quit()
def test_core(hex_file, vcd):
"""
Core: Behavioral test for the RISCV core.
"""
if vcd:
vcd = traceSignals(
core_testbench,
hex_file,
)
sim = Simulation(vcd)
else:
sim = Simulation(core_testbench(hex_file))
sim.run()
def run(x_vocab, y_skipgram, vocab_size):
"""Run train driver."""
# simulate design
#train = traceSignals(train)
sim = Simulation(train(x_vocab, y_skipgram, vocab_size))
sim.run()
def run_IM_cosim():
# Initiate signals
MAX_TIME = 1000000
clock = Signal(0)
MR = Signal(0, delay=10)
MW = Signal(0, delay=10)
address = Signal(intbv(0, 0, 2**32), delay=10)
WD = Signal(intbv(0, 0, 2**32), delay=10)
pyData = Signal(intbv(0, 0, 2**32))
vData = Signal(intbv(0, 0, 2**32))
# Build driver instances
clock_driver = clock_generator(clock, period=20)
addr_driver = random_signal(clock, address, seed=1)
WD_driver = random_signal(clock, WD, seed=2)
MR_driver = pulse_generator(clock, MR, delay=2)
MW_driver = pulse_generator(clock, MW, delay=3)
py_cosim = traceSignals(py_dm(clock, address, MW, MR, pyData, WD))
v_cosim = v_dm(clock, MR, MW, address, WD, vData)
read_test = match_test_report(clock,
vData,
pyData,
a_name="v:",
b_name="py:")
sim = Simulation(instances())
sim.run(MAX_TIME)
def test1(self):
try:
Simulation(None)
except SimulationError as e:
self.assertEqual(e.kind, _error.ArgType)
except:
self.fail()
def testMux(self):
def muxFunction(a, b, c, d):
if c:
return a
else:
return b
Simulation(self.bench(muxFunction)).run(quiet=QUIET)
def run_ALU_cosim():
# Initiate signals
MAX_TIME = 1000000
clock = Signal(0)
reset = Signal(0)
inA = Signal(intbv(0, 0, 2**32), delay=10)
inB = Signal(intbv(0, 0, 2**32), delay=10)
ALU_control = Signal(intbv(0, 0, 2**3), delay=10)
pyData = Signal(intbv(0, 0, 2**32))
pyZero = Signal(intbv(0, 0, 2**32))
vData = Signal(intbv(0, 0, 2**32))
vZero = Signal(intbv(0, 0, 2**32))
# Build driver instances
clock_driver = clock_generator(clock, period=20)
control_driver = random_signal(clock, ALU_control, seed=1)
A_rand = random_signal(clock, inA, seed=2)
B_rand = random_signal(clock, inB, seed=3)
reset_driver = pulse_generator(clock, reset)
py_cosim = traceSignals(
py_alu(clock, reset, inA, inB, ALU_control, pyData, pyZero))
v_cosim = v_alu(clock, reset, ALU_control, inA, inB, vData, vZero)
read_test = match_test_report(clock, (vData, vZero), (pyData, pyZero),
a_name="v:",
b_name="py:")
sim = Simulation(instances())
sim.run(MAX_TIME)
def test7(self):
a, b, c, d = [Signal(0) for i in range(4)]
def response():
yield join(a, delay(30)), join(c, d)
assert now() == 20
Simulation(self.stimulus(a, b, c, d), response()).run(quiet=QUIET)
def test11(self):
a, b, c, d = [Signal(0) for i in range(4)]
def response():
yield join(a, b.posedge, b.negedge, a)
assert now() == 15
Simulation(self.stimulus(a, b, c, d), response()).run(quiet=QUIET)
def test_lcounter(self):
def bench():
clk = Signal(False)
lzero = Signal(True)
lc = lcounter(clk, lzero)
@instance
def drive_stuff():
clk.next = 0
for j in range(2):
for i in range((1 << LCOUNT_BITS) - 1):
yield delay(1)
clk.next = 1
yield delay(1)
clk.next = 0
self.assertEqual(lzero, 0)
yield delay(1)
clk.next = 1
yield delay(1)
clk.next = 0
self.assertEqual(lzero, 1)
return (lc, drive_stuff)
tb = bench()
sim = Simulation(tb)
sim.run()
def run_test(self, test):
clk = Signal(bool(0))
rst = Signal(bool(1))
dout = Signal(intbv(0, min=0, max=16))
din = Signal(intbv(0, min=0, max=16))
ld = Signal(bool(1))
carry_out = Signal(bool(0))
inst = ring_counter(clk, rst, dout, din, ld, carry_out)
check = test(clk, rst, dout, din, ld, carry_out, 9)
sim = Simulation(inst, check)
sim.run(quiet=1)
inst = ring_counter(clk, rst, dout, din, ld, carry_out, max_val=5)
check = test(clk, rst, dout, din, ld, carry_out, 5)
sim = Simulation(inst, check)
sim.run(quiet=1)
def test2(self):
def g():
yield delay(10)
i = g()
with raises_kind(SimulationError, _error.DuplicatedArg):
Simulation(i, i)
def run_testbench(tbfunc, mexname='', dutmod=None, portmap=None):
"""
Arguments:
tbfunc: testbench function
dutmod: design under test module (function)
mexname: name of the exercise (name of the VCD file)
portmap: dictionary with the top-level port map for conversion
"""
if not os.path.isdir('vcd'):
os.makedirs('vcd')
traceSignals.name = 'vcd/{}'.format(mexname)
if os.path.isfile(traceSignals.name + '.vcd'):
os.remove(traceSignals.name + '.vcd')
Simulation(traceSignals(tbfunc)).run()
noerror = hasattr(tbfunc, 'error') and not tbfunc.error
if dutmod is not None and portmap is not None and noerror:
if not os.path.isdir('output'):
os.makedirs('output')
myhdl.toVHDL.directory = 'output'
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog.no_testbench = True
myhdl.toVHDL(dutmod, **portmap)
myhdl.toVerilog(dutmod, **portmap)
def test_jump(self):
dlx_instance = dlx(program=os.path.join(ROOT, 'programs/test6.txt'), data_mem=self.data_mem, reg_mem=self.reg_mem, Clk=None)
def test():
yield delay(10)
self.assertEqual(self.reg_mem[5].val, 0)
yield delay(2)
self.assertEqual(self.reg_mem[3].val, 8)
yield delay(2)
self.assertEqual(self.reg_mem[5].val, 4)
yield delay(2)
self.assertEqual(self.reg_mem[2].val, -4)
yield delay(6)
self.assertEqual(self.reg_mem[31].val, 7)
yield delay(12)
self.assertEqual(self.reg_mem[5].val, 8)
yield delay(2)
self.assertEqual(self.reg_mem[2].val, 0)
yield delay(2)
self.assertEqual(self.reg_mem[31].val, 24)
yield delay(6)
self.assertEqual(self.reg_mem[31].val, 52)
yield delay(6)
self.assertEqual(self.reg_mem[31].val, 7)
check = test()
sim = Simulation(dlx_instance, check)
sim.run(60, quiet=True)
def test_read():
mem = AxiMemory()
xbar = AxiBusInterface()
dut = xbar.map(mem)
sim = Simulation(dut, tb_read(xbar, 0, 3))
sim.run(quiet=1)
def test2(self):
def stimulus():
a = Signal(0)
yield join(delay(10), delay(20)), delay(5)
self.assertEqual(now(), 5)
yield a
self.fail("Incorrect run") # should not get here
Simulation(stimulus()).run(quiet=QUIET)
def test2(self):
def stimulus():
a = Signal(0)
yield join(delay(10), delay(20)), delay(5)
assert now() == 5
yield a
raise AssertionError("Incorrect run") # should not get here
Simulation(stimulus()).run(quiet=QUIET)
def testRedundantNegedges(self):
""" Redundant negedge waveform test """
s = self.sig
stimulus = self.stimulus()
expected = getExpectedTimes(self.waveform, isNegedge)
response = self.response(clause=(s.negedge,) * 9, expected=expected)
self.runSim(Simulation(stimulus, response))
assert self.duration <= now()
def testPosedge(self):
""" Posedge waveform test """
s = self.sig
stimulus = self.stimulus()
expected = getExpectedTimes(self.waveform, isPosedge)
response = self.response(clause=s.posedge, expected=expected)
self.runSim(Simulation(stimulus, response))
assert self.duration <= now()
def run_test(self, test):
din = Signal(intbv(0)[4:])
hex_disp = Signal(intbv(0)[7:])
inst = bcd_decoder(din, hex_disp)
check = test(din, hex_disp)
sim = Simulation(inst, check)
sim.run(quiet=1)
def testParityError(self):
""" Expect a parity error """
try:
Simulation(self.ParityError()).run(quiet=1)
except ParityError:
pass
else:
self.fail("Expected parity error")
def run_test(self, test):
clk = Signal(bool(0))
out = Signal(bool(0))
inst = clock_divider(clk, out, in_freq=50, out_freq=2)
check = test(clk, out, 50, 2)
sim = Simulation(inst, check)
sim.run(quiet=1)
def testNegedge(self):
""" Negedge waveform test """
s = self.sig
stimulus = self.stimulus()
expected = getExpectedTimes(self.waveform, isNegedge)
response = self.response(clause=s.negedge, expected=expected)
self.runSim(Simulation(stimulus, response))
self.assertTrue(self.duration <= now())
def testRedundantEvents(self):
""" Redundant event waveform test """
s = self.sig
stimulus = self.stimulus()
expected = getExpectedTimes(self.waveform, isEvent)
response = self.response(clause=(s,) * 6, expected=expected)
self.runSim(Simulation(stimulus, response))
assert self.duration <= now()
def test2(self):
def g():
yield delay(10)
i = g()
try:
Simulation(i, i)
except SimulationError, e:
self.assertEqual(e.kind, _error.DuplicatedArg)
def testRedundantPosedges(self):
""" Redundant posedge waveform test """
s = self.sig
stimulus = self.stimulus()
expected = getExpectedTimes(self.waveform, isPosedge)
response = self.response(clause=(s.posedge,) * 3, expected=expected)
self.runSim(Simulation(stimulus, response))
self.assert_(self.duration <= now())
def sim():
insts = []
insts.append(traceSignals(gen, *args))
insts.append(stimuli())
sim = Simulation(insts)
sim.run(duration)
print
sys.stdout.flush()
