def create_modules(self):
""" add all the required modules """
c = reload(__import__(OPTS.config.ms_flop))
self.mod_ms_flop = getattr(c, OPTS.config.ms_flop)
self.ms_flop = self.mod_ms_flop("ms_flop")
self.add_mod(self.ms_flop)
self.inv = pinv(nmos_width=drc["minwidth_tx"],
beta=parameter["pinv_beta"])
self.add_mod(self.inv)
self.nand2 = nand_2(nmos_width=2 * drc["minwidth_tx"])
self.add_mod(self.nand2)
self.NAND3 = nand_3(nmos_width=3 * drc["minwidth_tx"])
self.add_mod(self.NAND3)
# Special gates: 4x Inverter
self.inv4 = pinv(nmos_width=4 * drc["minwidth_tx"],
beta=parameter["pinv_beta"])
self.add_mod(self.inv4)
self.nor2 = nor_2(nmos_width=drc["minwidth_tx"])
self.add_mod(self.nor2)
self.msf_control = ms_flop_array(name="msf_control",
columns=3,
word_size=3)
self.add_mod(self.msf_control)
self.replica_bitline = replica_bitline(
name="replica_bitline", rows=int(math.ceil(self.num_rows / 10.0)))
self.add_mod(self.replica_bitline)
def add_modules(self):
self.m1m2_via = contact(layer_stack=("metal1", "via1", "metal2"))
# Vertical metal rail gap definition
self.metal2_extend_contact = (self.m1m2_via.second_layer_height -
self.m1m2_via.contact_width) / 2
self.gap_between_rails = self.metal2_extend_contact + drc[
"metal2_to_metal2"]
self.gap_between_rail_offset = self.gap_between_rails + drc[
"minwidth_metal2"]
self.via_shift = (self.m1m2_via.second_layer_width -
self.m1m2_via.first_layer_width) / 2
# used to shift contact when connecting to NAND3 C pin down
self.contact_shift = (self.m1m2_via.first_layer_width -
self.m1m2_via.contact_width) / 2
self.inv = pinv(name="pinverter",
nmos_width=drc["minwidth_tx"],
beta=2,
height=self.bitcell_height)
self.add_mod(self.inv)
self.nand2 = nand_2(name="pnand2",
nmos_width=self.nand2_nmos_width,
height=self.bitcell_height)
self.add_mod(self.nand2)
self.nand3 = nand_3(name="pnand3",
nmos_width=self.nand3_nmos_width,
height=self.bitcell_height)
self.add_mod(self.nand3)
# CREATION OF PRE-DECODER
self.pre2_4 = pre2x4(self.nand2_nmos_width, "pre2x4")
self.add_mod(self.pre2_4)
self.pre3_8 = pre3x8(self.nand3_nmos_width, "pre3x8")
self.add_mod(self.pre3_8)
def create_nand(self, inputs):
""" Create the NAND for the predecode input stage """
if inputs == 2:
self.nand = nand_2()
elif inputs == 3:
self.nand = nand_3()
else:
debug.error("Invalid number of predecode inputs.", -1)
def add_modules(self):
self.inv = pinv()
self.add_mod(self.inv)
self.nand2 = nand_2()
self.add_mod(self.nand2)
self.nand3 = nand_3()
self.add_mod(self.nand3)
# CREATION OF PRE-DECODER
self.pre2_4 = pre2x4()
self.add_mod(self.pre2_4)
self.pre3_8 = pre3x8()
self.add_mod(self.pre3_8)
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
import nand_3
import tech
debug.info(2, "Checking 3-input nand gate")
tx = nand_3.nand_3(nmos_width=3 * tech.drc["minwidth_tx"])
self.local_check(tx)
OPTS.check_lvsdrc = True
globals.end_openram()
def create_modules(self):
layer_stack = ("metal1", "via1", "metal2")
self.m1m2_via = contact(layer_stack=layer_stack)
self.inv = pinv(name="a_inv_1",
nmos_width=drc["minwidth_tx"],
beta=2,
height=self.bitcell_height)
self.add_mod(self.inv)
if self.number_of_inputs ==2:
self.nand = nand_2(name="a_nand_2",
nmos_width=self.nmos_width,
height=self.bitcell_height)
elif self.number_of_inputs ==3:
self.nand = nand_3(name="a_nand_3",
nmos_width=self.nmos_width,
height=self.bitcell_height)
self.add_mod(self.nand)
def create_modules(self):
""" add all the required modules """
input_lst = ["csb", "web", "oeb", "clk"]
output_lst = [
"s_en", "w_en", "tri_en", "tri_en_bar", "clk_bar", "clk_buf"
]
rails = ["vdd", "gnd"]
for pin in input_lst + output_lst + rails:
self.add_pin(pin)
self.nand2 = nand_2()
self.add_mod(self.nand2)
self.nand3 = nand_3()
self.add_mod(self.nand3)
self.nor2 = nor_2()
self.add_mod(self.nor2)
# Special gates: inverters for buffering
self.inv = self.inv1 = pinv()
self.add_mod(self.inv1)
self.inv2 = pinv(nmos_width=2 * drc["minwidth_tx"])
self.add_mod(self.inv2)
self.inv4 = pinv(nmos_width=4 * drc["minwidth_tx"])
self.add_mod(self.inv4)
self.inv8 = pinv(nmos_width=8 * drc["minwidth_tx"])
self.add_mod(self.inv8)
self.inv16 = pinv(nmos_width=16 * drc["minwidth_tx"])
self.add_mod(self.inv16)
c = reload(__import__(OPTS.config.ms_flop_array))
ms_flop_array = getattr(c, OPTS.config.ms_flop_array)
self.msf_control = ms_flop_array(name="msf_control",
columns=3,
word_size=3)
self.add_mod(self.msf_control)
c = reload(__import__(OPTS.config.replica_bitline))
replica_bitline = getattr(c, OPTS.config.replica_bitline)
self.replica_bitline = replica_bitline(
rows=int(math.ceil(self.num_rows / 10.0)))
self.add_mod(self.replica_bitline)
def create_nand(self):
self.nand = nand_3(nmos_width=self.nmos_width,
height=self.bitcell_height)