def test_selector_union_empty(self): a = Selector('') b = Selector('') c = Selector.union(a, b) self.assertEqual(len(c), 0) self.assertEqual(c.expanded, ((),)) self.assertEqual(c.max_levels, 0) self.assertEqual(c.str, '')
def test_selector_union_empty_nonempty(self): a = Selector('') b = Selector('/x[0:3]') c = Selector.union(a, b) self.assertEqual(len(c), 3) self.assertEqual(c.expanded, (('x', 0), ('x', 1), ('x', 2))) self.assertEqual(c.max_levels, 2) self.assertEqual(c.str, '/x/0,/x/1,/x/2')
def test_selector_union_empty_nonempty(self): a = Selector('') b = Selector('/x[0:3]') c = Selector.union(a, b) assert len(c) == 3 assert c.expanded == (('x', 0), ('x', 1), ('x', 2)) assert c.max_levels == 2 assert c.str == '/x/0,/x/1,/x/2'
def test_selector_union_empty(self): a = Selector('') b = Selector('') c = Selector.union(a, b) assert len(c) == 0 assert c.expanded == ((), ) assert c.max_levels == 0 assert c.str == ''
def test_selector_union_empty(self): a = Selector('') b = Selector('') c = Selector.union(a, b) assert len(c) == 0 assert c.expanded == ((),) assert c.max_levels == 0 assert c.str == ''
def gen_sels(conn_mat, scaling=1): """ Generate port selectors for LPUs in benchmark test. Parameters ---------- conn_mat : numpy.ndarray Square array containing numbers of directed spiking port connections between LPUs (which correspond to the row and column indices). scaling : int Scaling factor; multiply all connection numbers by this value. Returns ------- mod_sels : dict of tuples Ports in module interfaces; the keys are the module IDs and the values are tuples containing the respective selectors for all ports, all input ports, all output ports, all graded potential, and all spiking ports. pat_sels : dict of tuples Ports in pattern interfaces; the keys are tuples containing the two module IDs connected by the pattern and the values are pairs of tuples containing the respective selectors for all source ports, all destination ports, all input ports connected to the first module, all output ports connected to the first module, all graded potential ports connected to the first module, all spiking ports connected to the first module, all input ports connected to the second module, all output ports connected to the second module, all graded potential ports connected to the second module, and all spiking ports connected to the second module. """ conn_mat = np.asarray(conn_mat) r, c = conn_mat.shape assert r == c n_lpu = r assert scaling > 0 and isinstance(scaling, numbers.Integral) conn_mat *= scaling # Construct selectors describing the ports exposed by each module: mod_sels = {} for i in xrange(n_lpu): lpu_id = 'lpu%s' % i # Structure ports as # /lpu_id/in_or_out/spike_or_gpot/other_lpu_id/[0:n_spike] # where in_or_out is relative to module i: sel_in_gpot = Selector('') sel_out_gpot = Selector('') sel_in_spike = \ Selector(','.join(['/lpu%i/in/spike/lpu%i/[0:%i]' % (i, j, n) for j, n in \ enumerate(conn_mat[:, i]) if (j != i and n != 0)])) sel_out_spike = \ Selector(','.join(['/lpu%i/out/spike/lpu%i/[0:%i]' % (i, j, n) for j, n in \ enumerate(conn_mat[i, :]) if (j != i and n != 0)])) mod_sels[lpu_id] = (Selector.union(sel_in_gpot, sel_in_spike, sel_out_gpot, sel_out_spike), Selector.union(sel_in_gpot, sel_in_spike), Selector.union(sel_out_gpot, sel_out_spike), Selector.union(sel_in_gpot, sel_out_gpot), Selector.union(sel_in_spike, sel_out_spike)) # Construct selectors describing the ports connected by each pattern: pat_sels = {} for i, j in itertools.combinations(xrange(n_lpu), 2): lpu_i = 'lpu%s' % i lpu_j = 'lpu%s' % j # The pattern's input ports are labeled "../out.." because that selector # describes the output ports of the connected module's interface: sel_in_gpot_i = Selector('') sel_out_gpot_i = Selector('') sel_in_gpot_j = Selector('') sel_out_gpot_j = Selector('') sel_in_spike_i = Selector('/%s/out/spike/%s[0:%i]' % (lpu_i, lpu_j, conn_mat[i, j])) sel_out_spike_i = Selector('/%s/in/spike/%s[0:%i]' % (lpu_i, lpu_j, conn_mat[j, i])) sel_in_spike_j = Selector('/%s/out/spike/%s[0:%i]' % (lpu_j, lpu_i, conn_mat[j, i])) sel_out_spike_j = Selector('/%s/in/spike/%s[0:%i]' % (lpu_j, lpu_i, conn_mat[i, j])) # The order of these two selectors is important; the individual 'from' # and 'to' ports must line up properly for Pattern.from_concat to # produce the right pattern: sel_from = Selector.add(sel_in_gpot_i, sel_in_spike_i, sel_in_gpot_j, sel_in_spike_j) sel_to = Selector.add(sel_out_gpot_j, sel_out_spike_j, sel_out_gpot_i, sel_out_spike_i) # Exclude scenarios where the "from" or "to" selector is empty (and # therefore cannot be used to construct a pattern): if len(sel_from) and len(sel_to): pat_sels[(lpu_i, lpu_j)] = \ (sel_from, sel_to, Selector.union(sel_in_gpot_i, sel_in_spike_i), Selector.union(sel_out_gpot_i, sel_out_spike_i), Selector.union(sel_in_gpot_i, sel_out_gpot_i), Selector.union(sel_in_spike_i, sel_out_spike_i), Selector.union(sel_in_gpot_j, sel_in_spike_j), Selector.union(sel_out_gpot_j, sel_out_spike_j), Selector.union(sel_in_gpot_j, sel_out_gpot_j), Selector.union(sel_in_spike_j, sel_out_spike_j)) return mod_sels, pat_sels
def gen_sels(n_lpu, n_spike, n_gpot): """ Generate port selectors for LPUs in benchmark test. Parameters ---------- n_lpu : int Number of LPUs. Must be at least 2. n_spike : int Total number of input and output spiking ports any single LPU exposes to any other LPU. Each LPU will therefore have 2*n_spike*(n_lpu-1) total spiking ports. n_gpot : int Total number of input and output graded potential ports any single LPU exposes to any other LPU. Each LPU will therefore have 2*n_gpot*(n_lpu-1) total graded potential ports. Returns ------- mod_sels : dict of tuples Ports in module interfaces; the keys are the module IDs and the values are tuples containing the respective selectors for all ports, all input ports, all output ports, all graded potential, and all spiking ports. pat_sels : dict of tuples Ports in pattern interfaces; the keys are tuples containing the two module IDs connected by the pattern and the values are pairs of tuples containing the respective selectors for all source ports, all destination ports, all input ports connected to the first module, all output ports connected to the first module, all graded potential ports connected to the first module, all spiking ports connected to the first module, all input ports connected to the second module, all output ports connected to the second module, all graded potential ports connected to the second module, and all spiking ports connected to the second module. """ assert n_lpu >= 2 assert n_spike >= 0 assert n_gpot >= 0 mod_sels = {} pat_sels = {('lpu%s' % i) : {} for i in xrange(n_lpu)} for i in xrange(n_lpu): lpu_id = 'lpu%s' % i other_lpu_ids = '['+','.join(['lpu%s' % j for j in xrange(n_lpu) if j != i])+']' # Structure ports as # /lpu_id/in_or_out/spike_or_gpot/[other_lpu_ids,..]/[0:n_spike] sel_in_gpot = Selector('/%s/in/gpot/%s/[0:%i]' % \ (lpu_id, other_lpu_ids, n_gpot)) sel_in_spike = Selector('/%s/in/spike/%s/[0:%i]' % \ (lpu_id, other_lpu_ids, n_spike)) sel_out_gpot = Selector('/%s/out/gpot/%s/[0:%i]' % \ (lpu_id, other_lpu_ids, n_gpot)) sel_out_spike = Selector('/%s/out/spike/%s/[0:%i]' % \ (lpu_id, other_lpu_ids, n_spike)) mod_sels[lpu_id] = (Selector.union(sel_in_gpot, sel_in_spike, sel_out_gpot, sel_out_spike), Selector.union(sel_in_gpot, sel_in_spike), Selector.union(sel_out_gpot, sel_out_spike), Selector.union(sel_in_gpot, sel_out_gpot), Selector.union(sel_in_spike, sel_out_spike)) for i, j in itertools.combinations(xrange(n_lpu), 2): lpu_i = 'lpu%s' % i lpu_j = 'lpu%s' % j sel_in_gpot_i = Selector('/%s/out/gpot/%s[0:%i]' % (lpu_i, lpu_j, n_gpot)) sel_in_spike_i = Selector('/%s/out/spike/%s[0:%i]' % (lpu_i, lpu_j, n_spike)) sel_out_gpot_i = Selector('/%s/in/gpot/%s[0:%i]' % (lpu_i, lpu_j, n_gpot)) sel_out_spike_i = Selector('/%s/in/spike/%s[0:%i]' % (lpu_i, lpu_j, n_spike)) sel_in_gpot_j = Selector('/%s/out/gpot/%s[0:%i]' % (lpu_j, lpu_i, n_gpot)) sel_in_spike_j = Selector('/%s/out/spike/%s[0:%i]' % (lpu_j, lpu_i, n_spike)) sel_out_gpot_j = Selector('/%s/in/gpot/%s[0:%i]' % (lpu_j, lpu_i, n_gpot)) sel_out_spike_j = Selector('/%s/in/spike/%s[0:%i]' % (lpu_j, lpu_i, n_spike)) # The order of these two selectors is important; the individual 'from' # and 'to' ports must line up properly for Pattern.from_concat to # produce the right pattern: sel_from = Selector.add(sel_in_gpot_i, sel_in_spike_i, sel_in_gpot_j, sel_in_spike_j) sel_to = Selector.add(sel_out_gpot_j, sel_out_spike_j, sel_out_gpot_i, sel_out_spike_i) pat_sels[(lpu_i, lpu_j)] = \ (sel_from, sel_to, Selector.union(sel_in_gpot_i, sel_in_spike_i), Selector.union(sel_out_gpot_i, sel_out_spike_i), Selector.union(sel_in_gpot_i, sel_out_gpot_i), Selector.union(sel_in_spike_i, sel_out_spike_i), Selector.union(sel_in_gpot_j, sel_in_spike_j), Selector.union(sel_out_gpot_j, sel_out_spike_j), Selector.union(sel_in_gpot_j, sel_out_gpot_j), Selector.union(sel_in_spike_j, sel_out_spike_j)) return mod_sels, pat_sels
lpu_name_to_sel_gpot = {} lpu_name_to_sel_spike = {} lpu_name_to_sel = {} for name in lpu_name_list: n_dict = lpu_name_to_n_dict[name] lpu_name_to_sel_in_gpot[name] = \ Selector(LPU.extract_in_gpot(n_dict)) lpu_name_to_sel_in_spike[name] = \ Selector(LPU.extract_in_spk(n_dict)) lpu_name_to_sel_out_gpot[name] = \ Selector(LPU.extract_out_gpot(n_dict)) lpu_name_to_sel_out_spike[name] = \ Selector(LPU.extract_out_spk(n_dict)) lpu_name_to_sel_in[name] = \ Selector.union(lpu_name_to_sel_in_gpot[name], lpu_name_to_sel_in_spike[name]) lpu_name_to_sel_out[name] = \ Selector.union(lpu_name_to_sel_out_gpot[name], lpu_name_to_sel_out_spike[name]) lpu_name_to_sel_gpot[name] = \ Selector.union(lpu_name_to_sel_in_gpot[name], lpu_name_to_sel_out_gpot[name]) lpu_name_to_sel_spike[name] = \ Selector.union(lpu_name_to_sel_in_spike[name], lpu_name_to_sel_out_spike[name]) lpu_name_to_sel[name] = Selector.union(lpu_name_to_sel_in[name], lpu_name_to_sel_out[name]) lpu_name_to_int = {} for name in lpu_name_list: lpu_name_to_int[name] = \ pattern.Interface.from_selectors(lpu_name_to_sel[name], lpu_name_to_sel_in[name], lpu_name_to_sel_out[name],
def emulate(n_lpu, n_spike, n_gpot, steps): """ Benchmark inter-LPU communication throughput. Each LPU is configured to use a different local GPU. Parameters ---------- n_lpu : int Number of LPUs. Must be at least 2 and no greater than the number of local GPUs. n_spike : int Total number of input and output spiking ports any single LPU exposes to any other LPU. Each LPU will therefore have 2*n_spike*(n_lpu-1) total spiking ports. n_gpot : int Total number of input and output graded potential ports any single LPU exposes to any other LPU. Each LPU will therefore have 2*n_gpot*(n_lpu-1) total graded potential ports. steps : int Number of steps to execute. Returns ------- average_throughput, total_throughput : float Average per-step and total received data throughput in bytes/seconds. exec_time : float Execution time in seconds. """ # Time everything starting with manager initialization: start_all = time.time() # Check whether a sufficient number of GPUs are available: drv.init() if n_lpu > drv.Device.count(): raise RuntimeError('insufficient number of available GPUs.') # Set up manager: man = Manager() # Generate selectors for configuring modules and patterns: mod_sels, pat_sels = gen_sels(n_lpu, n_spike, n_gpot) # Set up modules: for i in xrange(n_lpu): lpu_i = 'lpu%s' % i sel, sel_in, sel_out, sel_gpot, sel_spike = mod_sels[lpu_i] sel = Selector.union(sel_in, sel_out, sel_gpot, sel_spike) man.add(MyModule, lpu_i, sel, sel_in, sel_out, sel_gpot, sel_spike, None, None, ['interface', 'io', 'type'], CTRL_TAG, GPOT_TAG, SPIKE_TAG, device=i, time_sync=True) # Set up connections between module pairs: for i, j in itertools.combinations(xrange(n_lpu), 2): lpu_i = 'lpu%s' % i lpu_j = 'lpu%s' % j sel_from, sel_to, sel_in_i, sel_out_i, sel_gpot_i, sel_spike_i, \ sel_in_j, sel_out_j, sel_gpot_j, sel_spike_j = pat_sels[(lpu_i, lpu_j)] pat = Pattern.from_concat(sel_from, sel_to, from_sel=sel_from, to_sel=sel_to, data=1) pat.interface[sel_in_i, 'interface', 'io'] = [0, 'in'] pat.interface[sel_out_i, 'interface', 'io'] = [0, 'out'] pat.interface[sel_gpot_i, 'interface', 'type'] = [0, 'gpot'] pat.interface[sel_spike_i, 'interface', 'type'] = [0, 'spike'] pat.interface[sel_in_j, 'interface', 'io'] = [1, 'in'] pat.interface[sel_out_j, 'interface', 'io'] = [1, 'out'] pat.interface[sel_gpot_j, 'interface', 'type'] = [1, 'gpot'] pat.interface[sel_spike_j, 'interface', 'type'] = [1, 'spike'] man.connect(lpu_i, lpu_j, pat, 0, 1, compat_check=False) man.spawn() start_main = time.time() man.start(steps) man.wait() stop_main = time.time() return man.average_step_sync_time, (time.time()-start_all), \ (stop_main-start_main), (man.stop_time-man.start_time)