def get_component():
# Create a model, composed of an iaf neuron, and
iaf_2coba_model = ComponentClass(
name="iaf_1coba",
subnodes={"iaf": iaf.get_component(),
"cobaExcit": coba_synapse.get_component()})
# Connections have to be setup as strings, because we are deep-copying objects.
iaf_2coba_model.connect_ports("iaf.V", "cobaExcit.V")
iaf_2coba_model.connect_ports("cobaExcit.I", "iaf.ISyn")
return iaf_2coba_model
def get_component():
# Create a model, composed of an iaf neuron, and
iaf_nmda_model = ComponentClass(
name="iaf_2coba",
subnodes={"iaf": iaf.get_component(),
"nmda": nmda.get_component(),
'cobaExcit': coba_synapse.get_component()
})
iaf_nmda_model.connect_ports("iaf.V", "cobaExcit.V")
iaf_nmda_model.connect_ports("iaf.V", "nmda.V")
iaf_nmda_model.connect_ports("cobaExcit.I", "iaf.ISyn")
iaf_nmda_model.connect_ports("nmda.I", "iaf.ISyn")
return iaf_nmda_model
def test_regime(self):
# Signature: name(self, name=None)
# Find a regime in the component by name
# from nineml.abstraction_layer.component.componentqueryer import ComponentClassQueryer
c = ComponentClass(name='cl',
regimes=[
Regime('dX/dt=0',
name='r1',
transitions=On('X>X1',
do=['X=X0'],
to='r2')),
Regime('dX/dt=0',
name='r2',
transitions=On('X>X1',
do=['X=X0'],
to='r3')),
Regime('dX/dt=0',
name='r3',
transitions=On('X>X1',
do=['X=X0'],
to='r4')),
Regime('dX/dt=0',
name='r4',
transitions=On('X>X1',
do=['X=X0'],
to='r1')),
])
self.assertEqual(c.query.regime(name='r1').name, 'r1')
self.assertEqual(c.query.regime(name='r2').name, 'r2')
self.assertEqual(c.query.regime(name='r3').name, 'r3')
self.assertEqual(c.query.regime(name='r4').name, 'r4')
def test_backsub_all(self):
# Check the aliases:
# ====================== #
c2 = ComponentClass(name='C1', aliases=['A:=1+2', 'B:=5*A', 'C:=B+2'])
self.assertEqual(c2.aliases_map['A'].rhs_as_python_func()(), 3)
# This should assert, because its not yet back-subbed
c2.backsub_all()
self.assertEqual(c2.aliases_map['B'].rhs_as_python_func()(), 15)
# Check the ordering:
self.assertEqual(c2.aliases_map['C'].rhs_as_python_func()(), ((5 * (3)) + 2))
# ====================== #
# Check the equations:
# ====================== #
warnings.warn('Tests not implemented')
def test_get_fully_qualified_port_connections(self):
# Signature: name(self)
# Used by the flattening code.
#
# This method returns a d list of tuples of the
# the fully-qualified port connections
# from nineml.abstraction_layer.component.componentqueryer import ComponentQueryer
# Signature: name(self)
# Get the namespace address of this component
d = ComponentClass(
name='D', aliases=['A:=1', 'B:=2'], analog_ports=[AnalogSendPort('A'), AnalogSendPort('B')])
e = ComponentClass(name='E', analog_ports=[AnalogReceivePort('C')])
f = ComponentClass(name='F', analog_ports=[AnalogReceivePort('D')])
g = ComponentClass(name='G', analog_ports=[AnalogReceivePort('E')])
b = ComponentClass(name='B', subnodes={
'd': d, 'e': e}, portconnections=[('d.A', 'e.C')])
c = ComponentClass(name='C',
aliases=['G:=-1'],
analog_ports=[AnalogSendPort('G')],
subnodes={'f': f, 'g': g},
portconnections=[('G', 'f.D')])
a = ComponentClass(name='A',
subnodes={'b': b, 'c': c},
analog_ports=[AnalogReceivePort('F')],
portconnections=[('b.d.A', 'F')]
)
bNew = a.get_subnode('b')
cNew = a.get_subnode('c')
# dNew = a.get_subnode('b.d')
# eNew = a.get_subnode('b.e')
# fNew = a.get_subnode('c.f')
# gNew = a.get_subnode('c.g')
self.assertEquals(list(a.query.get_fully_qualified_port_connections()),
[(NamespaceAddress('b.d.A'), NamespaceAddress('F'))])
self.assertEquals(list(bNew.query.get_fully_qualified_port_connections()),
[(NamespaceAddress('b.d.A'), NamespaceAddress('b.e.C'))])
self.assertEquals(list(cNew.query.get_fully_qualified_port_connections()),
[(NamespaceAddress('c.G'), NamespaceAddress('c.f.D'))])
def test_get_node_addr(self):
# Signature: name(self)
# Get the namespace address of this component
d = ComponentClass(name='D',)
e = ComponentClass(name='E')
f = ComponentClass(name='F')
g = ComponentClass(name='G')
b = ComponentClass(name='B', subnodes={'d': d, 'e': e})
c = ComponentClass(name='C', subnodes={'f': f, 'g': g})
a = ComponentClass(name='A', subnodes={'b': b, 'c': c})
# Construction of the objects causes cloning to happen:
# Therefore we test by looking up and checking that there
# are the correct component names:
bNew = a.get_subnode('b')
cNew = a.get_subnode('c')
dNew = a.get_subnode('b.d')
eNew = a.get_subnode('b.e')
fNew = a.get_subnode('c.f')
gNew = a.get_subnode('c.g')
self.assertEquals(a.get_node_addr(),
NamespaceAddress.create_root())
self.assertEquals(bNew.get_node_addr(),
NamespaceAddress('b'))
self.assertEquals(cNew.get_node_addr(),
NamespaceAddress('c'))
self.assertEquals(dNew.get_node_addr(),
NamespaceAddress('b.d'))
self.assertEquals(eNew.get_node_addr(),
NamespaceAddress('b.e'))
self.assertEquals(fNew.get_node_addr(),
NamespaceAddress('c.f'))
self.assertEquals(gNew.get_node_addr(),
NamespaceAddress('c.g'))
self.assertEquals(a.name, 'A')
self.assertEquals(bNew.name, 'B')
self.assertEquals(cNew.name, 'C')
self.assertEquals(dNew.name, 'D')
self.assertEquals(eNew.name, 'E')
self.assertEquals(fNew.name, 'F')
self.assertEquals(gNew.name, 'G')
def test_get_fully_qualified_port_connections(self):
# Signature: name(self)
# Used by the flattening code.
#
# This method returns a d list of tuples of the
# the fully-qualified port connections
# from nineml.abstraction_layer.component.componentqueryer import ComponentClassQueryer
# Signature: name(self)
# Get the namespace address of this component
d = ComponentClass(
name='D',
aliases=['A:=1', 'B:=2'],
analog_ports=[AnalogSendPort('A'),
AnalogSendPort('B')])
e = ComponentClass(name='E', analog_ports=[AnalogReceivePort('C')])
f = ComponentClass(name='F', analog_ports=[AnalogReceivePort('D')])
g = ComponentClass(name='G', analog_ports=[AnalogReceivePort('E')])
b = ComponentClass(name='B',
subnodes={
'd': d,
'e': e
},
portconnections=[('d.A', 'e.C')])
c = ComponentClass(name='C',
aliases=['G:=-1'],
analog_ports=[AnalogSendPort('G')],
subnodes={
'f': f,
'g': g
},
portconnections=[('G', 'f.D')])
a = ComponentClass(name='A',
subnodes={
'b': b,
'c': c
},
analog_ports=[AnalogReceivePort('F')],
portconnections=[('b.d.A', 'F')])
bNew = a.get_subnode('b')
cNew = a.get_subnode('c')
# dNew = a.get_subnode('b.d')
# eNew = a.get_subnode('b.e')
# fNew = a.get_subnode('c.f')
# gNew = a.get_subnode('c.g')
self.assertEquals(list(a.query.get_fully_qualified_port_connections()),
[(NamespaceAddress('b.d.A'), NamespaceAddress('F'))])
self.assertEquals(
list(bNew.query.get_fully_qualified_port_connections()),
[(NamespaceAddress('b.d.A'), NamespaceAddress('b.e.C'))])
self.assertEquals(
list(cNew.query.get_fully_qualified_port_connections()),
[(NamespaceAddress('c.G'), NamespaceAddress('c.f.D'))])
def get_component():
# Create a model, composed of an iaf neuron, and
iaf_3coba_model = ComponentClass(name="iaf_3coba",
subnodes={"iaf": iaf.get_component(),
"AMPA": coba_synapse.get_component(),
"GABAa": coba_synapse.get_component(),
"GABAb": coba_synapse.get_component(),
})
# Connections have to be setup as strings, because we are deep-copying objects.
iaf_3coba_model.connect_ports("iaf.V", "AMPA.V")
iaf_3coba_model.connect_ports("iaf.V", "GABAa.V")
iaf_3coba_model.connect_ports("iaf.V", "GABAb.V")
iaf_3coba_model.connect_ports("AMPA.I", "iaf.ISyn")
iaf_3coba_model.connect_ports("GABAa.I", "iaf.ISyn")
iaf_3coba_model.connect_ports("GABAb.I", "iaf.ISyn")
return iaf_3coba_model
def test_get_subns_addr(self):
# Signature: name(self, component_name)
# Returns the address of a subcomponent at this address.
#
# For example:
#
# >>> a = NamespaceAddress('level1.level2.level3')
# >>> a.get_subns_addr('subcomponent')
# NameSpaceAddress: '/level1/level2/level3/subcomponent/'
d = ComponentClass(name='D',)
e = ComponentClass(name='E')
f = ComponentClass(name='F')
g = ComponentClass(name='G')
b = ComponentClass(name='B', subnodes={'atD': d, 'atE': e})
c = ComponentClass(name='C', subnodes={'atF': f, 'atG': g})
a = ComponentClass(name='A', subnodes={'atB': b, 'atC': c})
# Construction of the objects causes cloning to happen:
# Therefore we test by looking up and checking that there
# are the correct component names:
bNew = a.get_subnode('atB')
cNew = a.get_subnode('atC')
dNew = a.get_subnode('atB.atD')
eNew = a.get_subnode('atB.atE')
fNew = a.get_subnode('atC.atF')
gNew = a.get_subnode('atC.atG')
self.assertEquals(
gNew.get_node_addr().get_subns_addr('MyObject1'),
NSA('atC.atG.MyObject1')
)
self.assertEquals(
eNew.get_node_addr().get_subns_addr('MyObject2'),
NSA('atB.atE.MyObject2')
)
self.assertEquals(
bNew.get_node_addr().get_subns_addr('MyObject3'),
NSA('atB.MyObject3')
)
def test_ports(self):
# Signature: name
# Return an iterator over all the port (Event & Analog) in the
# component
# from nineml.abstraction_layer.component.componentqueryer import ComponentClassQueryer
c = ComponentClass(name='Comp1',
regimes=[
Regime(name='r1',
transitions=[
On('spikeinput1', do=[]),
On('spikeinput2',
do=OutputEvent('ev_port2'),
to='r2'),
]),
Regime(name='r2',
transitions=[
On('V > a',
do=OutputEvent('ev_port2')),
On('spikeinput3',
do=OutputEvent('ev_port3'),
to='r1'),
])
],
aliases=['A:=0', 'C:=0'],
analog_ports=[
AnalogSendPort('A'),
AnalogReceivePort('B'),
AnalogSendPort('C')
])
ports = list(c.query.ports)
port_names = [p.name for p in ports]
self.assertEquals(len(port_names), 8)
self.assertEquals(
set(port_names),
set([
'A', 'B', 'C', 'spikeinput1', 'spikeinput2', 'spikeinput3',
'ev_port2', 'ev_port3'
]))
def test_recurse_all_components(self):
# Signature: name
# Returns an iterator over this component and all subcomponents
d = ComponentClass(name='D')
e = ComponentClass(name='E')
f = ComponentClass(name='F')
g = ComponentClass(name='G')
b = ComponentClass(name='B')
b.insert_subnode(namespace='d', subnode=d)
b.insert_subnode(namespace='e', subnode=e)
c = ComponentClass(name='C')
c.insert_subnode(namespace='f', subnode=f)
c.insert_subnode(namespace='g', subnode=g)
a = ComponentClass(name='A')
a.insert_subnode(namespace='b', subnode=b)
a.insert_subnode(namespace='c', subnode=c)
# Construction of the objects causes cloning to happen:
# Therefore we test by looking up and checking that there
# are the correct component names:
bNew = a.get_subnode('b')
cNew = a.get_subnode('c')
dNew = a.get_subnode('b.d')
eNew = a.get_subnode('b.e')
fNew = a.get_subnode('c.f')
gNew = a.get_subnode('c.g')
self.assertEquals(set(a.query.recurse_all_components),
set([a, bNew, cNew, dNew, eNew, fNew, gNew]))
self.assertEquals(set(bNew.query.recurse_all_components),
set([bNew, dNew, eNew]))
self.assertEquals(set(cNew.query.recurse_all_components),
set([cNew, fNew, gNew]))
self.assertEquals(set(dNew.query.recurse_all_components), set([dNew]))
self.assertEquals(set(eNew.query.recurse_all_components), set([eNew]))
self.assertEquals(set(fNew.query.recurse_all_components), set([fNew]))
self.assertEquals(set(gNew.query.recurse_all_components), set([gNew]))
def test_get_subns_addr(self):
# Signature: name(self, component_name)
# Returns the address of a subcomponent at this address.
#
# For example:
#
# >>> a = NamespaceAddress('level1.level2.level3')
# >>> a.get_subns_addr('subcomponent')
# NameSpaceAddress: '/level1/level2/level3/subcomponent/'
d = ComponentClass(name='D', )
e = ComponentClass(name='E')
f = ComponentClass(name='F')
g = ComponentClass(name='G')
b = ComponentClass(name='B', subnodes={'atD': d, 'atE': e})
c = ComponentClass(name='C', subnodes={'atF': f, 'atG': g})
a = ComponentClass(name='A', subnodes={'atB': b, 'atC': c})
# Construction of the objects causes cloning to happen:
# Therefore we test by looking up and checking that there
# are the correct component names:
bNew = a.get_subnode('atB')
cNew = a.get_subnode('atC')
dNew = a.get_subnode('atB.atD')
eNew = a.get_subnode('atB.atE')
fNew = a.get_subnode('atC.atF')
gNew = a.get_subnode('atC.atG')
self.assertEquals(gNew.get_node_addr().get_subns_addr('MyObject1'),
NSA('atC.atG.MyObject1'))
self.assertEquals(eNew.get_node_addr().get_subns_addr('MyObject2'),
NSA('atB.atE.MyObject2'))
self.assertEquals(bNew.get_node_addr().get_subns_addr('MyObject3'),
NSA('atB.MyObject3'))
import numpy
from nineml.abstraction_layer.dynamics import (ComponentClass, Regime, On,
OutputEvent, SendPort)
from util import TestFixture
component = ComponentClass("LeakyIAF",
regimes=[
Regime(name="subthreshold_regime",
time_derivatives=[
"dV/dt = (-gL*(V-vL) + I)/C",
],
transitions=[
On("V> theta",
do=[
"t_spike = t", "V = V_reset",
OutputEvent('spikeoutput')
],
to="refractory_regime")
]),
Regime(name="refractory_regime",
transitions=[
On("t >= t_spike + t_ref",
to='subthreshold_regime')
])
],
analog_ports=[SendPort("V")])
parameters = p = {
'C': 1, # nF
'vL': -65, # mV
'I': 0.5, # nA
A test of injecting current into an Izhikevich neuron.
"""
from nineml.abstraction_layer.dynamics import (ComponentClass, Regime, On,
OutputEvent, SendPort)
from util import TestFixture
component = ComponentClass(
"Izhikevich",
regimes=[
Regime(name="subthreshold_regime",
time_derivatives=[
"dV/dt = 0.04*V*V + 5*V + 140.0 - U + Isyn",
"dU/dt = a*(b*V - U)"
],
transitions=[
On("V > theta",
do=["V = c", "U = U + d",
OutputEvent('spikeoutput')])
])
],
analog_ports=[SendPort("V")])
parameters = {
'a': 0.02,
'b': 0.2,
'c': -50,
'd': 2,
'Isyn': 15,
'theta': 0,
def test_insert_subnode(self):
# Signature: name(self, subnode, namespace)
# Insert a subnode into this component
#
#
# :param subnode: An object of type ``ComponentClass``.
# :param namespace: A `string` specifying the name of the component in
# this components namespace.
#
# :raises: ``NineMLRuntimeException`` if there is already a subcomponent at
# the same namespace location
#
# .. note::
#
# This method will clone the subnode.
d = ComponentClass(name='D')
e = ComponentClass(name='E')
f = ComponentClass(name='F')
g = ComponentClass(name='G')
b = ComponentClass(name='B')
b.insert_subnode(namespace='d', subnode=d)
b.insert_subnode(namespace='e', subnode=e)
c = ComponentClass(name='C')
c.insert_subnode(namespace='f', subnode=f)
c.insert_subnode(namespace='g', subnode=g)
a = ComponentClass(name='A')
a.insert_subnode(namespace='b', subnode=b)
a.insert_subnode(namespace='c', subnode=c)
# Construction of the objects causes cloning to happen:
# Therefore we test by looking up and checking that there
# are the correct component names:
bNew = a.get_subnode('b')
cNew = a.get_subnode('c')
dNew = a.get_subnode('b.d')
eNew = a.get_subnode('b.e')
fNew = a.get_subnode('c.f')
gNew = a.get_subnode('c.g')
self.assertEquals(a.get_node_addr(),
NamespaceAddress.create_root())
self.assertEquals(bNew.get_node_addr(),
NamespaceAddress('b'))
self.assertEquals(cNew.get_node_addr(),
NamespaceAddress('c'))
self.assertEquals(dNew.get_node_addr(),
NamespaceAddress('b.d'))
self.assertEquals(eNew.get_node_addr(),
NamespaceAddress('b.e'))
self.assertEquals(fNew.get_node_addr(),
NamespaceAddress('c.f'))
self.assertEquals(gNew.get_node_addr(),
NamespaceAddress('c.g'))
self.assertEquals(a.name, 'A')
self.assertEquals(bNew.name, 'B')
self.assertEquals(cNew.name, 'C')
self.assertEquals(dNew.name, 'D')
self.assertEquals(eNew.name, 'E')
self.assertEquals(fNew.name, 'F')
self.assertEquals(gNew.name, 'G')
self.assertRaises(NineMLRuntimeError, a.get_subnode, 'x')
self.assertRaises(NineMLRuntimeError, a.get_subnode, 'a.')
self.assertRaises(NineMLRuntimeError, a.get_subnode, 'a.X')
self.assertRaises(NineMLRuntimeError, a.get_subnode, 'a.b.')
self.assertRaises(NineMLRuntimeError, a.get_subnode, 'a.b.X')
# Adding to the same namespace twice:
d1 = ComponentClass(name='D1')
d2 = ComponentClass(name='D2')
a = ComponentClass(name='B')
a.insert_subnode(namespace='d', subnode=d1)
self.assertRaises(
NineMLRuntimeError,
a.insert_subnode, namespace='d', subnode=d2)
def test_connect_ports(self):
# Signature: name(self, src, sink)
# Connects the ports of 2 subcomponents.
#
# The ports can be specified as ``string`` s or ``NamespaceAddresses`` es.
#
#
# :param src: The source port of one sub-component; this should either an
# event port or analog port, but it *must* be a send port.
#
# :param sink: The sink port of one sub-component; this should either an
# event port or analog port, but it *must* be either a 'recv' or a
# 'reduce' port.
tIaf = TestableComponent('iaf')
tCoba = TestableComponent('coba_synapse')
# Should be fine:
c = ComponentClass(name='C1',
subnodes={'iaf': tIaf(), 'coba': tCoba()})
c.connect_ports('iaf.V', 'coba.V')
c = ComponentClass(name='C1',
subnodes={'iaf': tIaf(), 'coba': tCoba()},
portconnections=[('iaf.V', 'coba.V')]
)
# Non existant Ports:
c = ComponentClass(name='C1',
subnodes={'iaf': tIaf(), 'coba': tCoba()})
self.assertRaises(
NineMLRuntimeError,
c.connect_ports, 'iaf.V1', 'coba.V')
self.assertRaises(
NineMLRuntimeError,
c.connect_ports, 'iaf.V', 'coba.V1')
self.assertRaises(
NineMLRuntimeError,
ComponentClass,
name='C1',
subnodes={'iaf': tIaf(), 'coba': tCoba()},
portconnections=[('iaf.V1', 'coba.V')]
)
self.assertRaises(
NineMLRuntimeError,
ComponentClass,
name='C1',
subnodes={'iaf': tIaf(), 'coba': tCoba()},
portconnections=[('iaf.V', 'coba.V1')]
)
# Connect ports the wronf way around:
# [Check the wright way around works:]
c = ComponentClass(name='C1',
subnodes={'iaf': tIaf(), 'coba': tCoba()},
portconnections=[('coba.I', 'iaf.ISyn')]
)
# And the wrong way around:
c = ComponentClass(name='C1',
subnodes={'iaf': tIaf(), 'coba': tCoba()})
self.assertRaises(
NineMLRuntimeError,
c.connect_ports, 'iaf.ISyn.', 'coba.I')
self.assertRaises(
NineMLRuntimeError,
c.connect_ports, 'coba.V', 'iaf.V')
# Error raised on duplicate port-connection:
c = ComponentClass(name='C1',
subnodes={'iaf': tIaf(), 'coba': tCoba()},
)
c.connect_ports('coba.I', 'iaf.ISyn')
self.assertRaises(
NineMLRuntimeError,
c.connect_ports, 'coba.I', 'iaf.ISyn')
component = ComponentClass(
"HodgkinHuxley",
aliases=[
"q10 := 3.0**((celsius - 6.3)/10.0)", # temperature correction factor
"alpha_m := -0.1*(V+40.0)/(exp(-(V+40.0)/10.0) - 1.0)", # m
"beta_m := 4.0*exp(-(V+65.0)/18.0)",
"mtau := 1/(q10*(alpha_m + beta_m))",
"minf := alpha_m/(alpha_m + beta_m)",
"alpha_h := 0.07*exp(-(V+65.0)/20.0)", # h
"beta_h := 1.0/(exp(-(V+35)/10.0) + 1.0)",
"htau := 1.0/(q10*(alpha_h + beta_h))",
"hinf := alpha_h/(alpha_h + beta_h)",
"alpha_n := -0.01*(V+55.0)/(exp(-(V+55.0)/10.0) - 1.0)", # n
"beta_n := 0.125*exp(-(V+65.0)/80.0)",
"ntau := 1.0/(q10*(alpha_n + beta_n))",
"ninf := alpha_n/(alpha_n + beta_n)",
"gna := gnabar*m*m*m*h",
"gk := gkbar*n*n*n*n",
"ina := gna*(ena - V)",
"ik := gk*(ek - V)",
"il := gl*(el - V )"],
regimes=[
Regime(
name="main",
time_derivatives=[
"dn/dt = (ninf-n)/ntau",
"dm/dt = (minf-m)/mtau",
"dh/dt = (hinf-h)/htau",
"dV/dt = (ina + ik + il + I)/C"],
transitions=On("V > theta", do=OutputEvent('spikeoutput')))],
analog_ports=[SendPort("V")],
parameters=['el', 'C', 'ek', 'ena', 'gkbar', 'gnabar', 'theta',
'gl', 'celsius', 'I']
)
Test of a mechanism that generates spikes at times given by the Fibonacci sequence (in milliseconds).
This is useless from a neuroscience perspective, but makes a nice test.
"""
from nineml.abstraction_layer.dynamics import (ComponentClass, Regime, On,
OutputEvent, SendPort)
from util import TestFixture
model = ComponentClass(
name="Fibonacci",
regimes=[
Regime(name="default",
transitions=On("t > t_next",
do=[
"t_next = a + b", "a = b", "b = t_next",
OutputEvent('spikeOutput')
]))
],
)
parameters = {}
initial_values = {
'a': 1, #0,
'b': 1,
't_next': 1
}
expected_output = [1, 2, 3, 5, 8, 13, 21, 34, 55, 89]
def test_recurse_all_components(self):
# Signature: name
# Returns an iterator over this component and all subcomponents
d = ComponentClass(name='D')
e = ComponentClass(name='E')
f = ComponentClass(name='F')
g = ComponentClass(name='G')
b = ComponentClass(name='B')
b.insert_subnode(namespace='d', subnode=d)
b.insert_subnode(namespace='e', subnode=e)
c = ComponentClass(name='C')
c.insert_subnode(namespace='f', subnode=f)
c.insert_subnode(namespace='g', subnode=g)
a = ComponentClass(name='A')
a.insert_subnode(namespace='b', subnode=b)
a.insert_subnode(namespace='c', subnode=c)
# Construction of the objects causes cloning to happen:
# Therefore we test by looking up and checking that there
# are the correct component names:
bNew = a.get_subnode('b')
cNew = a.get_subnode('c')
dNew = a.get_subnode('b.d')
eNew = a.get_subnode('b.e')
fNew = a.get_subnode('c.f')
gNew = a.get_subnode('c.g')
self.assertEquals(
set(a.query.recurse_all_components),
set([a, bNew, cNew, dNew, eNew, fNew, gNew]))
self.assertEquals(
set(bNew.query.recurse_all_components),
set([bNew, dNew, eNew]))
self.assertEquals(
set(cNew.query.recurse_all_components),
set([cNew, fNew, gNew]))
self.assertEquals(
set(dNew.query.recurse_all_components),
set([dNew]))
self.assertEquals(
set(eNew.query.recurse_all_components),
set([eNew]))
self.assertEquals(
set(fNew.query.recurse_all_components),
set([fNew]))
self.assertEquals(
set(gNew.query.recurse_all_components),
set([gNew]))
def test_Flattening4(self):
c = ComponentClass(
name='C',
aliases=['C1:=cp1', 'C2 := cIn1', 'C3 := SV1', 'C4:=cIn2'],
regimes=[
Regime(
'dSV1/dt = -SV1/cp2',
transitions=[
On('SV1>cp1', do=[OutputEvent('emit')]),
On('spikein', do=[OutputEvent('c_emit')])
],
name='r1',
),
Regime(name='r2', transitions=On('SV1>1', to='r1'))
],
analog_ports=[
AnalogReceivePort('cIn1'),
AnalogReceivePort('cIn2'),
AnalogSendPort('C1'),
AnalogSendPort('C2')
],
parameters=['cp1', 'cp2'])
d = ComponentClass(
name='D',
aliases=['D1:=dp1', 'D2 := dIn1 + dp2', 'D3 := SV1'],
regimes=[
Regime(
'dSV1/dt = -SV1/dp2',
transitions=[
On('SV1>dp1', do=[OutputEvent('emit')]),
On('spikein', do=[OutputEvent('d_emit')])
],
name='r1',
),
Regime(name='r2', transitions=On('SV1>1', to='r1'))
],
analog_ports=[
AnalogReceivePort('dIn1'),
AnalogReceivePort('dIn2'),
AnalogSendPort('D1'),
AnalogSendPort('D2')
],
parameters=['dp1', 'dp2'])
# Test Cloner, 2 levels of hierachy
# ------------------------------ #
# Everything should be as before:
b = ComponentClass(
name='B',
subnodes={
'c1': c,
'c2': c,
'd': d
},
portconnections=[('c1.C1', 'c2.cIn2'), ('c2.C1', 'c1.cIn1')],
)
a = ComponentClass(name='A',
subnodes={
'b': b,
'c': c
},
portconnections=[('b.c1.C1', 'b.c1.cIn2'),
('b.c1.C1', 'b.c2.cIn1'),
('b.c1.C2', 'b.d.dIn1')])
a_flat = flattening.flatten(a)
# Name
self.assertEqual(a_flat.name, 'A')
# Aliases
self.assertEqual(
set(a_flat.aliases_map.keys()),
set([
'b_c1_C1', 'b_c1_C2', 'b_c1_C3', 'b_c1_C4', 'b_c2_C1',
'b_c2_C2', 'b_c2_C3', 'b_c2_C4', 'b_d_D1', 'b_d_D2', 'b_d_D3',
'c_C1', 'c_C2', 'c_C3', 'c_C4'
]))
# - Regimes and Transitions:
self.assertEqual(len(a_flat.regimes_map), 16)
r_c1_1_c2_1_d_1_c_1 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r1 b.c2:r1 c:r1')
r_c1_1_c2_2_d_1_c_1 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r1 b.c2:r2 c:r1')
r_c1_2_c2_1_d_1_c_1 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r2 b.c2:r1 c:r1')
r_c1_2_c2_2_d_1_c_1 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r2 b.c2:r2 c:r1')
r_c1_1_c2_1_d_2_c_1 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r1 b.c2:r1 c:r1')
r_c1_1_c2_2_d_2_c_1 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r1 b.c2:r2 c:r1')
r_c1_2_c2_1_d_2_c_1 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r2 b.c2:r1 c:r1')
r_c1_2_c2_2_d_2_c_1 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r2 b.c2:r2 c:r1')
r_c1_1_c2_1_d_1_c_2 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r1 b.c2:r1 c:r2')
r_c1_1_c2_2_d_1_c_2 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r1 b.c2:r2 c:r2')
r_c1_2_c2_1_d_1_c_2 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r2 b.c2:r1 c:r2')
r_c1_2_c2_2_d_1_c_2 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r2 b.c2:r2 c:r2')
r_c1_1_c2_1_d_2_c_2 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r1 b.c2:r1 c:r2')
r_c1_1_c2_2_d_2_c_2 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r1 b.c2:r2 c:r2')
r_c1_2_c2_1_d_2_c_2 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r2 b.c2:r1 c:r2')
r_c1_2_c2_2_d_2_c_2 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r2 b.c2:r2 c:r2')
regimes = [
r_c1_1_c2_1_d_1_c_1, r_c1_1_c2_2_d_1_c_1, r_c1_2_c2_1_d_1_c_1,
r_c1_2_c2_2_d_1_c_1, r_c1_1_c2_1_d_2_c_1, r_c1_1_c2_2_d_2_c_1,
r_c1_2_c2_1_d_2_c_1, r_c1_2_c2_2_d_2_c_1, r_c1_1_c2_1_d_1_c_2,
r_c1_1_c2_2_d_1_c_2, r_c1_2_c2_1_d_1_c_2, r_c1_2_c2_2_d_1_c_2,
r_c1_1_c2_1_d_2_c_2, r_c1_1_c2_2_d_2_c_2, r_c1_2_c2_1_d_2_c_2,
r_c1_2_c2_2_d_2_c_2
]
self.assertEqual(len(set(regimes)), 16)
# Do we have the right number of on_events and on_conditions:
self.assertEqual(len(list(r_c1_1_c2_1_d_1_c_1.on_events)), 4)
self.assertEqual(len(list(r_c1_1_c2_1_d_1_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_1_c2_2_d_1_c_1.on_events)), 3)
self.assertEqual(len(list(r_c1_1_c2_2_d_1_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_1_d_1_c_1.on_events)), 3)
self.assertEqual(len(list(r_c1_2_c2_1_d_1_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_2_d_1_c_1.on_events)), 2)
self.assertEqual(len(list(r_c1_2_c2_2_d_1_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_1_c2_1_d_2_c_1.on_events)), 3)
self.assertEqual(len(list(r_c1_1_c2_1_d_2_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_1_c2_2_d_2_c_1.on_events)), 2)
self.assertEqual(len(list(r_c1_1_c2_2_d_2_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_1_d_2_c_1.on_events)), 2)
self.assertEqual(len(list(r_c1_2_c2_1_d_2_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_2_d_2_c_1.on_events)), 1)
self.assertEqual(len(list(r_c1_2_c2_2_d_2_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_1_c2_1_d_1_c_2.on_events)), 3)
self.assertEqual(len(list(r_c1_1_c2_1_d_1_c_2.on_conditions)), 4)
self.assertEqual(len(list(r_c1_1_c2_2_d_1_c_2.on_events)), 2)
self.assertEqual(len(list(r_c1_1_c2_2_d_1_c_2.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_1_d_1_c_2.on_events)), 2)
self.assertEqual(len(list(r_c1_2_c2_1_d_1_c_2.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_2_d_1_c_2.on_events)), 1)
self.assertEqual(len(list(r_c1_2_c2_2_d_1_c_2.on_conditions)), 4)
self.assertEqual(len(list(r_c1_1_c2_1_d_2_c_2.on_events)), 2)
self.assertEqual(len(list(r_c1_1_c2_1_d_2_c_2.on_conditions)), 4)
self.assertEqual(len(list(r_c1_1_c2_2_d_2_c_2.on_events)), 1)
self.assertEqual(len(list(r_c1_1_c2_2_d_2_c_2.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_1_d_2_c_2.on_events)), 1)
self.assertEqual(len(list(r_c1_2_c2_1_d_2_c_2.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_2_d_2_c_2.on_events)), 0)
self.assertEqual(len(list(r_c1_2_c2_2_d_2_c_2.on_conditions)), 4)
# All on_events return to thier same transition:
for r in a_flat.regimes:
for on_ev in r.on_events:
self.assertEquals(on_ev.target_regime, r)
# Check On-Event port names are remapped properly:
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_1_d_1_c_1.on_events]),
set(['c_spikein', 'b_c1_spikein', 'b_c2_spikein', 'b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_2_d_1_c_1.on_events]),
set(['c_spikein', 'b_c1_spikein', 'b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_1_d_1_c_1.on_events]),
set(['c_spikein', 'b_c2_spikein', 'b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_2_d_1_c_1.on_events]),
set(['c_spikein', 'b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_1_d_2_c_1.on_events]),
set(['c_spikein', 'b_c1_spikein', 'b_c2_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_2_d_2_c_1.on_events]),
set([
'c_spikein',
'b_c1_spikein',
]))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_1_d_2_c_1.on_events]),
set([
'c_spikein',
'b_c2_spikein',
]))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_2_d_2_c_1.on_events]),
set(['c_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_1_d_1_c_2.on_events]),
set(['b_c1_spikein', 'b_c2_spikein', 'b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_2_d_1_c_2.on_events]),
set(['b_c1_spikein', 'b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_1_d_1_c_2.on_events]),
set(['b_c2_spikein', 'b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_2_d_1_c_2.on_events]),
set(['b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_1_d_2_c_2.on_events]),
set(['b_c1_spikein', 'b_c2_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_2_d_2_c_2.on_events]),
set([
'b_c1_spikein',
]))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_1_d_2_c_2.on_events]),
set([
'b_c2_spikein',
]))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_2_d_2_c_2.on_events]),
set([]))
# ToDo: Check the OnConditions:
# - Ports & Parameters:
self.assertEqual(
set(a_flat.query.analog_ports_map.keys()),
set([
'b_c1_C1', 'b_c1_C2', 'b_c2_C1', 'b_c2_C2', 'b_d_dIn2',
'b_d_D1', 'b_d_D2', 'c_cIn1', 'c_cIn2', 'c_C1', 'c_C2'
]))
self.assertEqual(
set(a_flat.query.event_ports_map.keys()),
set([
'b_c1_spikein',
'b_c1_emit',
'b_c1_c_emit',
'b_c2_spikein',
'b_c2_emit',
'b_c2_c_emit',
'b_d_spikein',
'b_d_emit',
'b_d_d_emit',
'c_spikein',
'c_emit',
'c_c_emit',
]))
self.assertEqual(
set(a_flat.query.parameters_map.keys()),
set([
'c_cp1',
'c_cp2',
'b_c1_cp1',
'b_c1_cp2',
'b_c2_cp1',
'b_c2_cp2',
'b_d_dp1',
'b_d_dp2',
]))
self.assertEqual(set(a_flat.state_variables_map.keys()),
set(['b_c1_SV1', 'b_c2_SV1', 'b_d_SV1', 'c_SV1']))
# Back-sub everything - then do we get the correct port mappings:
a_flat.backsub_all()
self.assertEqual(set(a_flat.aliases_map['b_c2_C4'].rhs_atoms),
set(['b_c1_cp1']))
self.assertEqual(set(a_flat.aliases_map['b_c1_C2'].rhs_atoms),
set(['b_c2_cp1']))
self.assertEqual(set(a_flat.aliases_map['b_c1_C4'].rhs_atoms),
set(['b_c1_cp1']))
self.assertEqual(set(a_flat.aliases_map['b_c2_C2'].rhs_atoms),
set(['b_c1_cp1']))
self.assertEqual(set(a_flat.aliases_map['b_d_D2'].rhs_atoms),
set(['b_c2_cp1', 'b_d_dp2']))
A test of injecting current into a Morris-Lecar neuron.
"""
from nineml.abstraction_layer.dynamics import (ComponentClass, Regime, On,
OutputEvent, SendPort)
from util import TestFixture
component = ComponentClass(
"MorrisLecar",
regimes=[
Regime(name="subthreshold_regime",
transitions=[On("V > theta", do=OutputEvent('spikeoutput'))],
time_derivatives=[
"dV/dt = (g_l*(V_l - V) + I_ca + I_k + I)/C",
"dW/dt = lambda_W*(W_inf - W)",
])
],
aliases=[
"M_inf := 0.5*(1.0+tanh((V-V1)/V2))",
"W_inf := 0.5*(1.0+tanh((V-V3)/V4))",
"lambda_W := phi*cosh((V-V3)/(2.0*V4))", "I_ca := g_ca*M_inf*(V_ca-V)",
"I_k := g_k*W*(V_k-V)"
],
analog_ports=[SendPort("V"), SendPort("W")])
parameters = {
'C': 10,
'V1': -1.2,
'I': 100,
'phi': 0.04,
'V2': 18,
component = ComponentClass(
"IF_cond_exp",
regimes=[
Regime(
name="sub_threshold_regime",
time_derivatives=[
"dV/dt = (v_rest - V)/tau_m + (gE*(e_rev_E - V) + gI*(e_rev_I - V) + i_offset)/cm",
"dgE/dt = -gE/tau_syn_E",
"dgI/dt = -gI/tau_syn_I",
],
transitions=[
On("V > v_thresh",
do=[
"t_spike = t", "V = v_reset",
OutputEvent('spikeoutput')
],
to="refractory_regime"),
On('excitatory', do="gE=gE+q"),
On('inhibitory', do="gI=gI+q")
]),
Regime(name="refractory_regime",
time_derivatives=[
"dgE/dt = -gE/tau_syn_E",
"dgI/dt = -gI/tau_syn_I",
],
transitions=[
On("t >= t_spike + tau_refrac", to="sub_threshold_regime"),
On('excitatory', do="gE=gE+q"),
On('inhibitory', do="gI=gI+q")
]),
],
analog_ports=[
SendPort("V"),
SendPort("gE"),
SendPort("gI"),
RecvPort("q")
])
def test_Flattening1(self):
c = ComponentClass(name='C',
aliases=['C1:=cp1', 'C2 := cIn1', 'C3 := SV1'],
regimes=[
Regime(
'dSV1/dt = -SV1/cp2',
transitions=[
On('SV1>cp1', do=[OutputEvent('emit')]),
On('spikein',
do=[OutputEvent('c_emit')])
],
name='r1',
),
Regime(name='r2',
transitions=On('SV1>1', to='r1'))
],
analog_ports=[
AnalogReceivePort('cIn1'),
AnalogReceivePort('cIn2'),
AnalogSendPort('C1'),
AnalogSendPort('C2')
],
parameters=['cp1', 'cp2'])
d = ComponentClass(name='D',
aliases=['D1:=dp1', 'D2 := dIn1', 'D3 := SV1'],
regimes=[
Regime(
'dSV1/dt = -SV1/dp2',
transitions=[
On('SV1>dp1', do=[OutputEvent('emit')]),
On('spikein',
do=[OutputEvent('d_emit')])
],
name='r1',
),
Regime(name='r2',
transitions=On('SV1>1', to='r1'))
],
analog_ports=[
AnalogReceivePort('dIn1'),
AnalogReceivePort('dIn2'),
AnalogSendPort('D1'),
AnalogSendPort('D2')
],
parameters=['dp1', 'dp2'])
# Flatten a flat component
# Everything should be as before:
c_flat = flattening.flatten(c)
assert c_flat is not c
self.assertEqual(c_flat.name, 'C')
self.assertEqual(set(c_flat.aliases_map.keys()),
set(['C1', 'C2', 'C3']))
# - Regimes and Transitions:
self.assertEqual(set(c_flat.regimes_map.keys()), set(['r1', 'r2']))
self.assertEqual(len(list(c_flat.regimes_map['r1'].on_events)), 1)
self.assertEqual(len(list(c_flat.regimes_map['r1'].on_conditions)), 1)
self.assertEqual(len(list(c_flat.regimes_map['r2'].on_events)), 0)
self.assertEqual(len(list(c_flat.regimes_map['r2'].on_conditions)), 1)
self.assertEqual(len(list(c_flat.regimes_map['r2'].on_conditions)), 1)
# - Ports & Parameters:
self.assertEqual(set(c_flat.query.analog_ports_map.keys()),
set(['cIn2', 'cIn1', 'C1', 'C2']))
self.assertEqual(set(c_flat.query.event_ports_map.keys()),
set(['spikein', 'c_emit', 'emit']))
self.assertEqual(set(c_flat.query.parameters_map.keys()),
set(['cp1', 'cp2']))
self.assertEqual(set(c_flat.state_variables_map.keys()), set(['SV1']))
def test_event_send_recv_ports(self):
# Signature: name(self)
# Get the ``recv`` EventPorts
# from nineml.abstraction_layer.component.componentqueryer import ComponentClassQueryer
# Check inference of output event ports:
c = ComponentClass(
name='Comp1',
regimes=Regime(transitions=[
On('in_ev1', do=OutputEvent('ev_port1')),
On('V < b', do=OutputEvent('ev_port1')),
On('V < c', do=OutputEvent('ev_port2')),
]),
)
self.assertEquals(len(c.query.event_recv_ports), 1)
self.assertEquals((list(c.query.event_recv_ports)[0]).name, 'in_ev1')
self.assertEquals(len(c.query.event_send_ports), 2)
self.assertEquals((list(c.query.event_send_ports)[0]).name, 'ev_port1')
self.assertEquals((list(c.query.event_send_ports)[1]).name, 'ev_port2')
# Check inference of output event ports:
c = ComponentClass(name='Comp1',
regimes=[
Regime(name='r1',
transitions=[
On('V > a',
do=OutputEvent('ev_port1'),
to='r2'),
On('in_ev1',
do=OutputEvent('ev_port2')),
]),
Regime(name='r2',
transitions=[
On('V > a',
do=OutputEvent('ev_port2'),
to='r1'),
On('in_ev2',
do=OutputEvent('ev_port3')),
])
])
self.assertEquals(len(c.query.event_recv_ports), 2)
self.assertEquals((list(c.query.event_recv_ports)[0]).name, 'in_ev1')
self.assertEquals((list(c.query.event_recv_ports)[1]).name, 'in_ev2')
self.assertEquals(len(c.query.event_send_ports), 3)
self.assertEquals((list(c.query.event_send_ports)[0]).name, 'ev_port1')
self.assertEquals((list(c.query.event_send_ports)[1]).name, 'ev_port2')
self.assertEquals((list(c.query.event_send_ports)[2]).name, 'ev_port3')
# Check inference of output event ports:
c = ComponentClass(name='Comp1',
regimes=[
Regime(name='r1',
transitions=[
On('spikeinput1', do=[]),
On('spikeinput2',
do=[
OutputEvent('ev_port1'),
OutputEvent('ev_port2')
],
to='r2'),
]),
Regime(name='r2',
transitions=[
On('V > a',
do=OutputEvent('ev_port2')),
On('spikeinput3',
do=OutputEvent('ev_port3'),
to='r1'),
])
])
self.assertEquals(len(c.query.event_recv_ports), 3)
self.assertEquals((list(c.query.event_recv_ports)[0]).name,
'spikeinput1')
self.assertEquals((list(c.query.event_recv_ports)[1]).name,
'spikeinput2')
self.assertEquals((list(c.query.event_recv_ports)[2]).name,
'spikeinput3')
self.assertEquals(len(c.query.event_send_ports), 3)
self.assertEquals((list(c.query.event_send_ports)[0]).name, 'ev_port1')
self.assertEquals((list(c.query.event_send_ports)[1]).name, 'ev_port2')
self.assertEquals((list(c.query.event_send_ports)[2]).name, 'ev_port3')
def test_Flattening2(self):
c = ComponentClass(name='C',
aliases=['C1:=cp1', 'C2 := cIn1', 'C3 := SV1'],
regimes=[
Regime(
'dSV1/dt = -SV1/cp2',
transitions=[
On('SV1>cp1', do=[OutputEvent('emit')]),
On('spikein',
do=[OutputEvent('c_emit')])
],
name='r1',
),
Regime(name='r2',
transitions=On('SV1>1', to='r1'))
],
analog_ports=[
AnalogReceivePort('cIn1'),
AnalogReceivePort('cIn2'),
AnalogSendPort('C1'),
AnalogSendPort('C2')
],
parameters=['cp1', 'cp2'])
d = ComponentClass(name='D',
aliases=['D1:=dp1', 'D2 := dIn1', 'D3 := SV1'],
regimes=[
Regime(
'dSV1/dt = -SV1/dp2',
transitions=[
On('SV1>dp1', do=[OutputEvent('emit')]),
On('spikein',
do=[OutputEvent('d_emit')])
],
name='r1',
),
Regime(name='r2',
transitions=On('SV1>1', to='r1'))
],
analog_ports=[
AnalogReceivePort('dIn1'),
AnalogReceivePort('dIn2'),
AnalogSendPort('D1'),
AnalogSendPort('D2')
],
parameters=['dp1', 'dp2'])
# Test Cloner, 1 level of hierachy
# ------------------------------ #
# Everything should be as before:
b = ComponentClass(
name='B',
subnodes={
'c1': c,
'c2': c,
'd': d
},
# portconnections= [('c1.C1','c2.cIn1'),('c2.emit','c1.spikein'), ]
)
b_flat = flattening.flatten(b)
# Name
self.assertEqual(b_flat.name, 'B')
# Aliases
self.assertEqual(
set(b_flat.aliases_map.keys()),
set([
'c1_C1', 'c1_C2', 'c1_C3', 'c2_C1', 'c2_C2', 'c2_C3', 'd_D1',
'd_D2', 'd_D3'
]))
# - Regimes and Transitions:
self.assertEqual(len(b_flat.regimes_map), 8)
r_c1_1_c2_1_d_1 = b_flat.flattener.get_new_regime('d:r1 c1:r1 c2:r1 ')
r_c1_1_c2_2_d_1 = b_flat.flattener.get_new_regime('d:r1 c1:r1 c2:r2 ')
r_c1_2_c2_1_d_1 = b_flat.flattener.get_new_regime('d:r1 c1:r2 c2:r1')
r_c1_2_c2_2_d_1 = b_flat.flattener.get_new_regime('d:r1 c1:r2 c2:r2')
r_c1_1_c2_1_d_2 = b_flat.flattener.get_new_regime('d:r2 c1:r1 c2:r1 ')
r_c1_1_c2_2_d_2 = b_flat.flattener.get_new_regime('d:r2 c1:r1 c2:r2 ')
r_c1_2_c2_1_d_2 = b_flat.flattener.get_new_regime('d:r2 c1:r2 c2:r1')
r_c1_2_c2_2_d_2 = b_flat.flattener.get_new_regime('d:r2 c1:r2 c2:r2')
# Do we have the right number of on_events and on_conditions:
self.assertEqual(len(list(r_c1_1_c2_1_d_1.on_events)), 3)
self.assertEqual(len(list(r_c1_1_c2_1_d_1.on_conditions)), 3)
self.assertEqual(len(list(r_c1_1_c2_2_d_1.on_events)), 2)
self.assertEqual(len(list(r_c1_1_c2_2_d_1.on_conditions)), 3)
self.assertEqual(len(list(r_c1_2_c2_1_d_1.on_events)), 2)
self.assertEqual(len(list(r_c1_2_c2_1_d_1.on_conditions)), 3)
self.assertEqual(len(list(r_c1_2_c2_2_d_1.on_events)), 1)
self.assertEqual(len(list(r_c1_2_c2_2_d_1.on_conditions)), 3)
self.assertEqual(len(list(r_c1_1_c2_1_d_2.on_events)), 2)
self.assertEqual(len(list(r_c1_1_c2_1_d_2.on_conditions)), 3)
self.assertEqual(len(list(r_c1_1_c2_2_d_2.on_events)), 1)
self.assertEqual(len(list(r_c1_1_c2_2_d_2.on_conditions)), 3)
self.assertEqual(len(list(r_c1_2_c2_1_d_2.on_events)), 1)
self.assertEqual(len(list(r_c1_2_c2_1_d_2.on_conditions)), 3)
self.assertEqual(len(list(r_c1_2_c2_2_d_2.on_events)), 0)
self.assertEqual(len(list(r_c1_2_c2_2_d_2.on_conditions)), 3)
# All on_events return to thier same transition:
self.assertEqual((list(r_c1_1_c2_1_d_1.on_events))[0].target_regime,
r_c1_1_c2_1_d_1)
self.assertEqual((list(r_c1_1_c2_1_d_1.on_events))[1].target_regime,
r_c1_1_c2_1_d_1)
self.assertEqual((list(r_c1_1_c2_1_d_1.on_events))[2].target_regime,
r_c1_1_c2_1_d_1)
self.assertEqual((list(r_c1_1_c2_2_d_1.on_events))[0].target_regime,
r_c1_1_c2_2_d_1)
self.assertEqual((list(r_c1_1_c2_2_d_1.on_events))[1].target_regime,
r_c1_1_c2_2_d_1)
self.assertEqual((list(r_c1_2_c2_1_d_1.on_events))[0].target_regime,
r_c1_2_c2_1_d_1)
self.assertEqual((list(r_c1_2_c2_1_d_1.on_events))[1].target_regime,
r_c1_2_c2_1_d_1)
self.assertEqual((list(r_c1_2_c2_2_d_1.on_events))[0].target_regime,
r_c1_2_c2_2_d_1)
self.assertEqual((list(r_c1_1_c2_1_d_2.on_events))[0].target_regime,
r_c1_1_c2_1_d_2)
self.assertEqual((list(r_c1_1_c2_1_d_2.on_events))[1].target_regime,
r_c1_1_c2_1_d_2)
self.assertEqual((list(r_c1_1_c2_2_d_2.on_events))[0].target_regime,
r_c1_1_c2_2_d_2)
self.assertEqual((list(r_c1_2_c2_1_d_2.on_events))[0].target_regime,
r_c1_2_c2_1_d_2)
# Check On-Event port names are remapped properly:
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_1_d_1.on_events]),
set(['c1_spikein', 'c2_spikein', 'd_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_2_d_1.on_events]),
set(['c1_spikein', 'd_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_1_d_1.on_events]),
set(['c2_spikein', 'd_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_2_d_1.on_events]),
set(['d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_1_d_2.on_events]),
set(['c1_spikein', 'c2_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_2_d_2.on_events]),
set([
'c1_spikein',
]))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_1_d_2.on_events]),
set([
'c2_spikein',
]))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_2_d_2.on_events]),
set([]))
# ToDo: Check the OnConditions:
# - Ports & Parameters:
self.assertEqual(
set(b_flat.query.analog_ports_map.keys()),
set([
'c1_cIn1', 'c1_cIn2', 'c1_C1', 'c1_C2', 'c2_cIn1', 'c2_cIn2',
'c2_C1', 'c2_C2', 'd_dIn1', 'd_dIn2', 'd_D1', 'd_D2'
]))
self.assertEqual(
set(b_flat.query.event_ports_map.keys()),
set([
'c1_spikein', 'c1_emit', 'c1_c_emit', 'c2_spikein', 'c2_emit',
'c2_c_emit', 'd_spikein', 'd_emit', 'd_d_emit'
]))
self.assertEqual(
set(b_flat.query.parameters_map.keys()),
set([
'c1_cp1',
'c1_cp2',
'c2_cp1',
'c2_cp2',
'd_dp1',
'd_dp2',
]))
self.assertEqual(set(b_flat.state_variables_map.keys()),
set(['c1_SV1', 'c2_SV1', 'd_SV1']))
