def test_get_fully_qualified_port_connections(self):
# Signature: name(self)
# Used by the flattening code.
#
# This method returns a d list of tuples of the
# the fully-qualified port connections
# from nineml.abstraction_layer.component.componentqueryer import ComponentClassQueryer
# Signature: name(self)
# Get the namespace address of this component
d = ComponentClass(
name='D',
aliases=['A:=1', 'B:=2'],
analog_ports=[AnalogSendPort('A'),
AnalogSendPort('B')])
e = ComponentClass(name='E', analog_ports=[AnalogReceivePort('C')])
f = ComponentClass(name='F', analog_ports=[AnalogReceivePort('D')])
g = ComponentClass(name='G', analog_ports=[AnalogReceivePort('E')])
b = ComponentClass(name='B',
subnodes={
'd': d,
'e': e
},
portconnections=[('d.A', 'e.C')])
c = ComponentClass(name='C',
aliases=['G:=-1'],
analog_ports=[AnalogSendPort('G')],
subnodes={
'f': f,
'g': g
},
portconnections=[('G', 'f.D')])
a = ComponentClass(name='A',
subnodes={
'b': b,
'c': c
},
analog_ports=[AnalogReceivePort('F')],
portconnections=[('b.d.A', 'F')])
bNew = a.get_subnode('b')
cNew = a.get_subnode('c')
# dNew = a.get_subnode('b.d')
# eNew = a.get_subnode('b.e')
# fNew = a.get_subnode('c.f')
# gNew = a.get_subnode('c.g')
self.assertEquals(list(a.query.get_fully_qualified_port_connections()),
[(NamespaceAddress('b.d.A'), NamespaceAddress('F'))])
self.assertEquals(
list(bNew.query.get_fully_qualified_port_connections()),
[(NamespaceAddress('b.d.A'), NamespaceAddress('b.e.C'))])
self.assertEquals(
list(cNew.query.get_fully_qualified_port_connections()),
[(NamespaceAddress('c.G'), NamespaceAddress('c.f.D'))])
def duplicate_port_name_event_analog(self):
# Check different names are OK:
ComponentClass(name='C1',
aliases=['A:=1'],
event_ports=[EventReceivePort('A')],
analog_ports=[AnalogSendPort('A')])
self.assertRaises(NineMLRuntimeError,
ComponentClass,
name='C1',
aliases=['A:=1'],
event_ports=[EventReceivePort('A')],
analog_ports=[AnalogSendPort('A')])
def test_accept_visitor(self):
# Check the Component is forwarding arguments:
class TestVisitor(object):
def visit(self, obj, **kwargs):
return obj.accept_visitor(self, **kwargs)
def visit_analogsendport(self, component, **kwargs):
return kwargs
def visit_analogreceiveport(self, component, **kwargs):
return kwargs
def visit_analogreduceport(self, component, **kwargs):
return kwargs
v = TestVisitor()
self.assertEqual(
v.visit(AnalogSendPort('V'), kwarg1='Hello', kwarg2='Hello2'),
{'kwarg1': 'Hello', 'kwarg2': 'Hello2'}
)
self.assertEqual(
v.visit(AnalogReceivePort('V'), kwarg1='Hello', kwarg2='Hello2'),
{'kwarg1': 'Hello', 'kwarg2': 'Hello2'}
)
self.assertEqual(
v.visit(AnalogReducePort('V', reduce_op='+'), kwarg1='Hello', kwarg2='Hello2'),
{'kwarg1': 'Hello', 'kwarg2': 'Hello2'}
)
def test_ports(self):
# Signature: name
# Return an iterator over all the port (Event & Analog) in the
# component
# from nineml.abstraction_layer.component.componentqueryer import ComponentClassQueryer
c = ComponentClass(name='Comp1',
regimes=[
Regime(name='r1',
transitions=[
On('spikeinput1', do=[]),
On('spikeinput2',
do=OutputEvent('ev_port2'),
to='r2'),
]),
Regime(name='r2',
transitions=[
On('V > a',
do=OutputEvent('ev_port2')),
On('spikeinput3',
do=OutputEvent('ev_port3'),
to='r1'),
])
],
aliases=['A:=0', 'C:=0'],
analog_ports=[
AnalogSendPort('A'),
AnalogReceivePort('B'),
AnalogSendPort('C')
])
ports = list(c.query.ports)
port_names = [p.name for p in ports]
self.assertEquals(len(port_names), 8)
self.assertEquals(
set(port_names),
set([
'A', 'B', 'C', 'spikeinput1', 'spikeinput2', 'spikeinput3',
'ev_port2', 'ev_port3'
]))
def test_analog_ports(self):
# Signature: name
# No Docstring
c = ComponentClass(name='C1')
self.assertEqual(len(list(c.analog_ports)), 0)
c = ComponentClass(name='C1')
self.assertEqual(len(list(c.analog_ports)), 0)
c = ComponentClass(name='C1',
aliases=['A:=2'],
analog_ports=[AnalogSendPort('A')])
self.assertEqual(len(list(c.analog_ports)), 1)
self.assertEqual(list(c.analog_ports)[0].mode, 'send')
self.assertEqual(len(c.query.analog_send_ports), 1)
self.assertEqual(len(c.query.analog_recv_ports), 0)
self.assertEqual(len(c.query.analog_reduce_ports), 0)
c = ComponentClass(name='C1', analog_ports=[AnalogReceivePort('B')])
self.assertEqual(len(list(c.analog_ports)), 1)
self.assertEqual(list(c.analog_ports)[0].mode, 'recv')
self.assertEqual(len(c.query.analog_send_ports), 0)
self.assertEqual(len(c.query.analog_recv_ports), 1)
self.assertEqual(len(c.query.analog_reduce_ports), 0)
c = ComponentClass(name='C1',
analog_ports=[AnalogReducePort('B', reduce_op='+')])
self.assertEqual(len(list(c.analog_ports)), 1)
self.assertEqual(list(c.analog_ports)[0].mode, 'reduce')
self.assertEqual(list(c.analog_ports)[0].reduce_op, '+')
self.assertEqual(len(c.query.analog_send_ports), 0)
self.assertEqual(len(c.query.analog_recv_ports), 0)
self.assertEqual(len(c.query.analog_reduce_ports), 1)
# Duplicate Port Names:
self.assertRaises(NineMLRuntimeError,
ComponentClass,
name='C1',
aliases=['A:=1'],
analog_ports=[
AnalogReducePort('B', reduce_op='+'),
AnalogSendPort('B')
])
self.assertRaises(
NineMLRuntimeError,
ComponentClass,
name='C1',
aliases=['A:=1'],
analog_ports=[AnalogSendPort('A'),
AnalogSendPort('A')])
self.assertRaises(
NineMLRuntimeError,
ComponentClass,
name='C1',
aliases=['A:=1'],
analog_ports=[AnalogReceivePort('A'),
AnalogReceivePort('A')])
self.assertRaises(
NineMLRuntimeError,
lambda: ComponentClass(name='C1',
analog_ports=[AnalogReceivePort('1')]))
self.assertRaises(
NineMLRuntimeError,
lambda: ComponentClass(name='C1',
analog_ports=[AnalogReceivePort('?')]))
def test_name(self):
# Signature: name
# The name of the port, local to the current component
self.assertEqual(AnalogReceivePort('A').name, 'A')
self.assertEqual(AnalogReducePort('B', reduce_op='+').name, 'B')
self.assertEqual(AnalogSendPort('C').name, 'C')
def test_Flattening2(self):
c = ComponentClass(name='C',
aliases=['C1:=cp1', 'C2 := cIn1', 'C3 := SV1'],
regimes=[
Regime(
'dSV1/dt = -SV1/cp2',
transitions=[
On('SV1>cp1', do=[OutputEvent('emit')]),
On('spikein',
do=[OutputEvent('c_emit')])
],
name='r1',
),
Regime(name='r2',
transitions=On('SV1>1', to='r1'))
],
analog_ports=[
AnalogReceivePort('cIn1'),
AnalogReceivePort('cIn2'),
AnalogSendPort('C1'),
AnalogSendPort('C2')
],
parameters=['cp1', 'cp2'])
d = ComponentClass(name='D',
aliases=['D1:=dp1', 'D2 := dIn1', 'D3 := SV1'],
regimes=[
Regime(
'dSV1/dt = -SV1/dp2',
transitions=[
On('SV1>dp1', do=[OutputEvent('emit')]),
On('spikein',
do=[OutputEvent('d_emit')])
],
name='r1',
),
Regime(name='r2',
transitions=On('SV1>1', to='r1'))
],
analog_ports=[
AnalogReceivePort('dIn1'),
AnalogReceivePort('dIn2'),
AnalogSendPort('D1'),
AnalogSendPort('D2')
],
parameters=['dp1', 'dp2'])
# Test Cloner, 1 level of hierachy
# ------------------------------ #
# Everything should be as before:
b = ComponentClass(
name='B',
subnodes={
'c1': c,
'c2': c,
'd': d
},
# portconnections= [('c1.C1','c2.cIn1'),('c2.emit','c1.spikein'), ]
)
b_flat = flattening.flatten(b)
# Name
self.assertEqual(b_flat.name, 'B')
# Aliases
self.assertEqual(
set(b_flat.aliases_map.keys()),
set([
'c1_C1', 'c1_C2', 'c1_C3', 'c2_C1', 'c2_C2', 'c2_C3', 'd_D1',
'd_D2', 'd_D3'
]))
# - Regimes and Transitions:
self.assertEqual(len(b_flat.regimes_map), 8)
r_c1_1_c2_1_d_1 = b_flat.flattener.get_new_regime('d:r1 c1:r1 c2:r1 ')
r_c1_1_c2_2_d_1 = b_flat.flattener.get_new_regime('d:r1 c1:r1 c2:r2 ')
r_c1_2_c2_1_d_1 = b_flat.flattener.get_new_regime('d:r1 c1:r2 c2:r1')
r_c1_2_c2_2_d_1 = b_flat.flattener.get_new_regime('d:r1 c1:r2 c2:r2')
r_c1_1_c2_1_d_2 = b_flat.flattener.get_new_regime('d:r2 c1:r1 c2:r1 ')
r_c1_1_c2_2_d_2 = b_flat.flattener.get_new_regime('d:r2 c1:r1 c2:r2 ')
r_c1_2_c2_1_d_2 = b_flat.flattener.get_new_regime('d:r2 c1:r2 c2:r1')
r_c1_2_c2_2_d_2 = b_flat.flattener.get_new_regime('d:r2 c1:r2 c2:r2')
# Do we have the right number of on_events and on_conditions:
self.assertEqual(len(list(r_c1_1_c2_1_d_1.on_events)), 3)
self.assertEqual(len(list(r_c1_1_c2_1_d_1.on_conditions)), 3)
self.assertEqual(len(list(r_c1_1_c2_2_d_1.on_events)), 2)
self.assertEqual(len(list(r_c1_1_c2_2_d_1.on_conditions)), 3)
self.assertEqual(len(list(r_c1_2_c2_1_d_1.on_events)), 2)
self.assertEqual(len(list(r_c1_2_c2_1_d_1.on_conditions)), 3)
self.assertEqual(len(list(r_c1_2_c2_2_d_1.on_events)), 1)
self.assertEqual(len(list(r_c1_2_c2_2_d_1.on_conditions)), 3)
self.assertEqual(len(list(r_c1_1_c2_1_d_2.on_events)), 2)
self.assertEqual(len(list(r_c1_1_c2_1_d_2.on_conditions)), 3)
self.assertEqual(len(list(r_c1_1_c2_2_d_2.on_events)), 1)
self.assertEqual(len(list(r_c1_1_c2_2_d_2.on_conditions)), 3)
self.assertEqual(len(list(r_c1_2_c2_1_d_2.on_events)), 1)
self.assertEqual(len(list(r_c1_2_c2_1_d_2.on_conditions)), 3)
self.assertEqual(len(list(r_c1_2_c2_2_d_2.on_events)), 0)
self.assertEqual(len(list(r_c1_2_c2_2_d_2.on_conditions)), 3)
# All on_events return to thier same transition:
self.assertEqual((list(r_c1_1_c2_1_d_1.on_events))[0].target_regime,
r_c1_1_c2_1_d_1)
self.assertEqual((list(r_c1_1_c2_1_d_1.on_events))[1].target_regime,
r_c1_1_c2_1_d_1)
self.assertEqual((list(r_c1_1_c2_1_d_1.on_events))[2].target_regime,
r_c1_1_c2_1_d_1)
self.assertEqual((list(r_c1_1_c2_2_d_1.on_events))[0].target_regime,
r_c1_1_c2_2_d_1)
self.assertEqual((list(r_c1_1_c2_2_d_1.on_events))[1].target_regime,
r_c1_1_c2_2_d_1)
self.assertEqual((list(r_c1_2_c2_1_d_1.on_events))[0].target_regime,
r_c1_2_c2_1_d_1)
self.assertEqual((list(r_c1_2_c2_1_d_1.on_events))[1].target_regime,
r_c1_2_c2_1_d_1)
self.assertEqual((list(r_c1_2_c2_2_d_1.on_events))[0].target_regime,
r_c1_2_c2_2_d_1)
self.assertEqual((list(r_c1_1_c2_1_d_2.on_events))[0].target_regime,
r_c1_1_c2_1_d_2)
self.assertEqual((list(r_c1_1_c2_1_d_2.on_events))[1].target_regime,
r_c1_1_c2_1_d_2)
self.assertEqual((list(r_c1_1_c2_2_d_2.on_events))[0].target_regime,
r_c1_1_c2_2_d_2)
self.assertEqual((list(r_c1_2_c2_1_d_2.on_events))[0].target_regime,
r_c1_2_c2_1_d_2)
# Check On-Event port names are remapped properly:
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_1_d_1.on_events]),
set(['c1_spikein', 'c2_spikein', 'd_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_2_d_1.on_events]),
set(['c1_spikein', 'd_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_1_d_1.on_events]),
set(['c2_spikein', 'd_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_2_d_1.on_events]),
set(['d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_1_d_2.on_events]),
set(['c1_spikein', 'c2_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_2_d_2.on_events]),
set([
'c1_spikein',
]))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_1_d_2.on_events]),
set([
'c2_spikein',
]))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_2_d_2.on_events]),
set([]))
# ToDo: Check the OnConditions:
# - Ports & Parameters:
self.assertEqual(
set(b_flat.query.analog_ports_map.keys()),
set([
'c1_cIn1', 'c1_cIn2', 'c1_C1', 'c1_C2', 'c2_cIn1', 'c2_cIn2',
'c2_C1', 'c2_C2', 'd_dIn1', 'd_dIn2', 'd_D1', 'd_D2'
]))
self.assertEqual(
set(b_flat.query.event_ports_map.keys()),
set([
'c1_spikein', 'c1_emit', 'c1_c_emit', 'c2_spikein', 'c2_emit',
'c2_c_emit', 'd_spikein', 'd_emit', 'd_d_emit'
]))
self.assertEqual(
set(b_flat.query.parameters_map.keys()),
set([
'c1_cp1',
'c1_cp2',
'c2_cp1',
'c2_cp2',
'd_dp1',
'd_dp2',
]))
self.assertEqual(set(b_flat.state_variables_map.keys()),
set(['c1_SV1', 'c2_SV1', 'd_SV1']))
def test_Flattening1(self):
c = ComponentClass(name='C',
aliases=['C1:=cp1', 'C2 := cIn1', 'C3 := SV1'],
regimes=[
Regime(
'dSV1/dt = -SV1/cp2',
transitions=[
On('SV1>cp1', do=[OutputEvent('emit')]),
On('spikein',
do=[OutputEvent('c_emit')])
],
name='r1',
),
Regime(name='r2',
transitions=On('SV1>1', to='r1'))
],
analog_ports=[
AnalogReceivePort('cIn1'),
AnalogReceivePort('cIn2'),
AnalogSendPort('C1'),
AnalogSendPort('C2')
],
parameters=['cp1', 'cp2'])
d = ComponentClass(name='D',
aliases=['D1:=dp1', 'D2 := dIn1', 'D3 := SV1'],
regimes=[
Regime(
'dSV1/dt = -SV1/dp2',
transitions=[
On('SV1>dp1', do=[OutputEvent('emit')]),
On('spikein',
do=[OutputEvent('d_emit')])
],
name='r1',
),
Regime(name='r2',
transitions=On('SV1>1', to='r1'))
],
analog_ports=[
AnalogReceivePort('dIn1'),
AnalogReceivePort('dIn2'),
AnalogSendPort('D1'),
AnalogSendPort('D2')
],
parameters=['dp1', 'dp2'])
# Flatten a flat component
# Everything should be as before:
c_flat = flattening.flatten(c)
assert c_flat is not c
self.assertEqual(c_flat.name, 'C')
self.assertEqual(set(c_flat.aliases_map.keys()),
set(['C1', 'C2', 'C3']))
# - Regimes and Transitions:
self.assertEqual(set(c_flat.regimes_map.keys()), set(['r1', 'r2']))
self.assertEqual(len(list(c_flat.regimes_map['r1'].on_events)), 1)
self.assertEqual(len(list(c_flat.regimes_map['r1'].on_conditions)), 1)
self.assertEqual(len(list(c_flat.regimes_map['r2'].on_events)), 0)
self.assertEqual(len(list(c_flat.regimes_map['r2'].on_conditions)), 1)
self.assertEqual(len(list(c_flat.regimes_map['r2'].on_conditions)), 1)
# - Ports & Parameters:
self.assertEqual(set(c_flat.query.analog_ports_map.keys()),
set(['cIn2', 'cIn1', 'C1', 'C2']))
self.assertEqual(set(c_flat.query.event_ports_map.keys()),
set(['spikein', 'c_emit', 'emit']))
self.assertEqual(set(c_flat.query.parameters_map.keys()),
set(['cp1', 'cp2']))
self.assertEqual(set(c_flat.state_variables_map.keys()), set(['SV1']))
def test_Flattening4(self):
c = ComponentClass(
name='C',
aliases=['C1:=cp1', 'C2 := cIn1', 'C3 := SV1', 'C4:=cIn2'],
regimes=[
Regime(
'dSV1/dt = -SV1/cp2',
transitions=[
On('SV1>cp1', do=[OutputEvent('emit')]),
On('spikein', do=[OutputEvent('c_emit')])
],
name='r1',
),
Regime(name='r2', transitions=On('SV1>1', to='r1'))
],
analog_ports=[
AnalogReceivePort('cIn1'),
AnalogReceivePort('cIn2'),
AnalogSendPort('C1'),
AnalogSendPort('C2')
],
parameters=['cp1', 'cp2'])
d = ComponentClass(
name='D',
aliases=['D1:=dp1', 'D2 := dIn1 + dp2', 'D3 := SV1'],
regimes=[
Regime(
'dSV1/dt = -SV1/dp2',
transitions=[
On('SV1>dp1', do=[OutputEvent('emit')]),
On('spikein', do=[OutputEvent('d_emit')])
],
name='r1',
),
Regime(name='r2', transitions=On('SV1>1', to='r1'))
],
analog_ports=[
AnalogReceivePort('dIn1'),
AnalogReceivePort('dIn2'),
AnalogSendPort('D1'),
AnalogSendPort('D2')
],
parameters=['dp1', 'dp2'])
# Test Cloner, 2 levels of hierachy
# ------------------------------ #
# Everything should be as before:
b = ComponentClass(
name='B',
subnodes={
'c1': c,
'c2': c,
'd': d
},
portconnections=[('c1.C1', 'c2.cIn2'), ('c2.C1', 'c1.cIn1')],
)
a = ComponentClass(name='A',
subnodes={
'b': b,
'c': c
},
portconnections=[('b.c1.C1', 'b.c1.cIn2'),
('b.c1.C1', 'b.c2.cIn1'),
('b.c1.C2', 'b.d.dIn1')])
a_flat = flattening.flatten(a)
# Name
self.assertEqual(a_flat.name, 'A')
# Aliases
self.assertEqual(
set(a_flat.aliases_map.keys()),
set([
'b_c1_C1', 'b_c1_C2', 'b_c1_C3', 'b_c1_C4', 'b_c2_C1',
'b_c2_C2', 'b_c2_C3', 'b_c2_C4', 'b_d_D1', 'b_d_D2', 'b_d_D3',
'c_C1', 'c_C2', 'c_C3', 'c_C4'
]))
# - Regimes and Transitions:
self.assertEqual(len(a_flat.regimes_map), 16)
r_c1_1_c2_1_d_1_c_1 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r1 b.c2:r1 c:r1')
r_c1_1_c2_2_d_1_c_1 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r1 b.c2:r2 c:r1')
r_c1_2_c2_1_d_1_c_1 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r2 b.c2:r1 c:r1')
r_c1_2_c2_2_d_1_c_1 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r2 b.c2:r2 c:r1')
r_c1_1_c2_1_d_2_c_1 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r1 b.c2:r1 c:r1')
r_c1_1_c2_2_d_2_c_1 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r1 b.c2:r2 c:r1')
r_c1_2_c2_1_d_2_c_1 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r2 b.c2:r1 c:r1')
r_c1_2_c2_2_d_2_c_1 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r2 b.c2:r2 c:r1')
r_c1_1_c2_1_d_1_c_2 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r1 b.c2:r1 c:r2')
r_c1_1_c2_2_d_1_c_2 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r1 b.c2:r2 c:r2')
r_c1_2_c2_1_d_1_c_2 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r2 b.c2:r1 c:r2')
r_c1_2_c2_2_d_1_c_2 = a_flat.flattener.get_new_regime(
'b.d:r1 b.c1:r2 b.c2:r2 c:r2')
r_c1_1_c2_1_d_2_c_2 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r1 b.c2:r1 c:r2')
r_c1_1_c2_2_d_2_c_2 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r1 b.c2:r2 c:r2')
r_c1_2_c2_1_d_2_c_2 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r2 b.c2:r1 c:r2')
r_c1_2_c2_2_d_2_c_2 = a_flat.flattener.get_new_regime(
'b.d:r2 b.c1:r2 b.c2:r2 c:r2')
regimes = [
r_c1_1_c2_1_d_1_c_1, r_c1_1_c2_2_d_1_c_1, r_c1_2_c2_1_d_1_c_1,
r_c1_2_c2_2_d_1_c_1, r_c1_1_c2_1_d_2_c_1, r_c1_1_c2_2_d_2_c_1,
r_c1_2_c2_1_d_2_c_1, r_c1_2_c2_2_d_2_c_1, r_c1_1_c2_1_d_1_c_2,
r_c1_1_c2_2_d_1_c_2, r_c1_2_c2_1_d_1_c_2, r_c1_2_c2_2_d_1_c_2,
r_c1_1_c2_1_d_2_c_2, r_c1_1_c2_2_d_2_c_2, r_c1_2_c2_1_d_2_c_2,
r_c1_2_c2_2_d_2_c_2
]
self.assertEqual(len(set(regimes)), 16)
# Do we have the right number of on_events and on_conditions:
self.assertEqual(len(list(r_c1_1_c2_1_d_1_c_1.on_events)), 4)
self.assertEqual(len(list(r_c1_1_c2_1_d_1_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_1_c2_2_d_1_c_1.on_events)), 3)
self.assertEqual(len(list(r_c1_1_c2_2_d_1_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_1_d_1_c_1.on_events)), 3)
self.assertEqual(len(list(r_c1_2_c2_1_d_1_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_2_d_1_c_1.on_events)), 2)
self.assertEqual(len(list(r_c1_2_c2_2_d_1_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_1_c2_1_d_2_c_1.on_events)), 3)
self.assertEqual(len(list(r_c1_1_c2_1_d_2_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_1_c2_2_d_2_c_1.on_events)), 2)
self.assertEqual(len(list(r_c1_1_c2_2_d_2_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_1_d_2_c_1.on_events)), 2)
self.assertEqual(len(list(r_c1_2_c2_1_d_2_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_2_d_2_c_1.on_events)), 1)
self.assertEqual(len(list(r_c1_2_c2_2_d_2_c_1.on_conditions)), 4)
self.assertEqual(len(list(r_c1_1_c2_1_d_1_c_2.on_events)), 3)
self.assertEqual(len(list(r_c1_1_c2_1_d_1_c_2.on_conditions)), 4)
self.assertEqual(len(list(r_c1_1_c2_2_d_1_c_2.on_events)), 2)
self.assertEqual(len(list(r_c1_1_c2_2_d_1_c_2.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_1_d_1_c_2.on_events)), 2)
self.assertEqual(len(list(r_c1_2_c2_1_d_1_c_2.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_2_d_1_c_2.on_events)), 1)
self.assertEqual(len(list(r_c1_2_c2_2_d_1_c_2.on_conditions)), 4)
self.assertEqual(len(list(r_c1_1_c2_1_d_2_c_2.on_events)), 2)
self.assertEqual(len(list(r_c1_1_c2_1_d_2_c_2.on_conditions)), 4)
self.assertEqual(len(list(r_c1_1_c2_2_d_2_c_2.on_events)), 1)
self.assertEqual(len(list(r_c1_1_c2_2_d_2_c_2.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_1_d_2_c_2.on_events)), 1)
self.assertEqual(len(list(r_c1_2_c2_1_d_2_c_2.on_conditions)), 4)
self.assertEqual(len(list(r_c1_2_c2_2_d_2_c_2.on_events)), 0)
self.assertEqual(len(list(r_c1_2_c2_2_d_2_c_2.on_conditions)), 4)
# All on_events return to thier same transition:
for r in a_flat.regimes:
for on_ev in r.on_events:
self.assertEquals(on_ev.target_regime, r)
# Check On-Event port names are remapped properly:
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_1_d_1_c_1.on_events]),
set(['c_spikein', 'b_c1_spikein', 'b_c2_spikein', 'b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_2_d_1_c_1.on_events]),
set(['c_spikein', 'b_c1_spikein', 'b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_1_d_1_c_1.on_events]),
set(['c_spikein', 'b_c2_spikein', 'b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_2_d_1_c_1.on_events]),
set(['c_spikein', 'b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_1_d_2_c_1.on_events]),
set(['c_spikein', 'b_c1_spikein', 'b_c2_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_2_d_2_c_1.on_events]),
set([
'c_spikein',
'b_c1_spikein',
]))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_1_d_2_c_1.on_events]),
set([
'c_spikein',
'b_c2_spikein',
]))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_2_d_2_c_1.on_events]),
set(['c_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_1_d_1_c_2.on_events]),
set(['b_c1_spikein', 'b_c2_spikein', 'b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_2_d_1_c_2.on_events]),
set(['b_c1_spikein', 'b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_1_d_1_c_2.on_events]),
set(['b_c2_spikein', 'b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_2_d_1_c_2.on_events]),
set(['b_d_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_1_d_2_c_2.on_events]),
set(['b_c1_spikein', 'b_c2_spikein']))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_1_c2_2_d_2_c_2.on_events]),
set([
'b_c1_spikein',
]))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_1_d_2_c_2.on_events]),
set([
'b_c2_spikein',
]))
self.assertEqual(
set([ev.src_port_name for ev in r_c1_2_c2_2_d_2_c_2.on_events]),
set([]))
# ToDo: Check the OnConditions:
# - Ports & Parameters:
self.assertEqual(
set(a_flat.query.analog_ports_map.keys()),
set([
'b_c1_C1', 'b_c1_C2', 'b_c2_C1', 'b_c2_C2', 'b_d_dIn2',
'b_d_D1', 'b_d_D2', 'c_cIn1', 'c_cIn2', 'c_C1', 'c_C2'
]))
self.assertEqual(
set(a_flat.query.event_ports_map.keys()),
set([
'b_c1_spikein',
'b_c1_emit',
'b_c1_c_emit',
'b_c2_spikein',
'b_c2_emit',
'b_c2_c_emit',
'b_d_spikein',
'b_d_emit',
'b_d_d_emit',
'c_spikein',
'c_emit',
'c_c_emit',
]))
self.assertEqual(
set(a_flat.query.parameters_map.keys()),
set([
'c_cp1',
'c_cp2',
'b_c1_cp1',
'b_c1_cp2',
'b_c2_cp1',
'b_c2_cp2',
'b_d_dp1',
'b_d_dp2',
]))
self.assertEqual(set(a_flat.state_variables_map.keys()),
set(['b_c1_SV1', 'b_c2_SV1', 'b_d_SV1', 'c_SV1']))
# Back-sub everything - then do we get the correct port mappings:
a_flat.backsub_all()
self.assertEqual(set(a_flat.aliases_map['b_c2_C4'].rhs_atoms),
set(['b_c1_cp1']))
self.assertEqual(set(a_flat.aliases_map['b_c1_C2'].rhs_atoms),
set(['b_c2_cp1']))
self.assertEqual(set(a_flat.aliases_map['b_c1_C4'].rhs_atoms),
set(['b_c1_cp1']))
self.assertEqual(set(a_flat.aliases_map['b_c2_C2'].rhs_atoms),
set(['b_c1_cp1']))
self.assertEqual(set(a_flat.aliases_map['b_d_D2'].rhs_atoms),
set(['b_c2_cp1', 'b_d_dp2']))
def get_compound_component():
"""Cannot yet be implemented in PyDSTool
"""
from nineml.abstraction_layer.testing_utils import RecordValue
from nineml.abstraction_layer import DynamicsClass, Regime, On, OutputEvent, AnalogSendPort, AnalogReducePort
emitter = DynamicsClass(
name='EventEmitter',
parameters=['cyclelength'],
regimes=[
Regime(transitions=On('t > tchange + cyclelength',
do=[OutputEvent('emit'), 'tchange=t'])),
])
ev_based_cc = DynamicsClass(
name='EventBasedCurrentClass',
parameters=['dur', 'i'],
analog_ports=[AnalogSendPort('I')],
regimes=[
Regime(transitions=[
On('inputevent', do=['I=i', 'tchange = t']),
On('t>tchange + dur', do=['I=0', 'tchange=t'])
])
])
pulsing_emitter = DynamicsClass(name='pulsing_cc',
subnodes={
'evs': emitter,
'cc': ev_based_cc
},
portconnections=[('evs.emit',
'cc.inputevent')])
nrn = DynamicsClass(
name='LeakyNeuron',
parameters=['Cm', 'gL', 'E'],
regimes=[
Regime('dV/dt = (iInj + (E-V)*gL )/Cm'),
],
aliases=['iIn := iInj'],
analog_ports=[
AnalogSendPort('V'),
AnalogReducePort('iInj', reduce_op='+')
],
)
combined_comp = DynamicsClass(name='Comp1',
subnodes={
'nrn': nrn,
'cc1': pulsing_emitter,
'cc2': pulsing_emitter
},
portconnections=[('cc1.cc.I', 'nrn.iInj'),
('cc2.cc.I', 'nrn.iInj')])
combined_comp = al.flattening.flatten(combined_comp)
## records = [
## RecordValue(what='cc1_cc_I', tag='Current', label='Current Clamp 1'),
## RecordValue(what='cc2_cc_I', tag='Current', label='Current Clamp 2'),
## RecordValue(what='nrn_iIn', tag='Current', label='Total Input Current'),
## RecordValue(what='nrn_V', tag='Voltage', label='Neuron Voltage'),
## RecordValue(what='cc1_cc_tchange', tag='Tchange', label='tChange CC1'),
## RecordValue(what='cc2_cc_tchange', tag='Tchange', label='tChange CC2'),
## RecordValue(what='regime', tag='Regime', label='Regime'),
## ]
parameters = al.flattening.ComponentFlattener.flatten_namespace_dict({
'cc1.cc.i':
13.8,
'cc1.cc.dur':
10,
'cc1.evs.cyclelength':
30,
'cc2.cc.i':
20.8,
'cc2.cc.dur':
5.0,
'cc2.evs.cyclelength':
20,
'nrn.gL':
4.3,
'nrn.E':
-70
})
return combined_comp, parameters