class OvioCorePlatform(LatticeECP5Platform):
device = "LFE5U-85F"
package = "BG381"
speed = 8
resources = [
# This clock can only be an input to the PLL
Resource(
"pll_clk25",
0,
Pins("U16", dir="i"), # Input to LRC_GPLLOT
Clock(25e6),
Attrs(IO_TYPE="LVCMOS33")),
*LEDResources(pins="B17 C17 A17 B18",
invert=False,
attrs=Attrs(IO_TYPE="LVCMOS33")),
Resource(
"ft600",
0,
Subsignal("clk", Pins("J19", dir="i"), Clock(100e6),
Attrs(IO_TYPE="LVCMOS33")),
Subsignal(
"data",
Pins(
"C20 C18 D20 D19 E20 E19 F20 F19 G20 G19 H20 J17 J16 H16 H18 G18",
dir="io"), Attrs(IO_TYPE="LVCMOS33", DRIVE="16")),
Subsignal("be", Pins("H17 G16", dir="io"),
Attrs(IO_TYPE="LVCMOS33", DRIVE="16")),
Subsignal("read", PinsN("E18", dir="o"),
Attrs(IO_TYPE="LVCMOS33", DRIVE="16")),
Subsignal("write", PinsN("F17", dir="o"),
Attrs(IO_TYPE="LVCMOS33", DRIVE="16")),
Subsignal("oe", PinsN("E17", dir="o"),
Attrs(IO_TYPE="LVCMOS33", DRIVE="16")),
Subsignal("txe", PinsN("F16", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
Subsignal("rxf", PinsN("F18", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
Subsignal("reset", PinsN("D18", dir="o"),
Attrs(IO_TYPE="LVCMOS33")),
Subsignal("gpio0", Pins("D17", dir="i"),
Attrs(IO_TYPE="LVCMOS33")),
Subsignal("gpio1", Pins("E16", dir="i"),
Attrs(IO_TYPE="LVCMOS33")),
),
# The board has pseudo power pins, connect these with a constant `1`
Resource(
"pseudo_power",
0,
Subsignal("ft", Pins("J18", dir="o"),
Attrs(IO_TYPE="LVCMOS33", DRIVE="16")),
Subsignal("ddr", Pins("J5 M5 L3 N1 A3 D3 D2 H3", dir="o"),
Attrs(IO_TYPE="LVCMOS15")),
),
]
connectors = []
def toolchain_program(self, products, name):
raise NotImplementedError("Not implemented")
class ICE40HX8KBEVNPlatform(LatticeICE40Platform):
device = "iCE40HX8K"
package = "CT256"
# Resets should be on GBIN0/2/4/6. Clocks may be on any GBIN.
resources: List[Resource] = [
Resource(
"clk1",
0,
Pins("J3", dir="i"),
Clock(12e6),
Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS"),
), # GBIN6
Resource(
"clk2",
0,
Pins("G1", dir="i"),
Clock(12e6),
Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS"),
), # GBIN7
Resource("rst", 0, Pins("K9", dir="i"),
Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS")), # GBIN4
*Bus(
default_name="addr",
pins="B1 B2 C1 C2 D1 D2 E2 F1 F2 G2 H1 H2 J2 J1 K3 K1",
dir="oe",
attrs=Attrs(IO_STANDARD="SB_LVCMOS"),
),
*Bus(
default_name="data",
pins="M3 L5 N3 P1 M4 P2 M5 R1",
dir="io",
attrs=Attrs(IO_STANDARD="SB_LVCMOS"),
),
*Bus(
default_name="led",
pins="C3 B3 C4 C5 A1 A2 B4 B5",
dir="o",
attrs=Attrs(IO_STANDARD="SB_LVCMOS"),
),
Resource("ba", 0, Pins("M1", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("rw", 0, Pins("E4", dir="oe"),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("n_irq", 0, Pins("L3", dir="i"),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("n_nmi", 0, Pins("L1", dir="i"),
Attrs(IO_STANDARD="SB_LVCMOS")),
]
default_clk = "clk1"
default_rst = "rst"
connectors: List[Connector] = []
def toolchain_program(self, products, name):
iceprog = os.environ.get("ICEPROG", "iceprog")
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.check_call([iceprog, "-S", bitstream_filename])
class SensorPlatform(LatticeICE40Platform):
device = "iCE40HX8K"
package = "BG121"
resources = [
Resource("clk25", 0, Pins("B6", dir="i"), Clock(25e6)),
Resource("user_led", 0, Pins("A10", dir="o")),
Resource("user_led", 1, Pins("A11", dir="o")),
Resource("user_sw", 0, Pins("L1", dir="i")),
Resource("user_sw", 1, Pins("L7", dir="i")),
Resource(
"adc",
0,
Subsignal("cs", Pins("L2", dir="o")),
Subsignal("dout", Pins("L3", dir="o")),
Subsignal("sclk", Pins("L4", dir="o")),
),
Resource(
"daqnet",
0,
Subsignal("led1", Pins("A3", dir="o")),
Subsignal("led2", Pins("A4", dir="o")),
Subsignal("txp", Pins("C2", dir="o")),
Subsignal("txn", Pins("C1", dir="o")),
Subsignal("rx", Pins("B2", dir="i")),
),
]
connectors = []
def output_domain(self, domain_name, divisor, number=None, bufg=True):
if number is None:
number = next(x for x in range(6)
if x not in self._clock_constraints.keys())
assert number not in self._clock_constraints.keys(
), "port {} is already taken".format(number)
assert divisor in Mmcm.output_dividers
self._pll.parameters["CLKOUT{}_DIVIDE".format(number)] = divisor
self._pll.parameters["CLKOUT{}_PHASE".format(number)] = 0.0
m = self.m
clock_signal = Signal(name="pll_out_{}".format(number),
attrs={"KEEP": "TRUE"})
m.d.comb += clock_signal.eq(self._pll.clk.out[number])
if bufg:
# TODO: seems to not change anything
bufg = m.submodules["bufg_{}".format(number)] = Bufg(clock_signal)
output = bufg.o
else:
output = clock_signal
m.domains += ClockDomain(domain_name)
m.d.comb += ClockSignal(domain_name).eq(output)
m.d.comb += ResetSignal(domain_name).eq(~self.locked)
frequency = self._vco.frequency / divisor
self._clock_constraints[number] = (clock_signal, frequency)
return Clock(frequency)
def fck_domain(self,
requested_frequency=100e6,
domain_name="sync",
max_error_percent=1) -> Clock:
"""
Creates a clockdomain driven by a PS7 fclk
:param max_error_percent:
:param domain_name: teh name of the domain to create
:param requested_frequency: the requested frequency
:return: the real freqency that will be generated by the fclk
"""
self.m.domains += ClockDomain(domain_name)
fclk_num = len(self.clock_constraints)
driving_signal = Signal(attrs={"KEEP": "TRUE"},
name="{}_driving_signal".format(domain_name))
self.m.d.comb += driving_signal.eq(self.instance.fclk.clk[fclk_num])
bufg = self.m.submodules["fclk_bufg_{}".format(fclk_num)] = Bufg(
driving_signal)
real_freq = [
x for x in self.get_possible_fclk_frequencies()
if x <= requested_frequency
][-1]
max_error_freq(real_freq, requested_frequency, max_error_percent)
self.clock_constraints[fclk_num] = (driving_signal, bufg.o, real_freq,
domain_name)
return Clock(real_freq)
class Ulx3sPlatform(ULX3S_85F_Platform):
resources: List[Resource] = [
Resource("clk25", 0, Pins("G2", dir="i"), Clock(25e6),
Attrs(IO_TYPE="LVCMOS33")),
Resource("rst", 0, Pins("D6", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
*Bus(
default_name="addr",
pins="B11 C11 A10 A11 A9 B10 B9 C10 A7 A8 C8 B8 C6 C7 A6 B6",
dir="oe",
attrs=Attrs(IO_TYPE="LVCMOS33"),
),
*Bus(
default_name="data",
pins="A4 A5 A2 B1 C4 B4 F4 E3",
dir="io",
attrs=Attrs(IO_TYPE="LVCMOS33"),
),
*Bus(
default_name="led",
pins="H3 E1 E2 D1 D2 C1 C2 B2",
dir="o",
attrs=Attrs(IO_TYPE="LVCMOS33"),
),
Resource("ba", 0, Pins("G3", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("rw", 0, Pins("F3", dir="oe"), Attrs(IO_TYPE="LVCMOS33")),
Resource("n_irq", 0, Pins("H4", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
Resource("n_nmi", 0, Pins("G5", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
]
default_rst = "rst"
class FomuEVTPlatform(LatticeICE40Platform, LUNAPlatform):
""" Platform for the Fomu EVT platforms. """
default_clk = "clk48"
name = "Fomu EVT"
# Provide the type that'll be used to create our clock domains.
clock_domain_generator = FomuDomainGenerator
# We only have a direct connection on our USB lines, so use that for USB comms.
default_usb_connection = "usb"
device = "iCE40UP5K"
package = "SG48"
default_clk = "clk48"
resources = [
Resource("clk48", 0, Pins("44", dir="i"), Clock(48e6),
Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS")),
Resource("led", 0, PinsN("41"), Attrs(IO_STANDARD="SB_LVCMOS")),
Resource(
"rgb_led",
0,
Subsignal("r", PinsN("40"), Attrs(IO_STANDARD="SB_LVCMOS")),
Subsignal("g", PinsN("39"), Attrs(IO_STANDARD="SB_LVCMOS")),
Subsignal("b", PinsN("41"), Attrs(IO_STANDARD="SB_LVCMOS")),
),
Resource(
"usb",
0,
Subsignal("d_p", Pins("34")),
Subsignal("d_n", Pins("37")),
Subsignal("pullup", Pins("35", dir="o")),
Attrs(IO_STANDARD="SB_LVCMOS"),
),
# PMOD
Resource("user_io", 0, PinsN("25"), Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("user_io", 1, PinsN("26"), Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("user_io", 2, PinsN("27"), Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("user_io", 3, PinsN("28"), Attrs(IO_STANDARD="SB_LVCMOS")),
]
connectors = []
def toolchain_program(self, products, name):
""" Program the FPGA of an Fomu EVT board. """
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.check_call(["fomu-flash", "-f", bitstream_filename])
def toolchain_flash(self, products, name="top"):
""" Flash the SPI flash of an Fomu EVT board. """
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.check_call(["fomu-flash", "-w", bitstream_filename])
def __init__(self, resource, modeline, pix_domain="pix", generate_clocks=True):
self.resource = resource
self.pix_domain = pix_domain
self.generate_clocks = generate_clocks
self.initial_video_timing = parse_modeline(modeline)
self.pix_freq = Clock(self.initial_video_timing.pxclk * 1e6)
self.rgb = RGB24()
self.hsync_polarity = ControlSignal()
self.vsync_polarity = ControlSignal()
self.clock_pattern = ControlSignal(10, name="hdmi_clock_pattern", reset=0b1111100000)
self.timing_generator = HdmiTimingGenerator(self.initial_video_timing)
def __init__(self, plugin, modeline, generate_clocks=True):
self.plugin = plugin
self.generate_clocks = generate_clocks
video_timing = parse_modeline(modeline)
self.pix_freq = Clock(video_timing.pxclk * 1e6)
self.rgb = Rgb()
self.hsync_polarity = ControlSignal()
self.vsync_polarity = ControlSignal()
self.clock_pattern = ControlSignal(10,
name="hdmi_clock_pattern",
reset=0b1111100000)
self.timing_generator = TimingGenerator(video_timing)
class FomuHackerPlatform(LatticeICE40Platform, LUNAPlatform):
""" Base class for Fomu platforms. """
default_clk = "clk48"
name = "Fomu Hacker"
# Provide the type that'll be used to create our clock domains.
clock_domain_generator = FomuDomainGenerator
# We only have a direct connection on our USB lines, so use that for USB comms.
default_usb_connection = "usb"
device = "iCE40UP5K"
package = "UWG30"
default_clk = "clk48"
resources = [
Resource("clk48", 0, Pins("F5", dir="i"), Clock(48e6),
Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS")),
Resource("led", 0, PinsN("C5"), Attrs(IO_STANDARD="SB_LVCMOS")),
Resource(
"rgb_led",
0,
Subsignal("r", PinsN("C5"), Attrs(IO_STANDARD="SB_LVCMOS")),
Subsignal("g", PinsN("B5"), Attrs(IO_STANDARD="SB_LVCMOS")),
Subsignal("b", PinsN("A5"), Attrs(IO_STANDARD="SB_LVCMOS")),
),
Resource(
"usb",
0,
Subsignal("d_p", Pins("A4")),
Subsignal("d_n", Pins("A2")),
Subsignal("pullup", Pins("D5", dir="o")),
Attrs(IO_STANDARD="SB_LVCMOS"),
),
]
connectors = []
def toolchain_program(self, products, name):
""" Program the flash of a FomuHacker board. """
# Use the DFU bootloader to program the ECP5 bitstream.
dfu_util = os.environ.get("DFU_UTIL", "dfu-util")
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.check_call(
[dfu_util, "-d", "1209:5bf0", "-D", bitstream_filename])
def ULPIResource(name,
data_sites,
clk_site,
dir_site,
nxt_site,
stp_site,
reset_site,
extras=()):
""" Generates a set of resources for a ULPI-connected USB PHY. """
return Resource(
name, 0, Subsignal("data", Pins(data_sites, dir="io")),
Subsignal("clk", Pins(clk_site, dir="i"), Attrs(PULLDOWN="TRUE"),
Clock(60e6)), Subsignal("dir", Pins(dir_site, dir="i")),
Subsignal("nxt", Pins(nxt_site, dir="i")),
Subsignal("stp", Pins(stp_site, dir="o")),
Subsignal("rst", PinsN(reset_site, dir="o")), Attrs(SLEW="FAST"))
def __init__(self, input_freq, vco_mul, vco_div, input_domain="sync"):
Pll.is_valid_vco_conf(input_freq, vco_mul, vco_div, exception=True)
self._pll = RawPll(
clkin1_period=1 / input_freq * 1e9,
clkfbout_mult=vco_mul,
divclk_divide=vco_div,
)
m = self.m = Module()
m.d.comb += self._pll.clk.fbin.eq(self._pll.clk.fbout)
m.d.comb += self._pll.clk.in_[1].eq(ClockSignal(input_domain))
m.d.comb += self._pll.clk.insel.eq(1) # HIGH for clkin1
self.locked = StatusSignal()
self._input_domain = input_domain
self._input_freq = input_freq
self._vco = Clock(input_freq * vco_mul / vco_div)
self._clock_constraints = {}
def __init__(self, input_clock, vco_mul, vco_div, input_domain="sync"):
Mmcm.is_valid_vco_conf(input_clock, vco_mul, vco_div, exception=True)
self._mmcm = InstanceHelper("+/xilinx/cells_xtra.v", "MMCME2_ADV")(
clkin1_period=1 / input_clock * 1e9,
clkfbout_mult_f=vco_mul,
divclk_divide=vco_div,
)
m = self.m = Module()
m.d.comb += self._mmcm.clk.fbin.eq(self._mmcm.clk.fbout)
m.d.comb += self._mmcm.clk.in_[1].eq(ClockSignal(input_domain))
m.d.comb += self._mmcm.clk.ins.el.eq(1) # HIGH for clkin1
self.locked = StatusSignal()
self._input_domain = input_domain
self._input_clock = input_clock
self._vco = Clock(input_clock * vco_mul / vco_div)
self._clock_constraints = {}
def ULPIResource(name,
data_sites,
clk_site,
dir_site,
nxt_site,
stp_site,
reset_site,
extras=(),
attrs=None):
""" Generates a set of resources for a ULPI-connected USB PHY. """
attrs = Attrs() if attrs is None else attrs
return Resource(name, 0, Subsignal("data", Pins(data_sites, dir="io")),
Subsignal("clk", Pins(clk_site, dir="i"), Clock(60e6)),
Subsignal("dir", Pins(dir_site, dir="i")),
Subsignal("nxt", Pins(nxt_site, dir="i")),
Subsignal("stp", Pins(stp_site, dir="o")),
Subsignal("rst", Pins(reset_site, dir="o")), attrs)
class TinyFPGABxPlatform(LatticeICE40Platform, LUNAPlatform):
device = "iCE40LP8K"
package = "CM81"
default_clk = "clk16"
name = "TinyFPGA Bx"
# Provide the type that'll be used to create our clock domains.
clock_domain_generator = TinyFPGABxDomainGenerator
# We only have a direct connection on our USB lines, so use that for USB comms.
default_usb_connection = "usb"
resources = [
Resource("clk16", 0, Pins("B2", dir="i"), Clock(16e6),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("led", 0, Pins("B3"), Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("usb", 0, Subsignal("d_p", Pins("B4", dir="io")),
Subsignal("d_n", Pins("A4", dir="io")),
Subsignal("pullup", Pins("A3", dir="o")),
Attrs(IO_STANDARD="SB_LVCMOS")),
]
connectors = [
Connector(
"gpio",
0,
# Left side of the board
# 1 2 3 4 5 6 7 8 9 10 11 12 13
" A2 A1 B1 C2 C1 D2 D1 E2 E1 G2 H1 J1 H2 "
# Right side of the board
# 14 15 16 17 18 19 20 21 22 23 24
" H9 D9 D8 C9 A9 B8 A8 B7 A7 B6 A6 "
# Bottom of the board
# 25 26 27 28 29 30 31
"G1 J3 J4 G9 J9 E8 J2"),
]
def toolchain_program(self, products, name):
tinyprog = os.environ.get("TINYPROG", "tinyprog")
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.check_call([tinyprog, "-p", bitstream_filename])
def output_domain(self, domain_name, divisor, number=None, bufg=True):
if number is None:
number = next(x for x in range(7)
if x not in self._clock_constraints.keys())
assert number not in self._clock_constraints.keys(
), "port {} is already taken".format(number)
assert divisor in (Mmcm.output_dividers
if number != 0 else Mmcm.output_0_dividers)
divide_param = "CLKOUT{}_DIVIDE{}".format(number,
"_f" if number == 0 else "")
self._mmcm.parameters[divide_param] = divisor
self._mmcm.parameters["CLKOUT{}_PHASE".format(number)] = 0.0
m = self.m
clock_signal = Signal(name="mmcm_out_{}".format(number),
attrs={"KEEP": "TRUE"})
m.d.comb += clock_signal.eq(self._mmcm.clk.out[number])
if bufg:
# TODO: seems to not change anything
bufg = m.submodules["bufg_{}".format(number)] = BufG(clock_signal)
output = bufg.o
else:
output = clock_signal
m.domains += ClockDomain(domain_name)
m.d.comb += ClockSignal(domain_name).eq(output)
m.d.comb += ResetSignal(domain_name).eq(~self.locked)
frequency = self._vco.frequency / divisor
self._clock_constraints[number] = (clock_signal, frequency)
print("MMCM: creating domain '{}' with frequency {}Mhz".format(
domain_name, frequency / 1e6))
return Clock(frequency)
class IceBreakerPlatform(LatticeICE40Platform, LUNAPlatform):
""" Base class for Fomu platforms. """
device = "iCE40UP5K"
package = "SG48"
name = "iCEBreaker"
# Provide the type that'll be used to create our clock domains.
clock_domain_generator = IceBreakerDomainGenerator
# We only have a direct connection on our USB lines, so use that for USB comms.
default_usb_connection = "tnt_usb"
default_clk = "clk12"
resources = [
Resource("clk12", 0, Pins("35", dir="i"), Clock(12e6),
Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS")),
Resource("led", 0, PinsN("11", dir="o"),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("led", 1, PinsN("37", dir="o"),
Attrs(IO_STANDARD="SB_LVCMOS")),
# Semantic aliases
Resource("led_r", 0, PinsN("11", dir="o"),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("led_g", 0, PinsN("37", dir="o"),
Attrs(IO_STANDARD="SB_LVCMOS")),
# Default USB position.
Resource(
"tnt_usb",
0,
Subsignal("d_p", Pins("31")),
Subsignal("d_n", Pins("34")),
Subsignal("pullup", Pins("38", dir="o")),
Attrs(IO_STANDARD="SB_LVCMOS"),
),
Resource(
"kbeckmann_usb",
0,
Subsignal("d_p", Pins("43")),
Subsignal("d_n", Pins("38")),
Subsignal("pullup", Pins("34", dir="o")),
Attrs(IO_STANDARD="SB_LVCMOS"),
),
# Compatibility aliases.
Resource("user_io", 0, PinsN("4", dir="io"),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("user_io", 1, PinsN("2", dir="io"),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("user_io", 2, PinsN("47", dir="io"),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("user_io", 3, PinsN("25", dir="io"),
Attrs(IO_STANDARD="SB_LVCMOS")),
]
connectors = [
Connector("pmod", 0, " 4 2 47 45 - - 3 48 46 44 - -"), # PMOD1A
Connector("pmod", 1, "43 38 34 31 - - 42 36 32 28 - -"), # PMOD1B
Connector("pmod", 2, "27 25 21 19 - - 26 23 20 18 - -"), # PMOD2
]
def __init__(self, *args, **kwargs):
logging.warning(
"This platform is not officially supported, and thus not tested. Your results may vary."
)
logging.warning(
"Note also that this platform does not use the iCEBreaker's main USB port!"
)
logging.warning(
"You'll need to connect a cable or pmod. See the platform file for more info."
)
super().__init__(*args, **kwargs)
def toolchain_program(self, products, name):
iceprog = os.environ.get("ICEPROG", "iceprog")
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.check_call([iceprog, bitstream_filename])
def toolchain_flash(self, products, name="top"):
self.toolchain_program(products, name)
class ECPIX5PlatformRev02(LatticeECP5Platform, LUNAPlatform):
name = "ECPIX-5 R02"
device = "LFE5UM5G-85F"
package = "BG554"
speed = "8"
default_clk = "clk100"
default_rst = "rst"
# Provide the type that'll be used to create our clock domains.
clock_domain_generator = StubClockDomainGenerator
# We only have a single PHY; so use it directly.
default_usb_connection = "ulpi"
resources = [
Resource("rst", 0, PinsN("AB1", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
Resource("clk100", 0, Pins("K23", dir="i"), Clock(100e6),
Attrs(IO_TYPE="LVCMOS33")),
# LEDs
Resource(
"rgb_led",
0,
Subsignal("r", Pins("U21")),
Subsignal("g", Pins("W21")),
Subsignal("b", Pins("T24")),
Attrs(IO_TYPE="LVCMOS33"),
),
Resource(
"rgb_led",
1,
Subsignal("r", Pins("T23")),
Subsignal("g", Pins("R21")),
Subsignal("b", Pins("T22")),
Attrs(IO_TYPE="LVCMOS33"),
),
Resource(
"rgb_led",
2,
Subsignal("r", Pins("P21")),
Subsignal("g", Pins("R23")),
Subsignal("b", Pins("P22")),
Attrs(IO_TYPE="LVCMOS33"),
),
Resource(
"rgb_led",
3,
Subsignal("r", Pins("K21")),
Subsignal("g", Pins("K24")),
Subsignal("b", Pins("M21")),
Attrs(IO_TYPE="LVCMOS33"),
),
Resource("uart", 0, Subsignal("rx", Pins("R26", dir="i")),
Subsignal("tx", Pins("R24", dir="o")),
Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP")),
Resource("eth_rgmii", 0, Subsignal("rst", PinsN("C13", dir="o")),
Subsignal("mdio", Pins("A13", dir="io")),
Subsignal("mdc", Pins("C11", dir="o")),
Subsignal("tx_clk", Pins("A12", dir="o")),
Subsignal("tx_ctrl", Pins("C9", dir="o")),
Subsignal("tx_data", Pins("D8 C8 B8 A8", dir="o")),
Subsignal("rx_clk", Pins("E11", dir="i")),
Subsignal("rx_ctrl", Pins("A11", dir="i")),
Subsignal("rx_data", Pins("B11 A10 B10 A9", dir="i")),
Attrs(IO_TYPE="LVCMOS33")),
Resource("eth_int", 0, PinsN("B13", dir="i"),
Attrs(IO_TYPE="LVCMOS33")),
Resource(
"ddr3", 0,
Subsignal("clk", DiffPairs("H3", "J3", dir="o"),
Attrs(IO_TYPE="SSTL135D_I")),
Subsignal("clk_en", Pins("P1", dir="o")),
Subsignal("we", PinsN("R3", dir="o")),
Subsignal("ras", PinsN("T3", dir="o")),
Subsignal("cas", PinsN("P2", dir="o")),
Subsignal(
"a",
Pins("T5 M3 L3 V6 K2 W6 K3 L1 H2 L2 N1 J1 M1 K1", dir="o")),
Subsignal("ba", Pins("U6 N3 N4", dir="o")),
Subsignal("dqs", DiffPairs("V4 V1", "U5 U2", dir="io"),
Attrs(IO_TYPE="SSTL135D_I")),
Subsignal(
"dq",
Pins("T4 W4 R4 W5 R6 P6 P5 P4 R1 W3 T2 V3 U3 W1 T1 W2",
dir="io")), Subsignal("dm", Pins("J4 H5", dir="o")),
Subsignal("odt", Pins("L2", dir="o")), Attrs(IO_TYPE="SSTL135_I")),
Resource(
"hdmi", 0, Subsignal("rst", PinsN("N6", dir="o")),
Subsignal("scl", Pins("C17", dir="io")),
Subsignal("sda", Pins("E17", dir="io")),
Subsignal("pclk", Pins("C1", dir="o")),
Subsignal("vsync", Pins("A4", dir="o")),
Subsignal("hsync", Pins("B4", dir="o")),
Subsignal("de", Pins("A3", dir="o")),
Subsignal(
"d",
Subsignal(
"b",
Pins("AD25 AC26 AB24 AB25 B3 C3 D3 B1 C2 D2 D1 E3",
dir="o")),
Subsignal(
"g",
Pins("AA23 AA22 AA24 AA25 E1 F2 F1 D17 D16 E16 J6 H6",
dir="o")),
Subsignal(
"r",
Pins("AD26 AE25 AF25 AE26 E10 D11 D10 C10 D9 E8 H5 J4",
dir="o")),
), Subsignal("mclk", Pins("E19", dir="o")),
Subsignal("sck", Pins("D6", dir="o")),
Subsignal("ws", Pins("C6", dir="o")),
Subsignal("i2s", Pins("A6 B6 A5 C5", dir="o")),
Subsignal("int", PinsN("C4", dir="i")), Attrs(IO_TYPE="LVTTL33")),
Resource("sata", 0, Subsignal("tx", DiffPairs("AD16", "AD17",
dir="o")),
Subsignal("rx", DiffPairs("AF15", "AF16", dir="i")),
Attrs(IO_TYPE="LVDS")),
ULPIResource("ulpi",
data_sites="M26 L25 L26 K25 K26 J23 P25 H25",
clk_site="H24",
dir_site="F22",
stp_site="H23",
nxt_site="F23",
reset_site="E23",
attrs=Attrs(IO_TYPE="LVCMOS33")),
Resource("usbc_cfg", 0, Subsignal("scl", Pins("D24", dir="io")),
Subsignal("sda", Pins("C24", dir="io")),
Subsignal("dir", Pins("B23", dir="i")),
Subsignal("id", Pins("D23", dir="i")),
Subsignal("int", PinsN("B24", dir="i")),
Attrs(IO_TYPE="LVCMOS33")),
Resource(
"usbc_mux",
0,
Subsignal("en", Pins("C23", dir="oe")),
Subsignal("amsel", Pins("B26", dir="oe")),
Subsignal("pol", Pins("D26", dir="o")),
#Subsignal("lna", DiffPairs( "AF9", "AF10", dir="i"), Attrs(IO_TYPE="LVCMOS18D")),
#Subsignal("lnb", DiffPairs("AD10", "AD11", dir="o"), Attrs(IO_TYPE="LVCMOS18D")),
#Subsignal("lnc", DiffPairs( "AD7", "AD8", dir="o"), Attrs(IO_TYPE="LVCMOS18D")),
#Subsignal("lnd", DiffPairs( "AF6", "AF7", dir="i"), Attrs(IO_TYPE="LVCMOS18D")),
Attrs(IO_TYPE="LVCMOS33")),
# Compatibility aliases.
Resource("led", 0, Pins("W21", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 1, Pins("R21", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 2, Pins("R23", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 3, Pins("K24", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("user_io", 0, Pins("T25")),
Resource("user_io", 1, Pins("U25")),
Resource("user_io", 2, Pins("U24")),
Resource("user_io", 3, Pins("V24")),
]
connectors = [
Connector("pmod", 0, "T25 U25 U24 V24 - - T26 U26 V26 W26 - -"),
Connector("pmod", 1, "U23 V23 U22 V21 - - W25 W24 W23 W22 - -"),
Connector("pmod", 2, "J24 H22 E21 D18 - - K22 J21 H21 D22 - -"),
Connector("pmod", 3, " E4 F4 E6 H4 - - F3 D4 D5 F5 - -"),
Connector("pmod", 4, "E26 D25 F26 F25 - - A25 A24 C26 C25 - -"),
Connector("pmod", 5, "D19 C21 B21 C22 - - D21 A21 A22 A23 - -"),
Connector("pmod", 6, "C16 B17 C18 B19 - - A17 A18 A19 C19 - -"),
Connector("pmod", 7, "D14 B14 E14 B16 - - C14 A14 A15 A16 - -"),
]
@property
def file_templates(self):
return {
**super().file_templates, "{{name}}-openocd.cfg":
r"""
interface ftdi
ftdi_vid_pid 0x0403 0x6010
ftdi_channel 0
ftdi_layout_init 0xfff8 0xfffb
reset_config none
adapter_khz 25000
jtag newtap ecp5 tap -irlen 8 -expected-id 0x81113043
"""
}
def toolchain_program(self, products, name):
openocd = os.environ.get("OPENOCD", "openocd")
with products.extract("{}-openocd.cfg".format(name), "{}.svf".format(name)) \
as (config_filename, vector_filename):
subprocess.check_call([
openocd, "-f", config_filename, "-c",
"transport select jtag; init; svf -quiet {}; exit".format(
vector_filename)
])
class Firestarter(LatticeICE40Platform):
'''Kicad board available at
https://github.com/hstarmans/firestarter/tree/master/pi_hat
'''
name = "firestarter"
ic_dev_nr = 1 # spi connection
ic_address = 0x28 # spi address
enable_pin = 17 # enable pin for stepper motors
reset_pin = 26 # can be used to reset FPGA
stepspermm = {'x': 76.2, 'y': 76.2, 'z': 1600}
laser_axis = 'y'
laser_var = {
'RPM': 2000,
'SPINUP_TIME': 1.5,
'STABLE_TIME': 1.125,
'FACETS': 4,
'CRYSTAL_HZ': 50E6,
'LASER_HZ': 100E3,
'END%': 0.7,
'START%': 0.35,
'SINGLE_LINE': False,
'SINGLE_FACET': False,
'DIRECTION': 0
}
motors = len(stepspermm.keys())
memdepth = 256
device = 'iCE40HX4K'
package = 'TQ144'
default_clk = 'clk100_mhz'
clock_domain_generator = FirestarterDomainGenerator
resources = [
Resource("clk100_mhz", 0, Pins("61", dir="i"), Clock(100e6),
Attrs(IO_STANDARD="SB_LVCMOS")),
*LEDResources(pins='8 3', attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
# NOTE: there is a proper resource in nmigen_boards
# this is used as it is also done by luna
Resource("debug_spi", 0, Subsignal("sck", Pins("79", dir="i")),
Subsignal("sdi", Pins("90", dir="i")),
Subsignal("sdo", Pins("87", dir="o")),
Subsignal("cs", PinsN("85", dir="i")),
Attrs(IO_STANDARD="SB_LVCMOS")),
# Laserscanner resource
LaserscannerResource(number=0,
laser0='134',
laser1='135',
photodiode='137',
pwm='139',
enable='141',
attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
# x-stepper
StepperResource(number=0,
step="38",
direction="37",
limit="110",
attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
# y-stepper
StepperResource(number=1,
step="19",
direction="18",
limit="124",
attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
# z-stepper
StepperResource(number=2,
step="143",
direction="142",
limit="130",
attrs=Attrs(IO_STANDARD="SB_LVCMOS"))
]
connectors = []
def toolchain_program(self, products, name, **kwargs):
icezprog = os.environ.get("ICEZPROG", "icezprog")
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.check_call([icezprog, bitstream_filename])
class DaishoPlatform(IntelPlatform):
""" Board description for Daisho boards."""
name = "Daisho"
device = "EEP4CE30F29C8"
default_clk = "clk_60MHz"
#
# Default clock frequencies for each of our clock domains.
#
# Different revisions have different FPGA speed grades, and thus the
# default frequencies will vary.
#
DEFAULT_CLOCK_FREQUENCIES_MHZ = {
"fast": 120,
"sync": 60,
"ulpi": 60
}
#
# Preferred DRAM bus I/O (de)-skewing constants.
#
ram_timings = dict(
clock_skew = 64
)
# Provides any platform-specific ULPI registers necessary.
# This is the spot to put any platform-specific vendor registers that need
# to be written.
ulpi_extra_registers = {
0x39: 0b000110 # USB3343: swap D+ and D- to match the LUNA boards
}
#
# I/O resources.
#
resources = [
# Primary, discrete 60MHz oscillator.
Resource("clk_60MHz", 0, Pins("A8", dir="i"),
Clock(60e6), Attrs(IO_TYPE="LVCMOS33")),
# Connection to our SPI flash; can be used to work with the flash
# from e.g. a bootloader.
Resource("spi_flash", 0,
# SCK is on pin 9; but doesn't have a traditional I/O buffer.
# Instead, we'll need to drive a clock into a USRMCLK instance.
# See interfaces/flash.py for more information.
Subsignal("sdi", Pins("T8", dir="o")),
Subsignal("sdo", Pins("T7", dir="i")),
# In r0.1, the chip select line can either be driven by the FPGA
# or by the Debug Controller. Accordingly, we'll mark the line as
# bidirectional, and let the user decide.
Subsignal("cs", PinsN("N8", dir="io")),
Attrs(IO_TYPE="LVCMOS33")
),
#
# Note: r0.1 has a DFM issue that makes it difficult to solder a BGA with
# reliable connections on the intended SCK pin (P12), and lacks a CS pin on the
# debug SPI; which seems like a silly omission.
#
# Accordingly, we're mapping the debug SPI and UART over the same pins, as the
# microcontroller can use either.
#
# UART connected to the debug controller; can be routed to a host via CDC-ACM.
Resource("uart", 0,
Subsignal("rx", Pins("R14", dir="i")),
Subsignal("tx", Pins("T14", dir="o")),
Attrs(IO_TYPE="LVCMOS33")
),
# SPI bus connected to the debug controller, for simple register exchanges.
# Note that the Debug Controller is the master on this bus.
Resource("debug_spi", 0,
Subsignal("sck", Pins( "R14", dir="i")),
Subsignal("sdi", Pins( "P13", dir="i")),
Subsignal("sdo", Pins( "P11", dir="o")),
Subsignal("cs", PinsN("T14", dir="i")),
Attrs(IO_TYPE="LVCMOS33")
),
# FPGA-connected LEDs.
Resource("led", 5, PinsN("P15", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 4, PinsN("N16", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 3, PinsN("M15", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 2, PinsN("M16", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 1, PinsN("L15", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 0, PinsN("L16", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
# USB PHYs
ULPIResource("sideband_phy",
data_sites="R2 R1 P2 P1 N1 M2 M1 L2", clk_site="R4",
dir_site="T3", nxt_site="T2", stp_site="T4", reset_site="R3"),
ULPIResource("host_phy",
data_sites="G2 G1 F2 F1 E1 D1 C1 B1", clk_site="K2",
dir_site="J1", nxt_site="H2", stp_site="J2", reset_site="K1"),
ULPIResource("target_phy",
data_sites="D16 E15 E16 F15 F16 G15 J16 K16", clk_site="B15",
dir_site="C15", nxt_site="C16", stp_site="B16", reset_site="G16"),
# Target port power switching
# Note: the r0.1 boards that have been produced incorrectly use the AP22814B
# instead of the AP22814A. This inverts the load-switch enables.
#
Resource("power_a_port", 0, PinsN("C14", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("pass_through_vbus", 0, PinsN("D14", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("target_vbus_fault", 0, Pins("K15", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
# HyperRAM (1V8 domain).
Resource("ram", 0,
# Note: our clock uses the pseudo-differential I/O present on the top tiles.
# This requires a recent version of trellis+nextpnr. If your build complains
# that LVCMOS18D is an invalid I/O type, you'll need to upgrade.
Subsignal("clk", DiffPairs("B14", "A15", dir="o"), Attrs(IO_TYPE="LVCMOS18D")),
Subsignal("dq", Pins("A11 B10 B12 A12 B11 A10 B9 A9", dir="io")),
Subsignal("rwds", Pins( "A13", dir="io")),
Subsignal("cs", PinsN("A14", dir="o")),
Subsignal("reset", PinsN("B13", dir="o")),
Attrs(IO_TYPE="LVCMOS18", SLEWRATE="FAST")
),
# User I/O connections.
Resource("user_io", 0, Pins("A5", dir="io"), Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST")),
Resource("user_io", 1, Pins("A4", dir="io"), Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST")),
Resource("user_io", 2, Pins("A3", dir="io"), Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST")),
Resource("user_io", 3, Pins("A2", dir="io"), Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST")),
]
connectors = [
# User I/O connector.
Connector("user_io", 0, """
A5 - A2
A4 - A3
""")
]
def toolchain_prepare(self, fragment, name, **kwargs):
overrides = {
'ecppack_opts': '--compress --idcode {} --freq 38.8'.format(0x21111043)
}
return super().toolchain_prepare(fragment, name, **overrides, **kwargs)
def toolchain_program(self, products, name):
""" Programs the relevant LUNA board via its sideband connection. """
from luna.apollo import ApolloDebugger
from luna.apollo.ecp5 import ECP5_JTAGProgrammer
# Create our connection to the debug module.
debugger = ApolloDebugger()
# Grab our generated bitstream, and upload it to the FPGA.
bitstream = products.get("{}.bit".format(name))
with debugger.jtag as jtag:
programmer = ECP5_JTAGProgrammer(jtag)
programmer.configure(bitstream)
def toolchain_flash(self, products, name="top"):
""" Programs the LUNA board's flash via its sideband connection. """
from luna.apollo import ApolloDebugger
from luna.apollo.flash import ensure_flash_gateware_loaded
# Create our connection to the debug module.
debugger = ApolloDebugger()
ensure_flash_gateware_loaded(debugger, platform=self.__class__())
# Grab our generated bitstream, and upload it to the .
bitstream = products.get("{}.bit".format(name))
with debugger.flash as flash:
flash.program(bitstream)
debugger.soft_reset()
def toolchain_erase(self):
""" Erases the LUNA board's flash. """
from luna.apollo import ApolloDebugger
from luna.apollo.flash import ensure_flash_gateware_loaded
# Create our connection to the debug module.
debugger = ApolloDebugger()
ensure_flash_gateware_loaded(debugger, platform=self.__class__())
with debugger.flash as flash:
flash.erase()
debugger.soft_reset()
class OrangeCrabR0D2(OrangeCrabPlatform, LUNAPlatform):
""" Board description for OrangeCrab r0.2. """
name = "OrangeCrab r0.2"
#
# I/O resources.
#
resources = [
# System clock.
Resource("clk_48MHz", 0, Pins("A9"), Attrs(IO_TYPE="LVCMOS33"),
Clock(48e6)),
# Self-reset.
Resource("rst_n", 0, Pins("V17"), Attrs(IO_TYPE="LVCMOS33")),
# Buttons.
Resource("user_button", 0, Pins("J17"), Attrs(IO_TYPE="SSTL135_I")),
# LEDs.
Resource(
"rgb_led",
0,
Subsignal("r", Pins("K4", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Subsignal("g", Pins("M3", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Subsignal("b", Pins("J3", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
),
# Create aliases for our LEDs with standard naming.
Resource("led", 0, Pins("K4", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 1, Pins("M3", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 2, Pins("J3", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
# RAM.
Resource(
"ddram", 0,
Subsignal(
"a", Pins("C4 D2 D3 A3 A4 D4 C3 B2"
"B1 D1 A7 C2 B6 C1 A2 C7"),
Attrs(IO_TYPE="SSTL135_I")),
Subsignal(
"ba",
Pins("D6 B7 A6"),
Attrs(IO_TYPE="SSTL135_I"),
), Subsignal("ras_n", Pins("C12"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("cas_n", Pins("D13"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("we_n", Pins("B12"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("cs_n", Pins("A12"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("dm", Pins("D16 G16"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal(
"dq",
Pins("C17 D15 B17 C16 A15 B13 A17 A13"
"F17 F16 G15 F15 J16 C18 H16 F18"),
Attrs(IO_TYPE="SSTL135_I"), Attrs(TERMINATION="75")),
Subsignal("dqs_p", Pins("B15 G18"), Attrs(IO_TYPE="SSTL135D_I"),
Attrs(TERMINATION="OFF"), Attrs(DIFFRESISTOR="100")),
Subsignal("clk_p", Pins("J18"), Attrs(IO_TYPE="SSTL135D_I")),
Subsignal("cke", Pins("D18"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("odt", Pins("C13"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("reset_n", Pins("L18"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("vccio", Pins("K16 D17 K15 K17 B18 C6"),
Attrs(IO_TYPE="SSTL135_II")),
Subsignal("gnd", Pins("L15 L16"), Attrs(IO_TYPE="SSTL135_II")),
Attrs(SLEWRATE="FAST")),
# USB Connector.
Resource("usb", 0, Subsignal("d_p", Pins("N1", dir="io")),
Subsignal("d_n", Pins("M2", dir="io")),
Subsignal("pullup", Pins("N2", dir="o")),
Attrs(IO_TYPE="LVCMOS33")),
# Onboard flash.
Resource(
"spiflash4x",
0,
Subsignal("cs_n", Pins("U17"), Attrs(IO_TYPE="LVCMOS33")),
#Subsignal("clk", Pins("U16"), Attrs(IO_TYPE="LVCMOS33")),
Subsignal("dq", Pins("U18 T18 R18 N18"),
Attrs(IO_TYPE="LVCMOS33")),
),
Resource(
"spiflash",
0,
Subsignal("cs_n", Pins("U17"), Attrs(IO_TYPE="LVCMOS33")),
#Subsignal("clk", Pins("U16"), Attrs(IO_TYPE="LVCMOS33")), # Note: CLK is bound using USRMCLK block
Subsignal("miso", Pins("T18"), Attrs(IO_TYPE="LVCMOS33")),
Subsignal("mosi", Pins("U18"), Attrs(IO_TYPE="LVCMOS33")),
Subsignal("wp", Pins("R18"), Attrs(IO_TYPE="LVCMOS33")),
Subsignal("hold", Pins("N18"), Attrs(IO_TYPE="LVCMOS33")),
),
# SD Card.
Resource(
"spisdcard",
0,
Subsignal("clk", Pins("K1")),
Subsignal("mosi", Pins("K2"), Attrs(PULLMODE="UP")),
Subsignal("cs_n", Pins("M1"), Attrs(PULLMODE="UP")),
Subsignal("miso", Pins("J1"), Attrs(PULLMODE="UP")),
Attrs(SLEW="FAST"),
Attrs(IO_TYPE="LVCMOS33"),
),
# User I/O
Resource("user_io", 0, Pins("N17")),
Resource("user_io", 1, Pins("M18")),
Resource("user_io", 2, Pins("C10")),
Resource("user_io", 3, Pins("C9")),
# 4
Resource("user_io", 5, Pins("B10")),
Resource("user_io", 6, Pins("B9")),
# 7
# 8
Resource("user_io", 9, Pins("C8")),
Resource("user_io", 10, Pins("B8")),
Resource("user_io", 11, Pins("A8")),
Resource("user_io", 12, Pins("H2")),
Resource("user_io", 13, Pins("J2")),
Resource("user_io", 14, Pins("N15")),
Resource("user_io", 15, Pins("R17")),
Resource("user_io", 16, Pins("N16")),
# 17
Resource("user_io", 18, Pins("L4")),
Resource("user_io", 19, Pins("N3")),
Resource("user_io", 20, Pins("N4")),
Resource("user_io", 21, Pins("H4")),
Resource("user_io", 22, Pins("G4")),
Resource("user_io", 23, Pins("T17")),
]
connectors = [
Connector(
"GPIO", 0,
"N17 M18 C10 C9 - B10 B9 - - C8 B8 A8 H2 J2 N15 R17 N16 - L4 N3 N4 H4 G4 T17"
)
]
class OrangeCrabR0D1(OrangeCrabPlatform, LUNAPlatform):
""" Board description for OrangeCrab r0.1. """
name = "OrangeCrab r0.1"
#
# I/O resources.
#
resources = [
Resource("clk_48MHz", 0, Pins("A9"), Attrs(IO_TYPE="LVCMOS33"),
Clock(48e6)),
Resource(
"rgb_led",
0,
Subsignal("r", Pins("V17"), Attrs(IO_TYPE="LVCMOS33")),
Subsignal("g", Pins("T17"), Attrs(IO_TYPE="LVCMOS33")),
Subsignal("b", Pins("J3"), Attrs(IO_TYPE="LVCMOS33")),
),
Resource(
"ddram", 0,
Subsignal("a", Pins("A4 D2 C3 C7 D3 D4 D1 B2 C1 A2 A7 C2 C4"),
Attrs(IO_TYPE="SSTL135_I")),
Subsignal("ba", Pins("B6 B7 A6"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("ras_n", Pins("C12"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("cas_n", Pins("D13"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("we_n", Pins("B12"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("cs_n", Pins("A12"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("dm", Pins("D16 G16"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal(
"dq",
Pins(
"C17 D15 B17 C16 A15 B13 A17 A13 F17 F16 G15 F15 J16 C18 H16 F18"
), Attrs(IO_TYPE="SSTL135_I", TERMINATION="75")),
Subsignal(
"dqs_p", Pins("B15 G18"),
Attrs(IO_TYPE="SSTL135D_I",
TERMINATION="OFF",
DIFFRESISTOR="100")),
Subsignal("clk_p", Pins("J18"), Attrs(IO_TYPE="SSTL135D_I")),
Subsignal("cke", Pins("D6"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("odt", Pins("C13"), Attrs(IO_TYPE="SSTL135_I")),
Subsignal("reset_n", Pins("B1"), Attrs(IO_TYPE="SSTL135_I")),
Attrs(SLEWRATE="FAST")),
Resource("spiflash4x", 0, Subsignal("cs_n", Pins("U17")),
Subsignal("clk", Pins("U16")),
Subsignal("dq", Pins("U18 T18 R18 N18")),
Attrs(IO_TYPE="LVCMOS33")),
Resource("spi-internal", 0,
Subsignal("cs_n", Pins("B11"), Attrs(PULLMODE="UP")),
Subsignal("clk", Pins("C11")),
Subsignal("miso", Pins("A11"), Attrs(PULLMODE="UP")),
Subsignal("mosi", Pins("A10"), Attrs(PULLMODE="UP")),
Attrs(IO_TYPE="LVCMOS33", SLEWRATE="SLOW")),
Resource(
"spisdcard",
0,
Subsignal("clk", Pins("K1")),
Subsignal("mosi", Pins("K2"), Attrs(PULLMODE="UP")),
Subsignal("cs_n", Pins("M1"), Attrs(PULLMODE="UP")),
Subsignal("miso", Pins("J1"), Attrs(PULLMODE="UP")),
Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST"),
),
# USB Connector.
Resource("usb", 0, Subsignal("d_p", Pins("N1", dir="io")),
Subsignal("d_n", Pins("M2", dir="io")),
Subsignal("pullup", Pins("N2", dir="o")),
Attrs(IO_TYPE="LVCMOS33")),
]
connectors = [
Connector(
"GPIO", 0,
"N17 M18 C10 C9 - B10 B9 - - C8 B8 A8 H2 J2 N15 R17 N16 - - - - - - - -"
)
]
class FMCWRadar(Xilinx7SeriesPlatform):
"""
"""
device = "XC7A15T"
package = "FTG256"
speed = "1"
resources = [
Resource(
"clk40",
0,
Pins("N11", dir="i"),
Clock(40e6),
Attrs(IOSTANDARD="LVCMOS33"),
),
Resource(
"ft_data_io",
0,
Pins("F15 G16 G15 F14 E16 E15 D16 D15", dir="io"),
Attrs(IOSTANDARD="LVCMOS33"),
),
Resource(
"ft_clkout_i",
0,
Pins("A15", dir="i"),
Clock(60e6),
Attrs(IOSTANDARD="LVCMOS33"),
),
Resource(
"ft_wr_n_o", 0, Pins("A14", dir="o"), Attrs(IOSTANDARD="LVCMOS33")
),
Resource(
"ft_rd_n_o", 0, Pins("B14", dir="o"), Attrs(IOSTANDARD="LVCMOS33")
),
Resource(
"ft_rxf_n_i", 0, Pins("B16", dir="i"), Attrs(IOSTANDARD="LVCMOS33")
),
Resource(
"ft_txe_n_i", 0, Pins("B15", dir="i"), Attrs(IOSTANDARD="LVCMOS33")
),
Resource(
"ft_siwua_n_o",
0,
Pins("A13", dir="o"),
Attrs(IOSTANDARD="LVCMOS33"),
),
Resource(
"ft_oe_n_o", 0, Pins("A12", dir="o"), Attrs(IOSTANDARD="LVCMOS33")
),
Resource(
"ft_suspend_n_i",
0,
Pins("C16", dir="i"),
Attrs(IOSTANDARD="LVCMOS33"),
),
Resource(
"adc_d_i",
0,
Pins("L2 K2 K1 J3 H1 H2 H3 G2 G1 F2 E1 E2", dir="i"),
Attrs(IOSTANDARD="LVCMOS33"),
),
Resource(
"adc_oe_o",
0,
Pins("B2 P1", dir="o"),
Attrs(IOSTANDARD="LVCMOS33"),
),
Resource(
"adc_shdn_o",
0,
Pins("B1 N2", dir="o"),
Attrs(IOSTANDARD="LVCMOS33"),
),
Resource("led", 0, Pins("D1", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource(
"ext1",
0,
Pins("C11 B10 A9 C12 B9 A8", dir="o"),
Attrs(IOSTANDARD="LVCMOS33"),
),
Resource(
"pa_en_n_o", 0, Pins("T2", dir="o"), Attrs(IOSTANDARD="LVCMOS33")
),
Resource(
"mix_en_n_o", 0, Pins("J4", dir="o"), Attrs(IOSTANDARD="LVCMOS33")
),
]
connectors = []
default_clk = "clk40"
def toolchain_program(self, products, name):
# bitstream = products.get("{}.bin".format(name))
os.system("openocd -f interface.cfg -f program_fpga.cfg")
class Supercon2019Badge(LatticeECP5Platform, LUNAPlatform):
""" Platform for the Supercon 2019 badge (final, black PCB). """
name = "HAD Supercon 2019 Badge"
device = "LFE5U-45F"
package = "BG381"
speed = "8"
default_clk = "clk8"
# Provide the type that'll be used to create our clock domains.
clock_domain_generator = SuperconDomainGenerator
# We only have a direct connection on our USB lines, so use that for USB comms.
default_usb_connection = "usb"
#
# I/O resources.
#
resources = [
Resource("clk8", 0, Pins("U18"), Clock(8e6),
Attrs(IOStandard="LVCMOS33")),
Resource("programn", 0, Pins("R1"), Attrs(IOStandard="LVCMOS33")),
Resource(
"serial",
0,
Subsignal("rx", Pins("U2"), Attrs(IOStandard="LVCMOS33"),
Attrs(PULLMODE="UP")),
Subsignal("tx", Pins("U1"), Attrs(IOStandard="LVCMOS33")),
),
# Full LED array.
Resource("led_anodes", 0,
Pins("E3 D3 C3 C4 C2 B1 B20 B19 A18 K20 K19"),
Attrs(IOStandard="LVCMOS33")), # Anodes
Resource("led_cathodes", 1, Pins("P19 L18 K18"),
Attrs(IOStandard="LVCMOS33")), # Cathodes via FET
# Compatibility aliases.
Resource("led", 0, Pins("E3")),
Resource("led", 1, Pins("D3")),
Resource("led", 2, Pins("C3")),
Resource("led", 3, Pins("C4")),
Resource("led", 4, Pins("C2")),
Resource("led", 5, Pins("B1")),
Resource("usb", 0, Subsignal("d_p", Pins("F3")),
Subsignal("d_n", Pins("G3")),
Subsignal("pullup", Pins("E4", dir="o")),
Subsignal("vbus_valid", Pins("F4", dir="i")),
Attrs(IOStandard="LVCMOS33")),
Resource(
"keypad",
0,
Subsignal("left", Pins("G2"), Attrs(PULLMODE="UP")),
Subsignal("right", Pins("F2"), Attrs(PULLMODE="UP")),
Subsignal("up", Pins("F1"), Attrs(PULLMODE="UP")),
Subsignal("down", Pins("C1"), Attrs(PULLMODE="UP")),
Subsignal("start", Pins("E1"), Attrs(PULLMODE="UP")),
Subsignal("select", Pins("D2"), Attrs(PULLMODE="UP")),
Subsignal("a", Pins("D1"), Attrs(PULLMODE="UP")),
Subsignal("b", Pins("E2"), Attrs(PULLMODE="UP")),
),
Resource(
"hdmi_out",
0,
Subsignal("clk_p", PinsN("P20"), Attrs(IOStandard="TMDS_33")),
Subsignal("clk_n", PinsN("R20"), Attrs(IOStandard="TMDS_33")),
Subsignal("data0_p", Pins("N19"), Attrs(IOStandard="TMDS_33")),
Subsignal("data0_n", Pins("N20"), Attrs(IOStandard="TMDS_33")),
Subsignal("data1_p", Pins("L20"), Attrs(IOStandard="TMDS_33")),
Subsignal("data1_n", Pins("M20"), Attrs(IOStandard="TMDS_33")),
Subsignal("data2_p", Pins("L16"), Attrs(IOStandard="TMDS_33")),
Subsignal("data2_n", Pins("L17"), Attrs(IOStandard="TMDS_33")),
Subsignal("hpd_notif", PinsN("R18"),
Attrs(IOStandard="LVCMOS33")), # Also called HDMI_HEAC_n
Subsignal("hdmi_heac_p", PinsN("T19"),
Attrs(IOStandard="LVCMOS33")),
Attrs(DRIVE=4),
),
Resource(
"lcd",
0,
Subsignal(
"db",
Pins("J3 H1 K4 J1 K3 K2 L4 K1 L3 L2 M4 L1 M3 M1 N4 N2 N3 N1"),
Attrs(IOStandard="LVCMOS33")),
Subsignal("rd", Pins("P2"), Attrs(IOStandard="LVCMOS33")),
Subsignal("wr", Pins("P4"), Attrs(IOStandard="LVCMOS33")),
Subsignal("rs", Pins("P1"), Attrs(IOStandard="LVCMOS33")),
Subsignal("cs", Pins("P3"), Attrs(IOStandard="LVCMOS33")),
Subsignal("id", Pins("J4"), Attrs(IOStandard="LVCMOS33")),
Subsignal("rst", Pins("H2"), Attrs(IOStandard="LVCMOS33")),
Subsignal("fmark", Pins("G1"), Attrs(IOStandard="LVCMOS33")),
Subsignal("blen", Pins("P5"), Attrs(IOStandard="LVCMOS33")),
),
Resource(
"spiflash",
0, # clock needs to be accessed through USRMCLK
Subsignal("cs_n", Pins("R2"), Attrs(IOStandard="LVCMOS33")),
Subsignal("mosi", Pins("W2"), Attrs(IOStandard="LVCMOS33")),
Subsignal("miso", Pins("V2"), Attrs(IOStandard="LVCMOS33")),
Subsignal("wp", Pins("Y2"), Attrs(IOStandard="LVCMOS33")),
Subsignal("hold", Pins("W1"), Attrs(IOStandard="LVCMOS33")),
),
Resource(
"spiflash4x",
0, # clock needs to be accessed through USRMCLK
Subsignal("cs_n", Pins("R2"), Attrs(IOStandard="LVCMOS33")),
Subsignal("dq", Pins("W2 V2 Y2 W1"), Attrs(IOStandard="LVCMOS33")),
),
Resource(
"spiram4x",
0,
Subsignal("cs_n", Pins("D20"), Attrs(IOStandard="LVCMOS33"),
Attrs(SLEWRATE="SLOW")),
Subsignal("clk", Pins("E20"), Attrs(IOStandard="LVCMOS33"),
Attrs(SLEWRATE="SLOW")),
Subsignal("dq", Pins("E19 D19 C20 F19"),
Attrs(IOStandard="LVCMOS33"), Attrs(PULLMODE="UP"),
Attrs(SLEWRATE="SLOW")),
),
Resource(
"spiram4x",
1,
Subsignal("cs_n", Pins("F20"), Attrs(IOStandard="LVCMOS33"),
Attrs(SLEWRATE="SLOW")),
Subsignal("clk", Pins("J19"), Attrs(IOStandard="LVCMOS33"),
Attrs(SLEWRATE="SLOW")),
Subsignal("dq", Pins("J20 G19 G20 H20"),
Attrs(IOStandard="LVCMOS33"), Attrs(PULLMODE="UP"),
Attrs(SLEWRATE="SLOW")),
),
Resource(
"sao",
0,
Subsignal("sda", Pins("B3")),
Subsignal("scl", Pins("B2")),
Subsignal("gpio", Pins("A2 A3 B4")),
Subsignal("drm", Pins("A4")),
),
Resource(
"sao",
1,
Subsignal("sda", Pins("A16")),
Subsignal("scl", Pins("B17")),
Subsignal("gpio", Pins("B18 A17 B16")),
Subsignal("drm", Pins("C17")),
),
Resource(
"testpts",
0,
Subsignal("a1", Pins("A15")),
Subsignal("a2", Pins("C16")),
Subsignal("a3", Pins("A14")),
Subsignal("a4", Pins("D16")),
Subsignal("b1", Pins("B15")),
Subsignal("b2", Pins("C15")),
Subsignal("b3", Pins("A13")),
Subsignal("b4", Pins("B13")),
),
Resource("sdram_clock", 0, Pins("D11"), Attrs(IOStandard="LVCMOS33")),
Resource(
"sdram", 0,
Subsignal("a",
Pins("A8 D9 C9 B9 C14 E17 A12 B12 H17 G18 B8 A11 B11")),
Subsignal("dq", Pins("C5 B5 A5 C6 B10 C10 D10 A9")),
Subsignal("we_n", Pins("B6")), Subsignal("ras_n", Pins("D6")),
Subsignal("cas_n", Pins("A6")), Subsignal("cs_n", Pins("C7")),
Subsignal("cke", Pins("C11")), Subsignal("ba", Pins("A7 C8")),
Subsignal("dm", Pins("A10")), Attrs(IOStandard="LVCMOS33"),
Attrs(SLEWRATE="FAST")),
# Compatibility.
Resource("user_io", 0, Pins("A15")),
Resource("user_io", 1, Pins("C16")),
Resource("user_io", 2, Pins("A14")),
Resource("user_io", 3, Pins("D16")),
]
connectors = [
Connector("pmod", 0, "A15 C16 A14 D16 B15 C15 A13 B13"),
Connector(
"genio", 0,
"C5 B5 A5 C6 B6 A6 D6 C7 A7 C8 B8 A8 D9 C9 B9 A9 D10 C10 B10 A10 D11 C11 B11 A11 G18 H17 B12 A12 E17 C14"
),
]
def __init__(self, *args, **kwargs):
logging.warning(
"This platform is not officially supported, and thus not tested.")
logging.warning("Your results may vary.")
super().__init__(*args, **kwargs)
def toolchain_prepare(self, fragment, name, **kwargs):
overrides = {'ecppack_opts': '--compress --freq 38.8'}
return super().toolchain_prepare(fragment, name, **overrides, **kwargs)
def toolchain_program(self, products, name):
""" Program the flash of an Supercon board. """
# Use the DFU bootloader to program the ECP5 bitstream.
dfu_util = os.environ.get("DFU_UTIL", "dfu-util")
with products.extract("{}.bit".format(name)) as bitstream_filename:
subprocess.check_call([
dfu_util, "-d", "1d50:614b", "-a", "0", "-D",
bitstream_filename
])
def toolchain_flash(self, products, name="top"):
""" Program the flash of an Supercon cartridge. """
# Use the DFU bootloader to program the ECP5 bitstream.
dfu_util = os.environ.get("DFU_UTIL", "dfu-util")
with products.extract("{}.bit".format(name)) as bitstream_filename:
subprocess.check_call([
dfu_util, "-d", "1d50:614b", "-a", "2", "-D",
bitstream_filename
])
class AmaltheaPlatformRev0D1(LatticeECP5Platform):
""" Board description for the pre-release r0.1 revision of LUNA. """
name = "Amalthea r0.1 (26MHz mod)"
device = "LFE5U-12F"
package = "BG256"
speed = os.getenv("LUNA_SPEED_GRADE", "8")
default_clk = "clk_26MHz"
# Provide the type that'll be used to create our clock domains.
clock_domain_generator = DomainGenerator
#
# Default clock frequencies for each of our clock domains.
#
# Different revisions have different FPGA speed grades, and thus the
# default frequencies will vary.
#
DEFAULT_CLOCK_FREQUENCIES_MHZ = {
"fast": 240,
"sync": 120,
"usb": 60
}
#
# Preferred DRAM bus I/O (de)-skewing constants.
#
ram_timings = dict(
clock_skew = 64
)
# Provides any platform-specific ULPI registers necessary.
# This is the spot to put any platform-specific vendor registers that need
# to be written.
ulpi_extra_registers = {
0x39: 0b000110 # USB3343: swap D+ and D- to match the LUNA boards
}
#
# I/O resources.
#
resources = [
# 26MHz clock from AT86RF215 CLKOUT.
Resource("clk_26MHz", 0, Pins("A7", dir="i"),
Clock(26e6), Attrs(IO_TYPE="LVCMOS33")),
# Connection to our SPI flash; can be used to work with the flash
# from e.g. a bootloader.
Resource("spi_flash", 0,
# SCK is on pin 9; but doesn't have a traditional I/O buffer.
# Instead, we'll need to drive a clock into a USRMCLK instance.
# See interfaces/flash.py for more information.
Subsignal("sdi", Pins("T8", dir="o")),
Subsignal("sdo", Pins("T7", dir="i")),
# In r0.1, the chip select line can either be driven by the FPGA
# or by the Debug Controller. Accordingly, we'll mark the line as
# bidirectional, and let the user decide.
Subsignal("cs", PinsN("N8", dir="io")),
Attrs(IO_TYPE="LVCMOS33")
),
# UART connected to the debug controller; can be routed to a host via CDC-ACM.
Resource("uart", 0,
Subsignal("rx", Pins("R14", dir="i")),
Subsignal("tx", Pins("T14", dir="o")),
Attrs(IO_TYPE="LVCMOS33")
),
# SPI bus connected to the debug controller, for simple register exchanges.
# Note that the Debug Controller is the master on this bus.
Resource("debug_spi", 0,
Subsignal("sck", Pins( "R13", dir="i")),
Subsignal("sdi", Pins( "P13", dir="i")),
Subsignal("sdo", Pins( "P11", dir="o")),
Subsignal("cs", PinsN("T13", dir="i")),
Attrs(IO_TYPE="LVCMOS33")
),
# FPGA-connected LEDs.
Resource("led", 5, PinsN("P15", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 4, PinsN("N16", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 3, PinsN("M15", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 2, PinsN("M16", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 1, PinsN("L15", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("led", 0, PinsN("L16", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
# USB PHYs
ULPIResource("sideband_phy",
data_sites="R2 R1 P2 P1 N1 M2 M1 L2", clk_site="R4",
dir_site="T3", nxt_site="T2", stp_site="T4", reset_site="R3"),
ULPIResource("host_phy",
data_sites="G2 G1 F2 F1 E1 D1 C1 C2", clk_site="K2",
dir_site="J1", nxt_site="H2", stp_site="J2", reset_site="K1"),
# HyperRAM (1V8 domain).
Resource("ram", 0,
# Note: our clock uses the pseudo-differential I/O present on the top tiles.
# This requires a recent version of trellis+nextpnr. If your build complains
# that LVCMOS18D is an invalid I/O type, you'll need to upgrade.
Subsignal("clk", DiffPairs("B14", "A15", dir="o"), Attrs(IO_TYPE="LVCMOS18D")),
Subsignal("dq", Pins("A11 B10 B12 A12 B11 A10 B9 A9", dir="io")),
Subsignal("rwds", Pins( "A13", dir="io")),
Subsignal("cs", PinsN("A14", dir="o")),
Subsignal("reset", PinsN("B13", dir="o")),
Attrs(IO_TYPE="LVCMOS18", SLEWRATE="FAST")
),
# Radio.
Resource("radio", 0,
Subsignal("rst", PinsN("C14", dir="o")),
Subsignal("sclk", Pins( "K14", dir="o")),
Subsignal("sel", PinsN("E16", dir="o")),
Subsignal("mosi", Pins( "F16", dir="o")),
Subsignal("miso", Pins( "G16", dir="i")),
Subsignal("irq", Pins( "F15", dir="i")),
Subsignal("rxclk", DiffPairs("J16", "J15", dir="i"), Attrs(IO_TYPE="LVDS", DIFFRESISTOR="100", PULLMODE="UP")),
Subsignal("rxd09", DiffPairs("D16", "E15", dir="i"), Attrs(IO_TYPE="LVDS", DIFFRESISTOR="100")),
Subsignal("rxd24", DiffPairs("K16", "K15", dir="i"), Attrs(IO_TYPE="LVDS", DIFFRESISTOR="100")),
Subsignal("txclk", DiffPairs("B16", "B15", dir="o"), Attrs(IO_TYPE="LVCMOS33D", DRIVE="4")),
Subsignal("txd", DiffPairs("C16", "C15", dir="o"), Attrs(IO_TYPE="LVCMOS33D", DRIVE="4")),
Attrs(IO_TYPE="LVCMOS33"),
),
# User I/O connections.
# TODO: Update these for io0+/- & io1+/-
Resource("user_io", 0, Pins("A5", dir="io"), Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST")),
Resource("user_io", 1, Pins("A4", dir="io"), Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST")),
Resource("user_io", 2, Pins("A3", dir="io"), Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST")),
Resource("user_io", 3, Pins("A2", dir="io"), Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST")),
]
connectors = [
# User I/O connector.
Connector("user_io", 0, """
A5 - A2
A4 - A3
""")
]
def toolchain_prepare(self, fragment, name, **kwargs):
overrides = {
'ecppack_opts': '--compress --freq 38.8'
}
return super().toolchain_prepare(fragment, name, **overrides, **kwargs)
def toolchain_program(self, products, name):
""" Programs the relevant LUNA board via its sideband connection. """
from luna.apollo import ApolloDebugger
from luna.apollo.ecp5 import ECP5_JTAGProgrammer
# Create our connection to the debug module.
debugger = ApolloDebugger()
# Grab our generated bitstream, and upload it to the FPGA.
bitstream = products.get("{}.bit".format(name))
with debugger.jtag as jtag:
programmer = ECP5_JTAGProgrammer(jtag)
programmer.configure(bitstream)
def toolchain_flash(self, products, name="top"):
""" Programs the LUNA board's flash via its sideband connection. """
from luna.apollo import ApolloDebugger
from luna.apollo.flash import ensure_flash_gateware_loaded
# Create our connection to the debug module.
debugger = ApolloDebugger()
ensure_flash_gateware_loaded(debugger, platform=self.__class__())
# Grab our generated bitstream, and upload it to the .
bitstream = products.get("{}.bit".format(name))
with debugger.flash as flash:
flash.program(bitstream)
debugger.soft_reset()
def toolchain_erase(self):
""" Erases the LUNA board's flash. """
from luna.apollo import ApolloDebugger
from luna.apollo.flash import ensure_flash_gateware_loaded
# Create our connection to the debug module.
debugger = ApolloDebugger()
ensure_flash_gateware_loaded(debugger, platform=self.__class__())
with debugger.flash as flash:
flash.erase()
debugger.soft_reset()
class Basys3Platform(Xilinx7SeriesPlatform):
device = "xc7a35t"
package = "cpg236"
speed = "1"
default_clk = "CLK100"
# J connectors are layed out looking at the connector head-on [6-1],[12-7]
# J[A(0), B(1), C(2), XADC(3)]
connectors = [
# JA
Connector("J", 0, " - - G2 J2 L2 J1 "
" - - G3 H2 K2 H1 "),
# JB
Connector("J", 1, " - - B16 B15 A16 A14 "
" - - C16 C15 A17 A15 "),
# JC
Connector("J", 2, " - - P18 N17 M18 K17 "
" - - R18 P17 M19 L17 "),
# JXADC
Connector("J", 3, " - - N2 M2 L3 J3 "
" - - N1 M1 M3 K3 "),
]
resources = [
# Integrated 100MHz clock
Resource("CLK100", 0, Pins("W5", dir="i"), Clock(100e6),
Attrs(IOSTANDARD="LVCMOS33")),
# Onboard LEDs: LD[0-15]
Resource("LD", 0, Pins("U16", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 1, Pins("E19", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 2, Pins("U19", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 3, Pins("V19", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 4, Pins("W18", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 5, Pins("U15", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 6, Pins("U14", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 7, Pins("V14", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 8, Pins("V13", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 9, Pins("V3", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 10, Pins("W3", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 11, Pins("U3", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 12, Pins("P3", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 13, Pins("N3", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 14, Pins("P1", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("LD", 15, Pins("L1", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
# Onboard switches: SW[0-15]
Resource("SW", 0, Pins("V17", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 1, Pins("V16", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 2, Pins("W16", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 3, Pins("W17", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 4, Pins("W15", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 5, Pins("V15", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 6, Pins("W14", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 7, Pins("W13", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 8, Pins("V2", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 9, Pins("T3", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 10, Pins("T2", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 11, Pins("R3", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 12, Pins("W2", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 13, Pins("U1", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 14, Pins("T1", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("SW", 15, Pins("R2", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
# Onboard buttons: BTN[L(0),R(1),U(2),D(3),C(4)]
Resource("BTN", 0, Pins("W19", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("BTN", 1, Pins("T17", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("BTN", 2, Pins("T18", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("BTN", 3, Pins("U17", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("BTN", 4, Pins("U18", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
# 7seg anode/cathodes: AN[0-3] C[A(0),B(1),C(2),D(3),E(4),F(5),G(6),P(7)]
Resource("7SEG", 0, Subsignal("AN0", Pins("U2", dir="o")),
Subsignal("AN1", Pins("U4", dir="o")),
Subsignal("AN2", Pins("V4", dir="o")),
Subsignal("AN3", Pins("W4", dir="o")),
Subsignal("CA", PinsN("W7", dir="o")),
Subsignal("CB", PinsN("W6", dir="o")),
Subsignal("CC", PinsN("U8", dir="o")),
Subsignal("CD", PinsN("V8", dir="o")),
Subsignal("CE", PinsN("U5", dir="o")),
Subsignal("CF", PinsN("V5", dir="o")),
Subsignal("CG", PinsN("U7", dir="o")),
Subsignal("CP", PinsN("V7", dir="o")),
Attrs(IOSTANDARD="LVCMOS33")),
# VGA port
Resource("VGA", 0, Subsignal("RED0", Pins("G19", dir="o")),
Subsignal("RED1", Pins("H19", dir="o")),
Subsignal("RED2", Pins("J19", dir="o")),
Subsignal("RED3", Pins("N19", dir="o")),
Subsignal("GRN0", Pins("J17", dir="o")),
Subsignal("GRN1", Pins("H17", dir="o")),
Subsignal("GRN2", Pins("G17", dir="o")),
Subsignal("GRN3", Pins("D17", dir="o")),
Subsignal("BLU0", Pins("N18", dir="o")),
Subsignal("BLU1", Pins("L18", dir="o")),
Subsignal("BLU2", Pins("K18", dir="o")),
Subsignal("BLU3", Pins("J18", dir="o")),
Subsignal("HSYNC", Pins("P19", dir="o")),
Subsignal("VSYNC", Pins("R19", dir="o")),
Attrs(IOSTANDARD="LVCMOS33")),
# JA GPIO
Resource("JA", 0, Subsignal("P1", Pins("J1")),
Subsignal("P2", Pins("L2")), Subsignal("P3", Pins("J2")),
Subsignal("P4", Pins("G2")), Subsignal("P7", Pins("H1")),
Subsignal("P8", Pins("K2")), Subsignal("P9", Pins("H2")),
Subsignal("P10", Pins("G3")), Attrs(IOSTANDARD="LVCMOS33")),
# JB GPIO
Resource("JB", 0, Subsignal("P1", Pins("A14")),
Subsignal("P2", Pins("A16")), Subsignal("P3", Pins("B15")),
Subsignal("P4", Pins("B16")), Subsignal("P7", Pins("A15")),
Subsignal("P8", Pins("A17")), Subsignal("P9", Pins("C15")),
Subsignal("P10", Pins("C16")), Attrs(IOSTANDARD="LVCMOS33")),
# JC GPIO
Resource("JC", 0, Subsignal("P1", Pins("K17")),
Subsignal("P2", Pins("M18")), Subsignal("P3", Pins("N17")),
Subsignal("P4", Pins("P18")), Subsignal("P7", Pins("L17")),
Subsignal("P8", Pins("M19")), Subsignal("P9", Pins("P17")),
Subsignal("P10", Pins("R18")), Attrs(IOSTANDARD="LVCMOS33")),
# JXADC GPIO
Resource("JXADC", 0, Subsignal("P1", Pins("J3")),
Subsignal("P2", Pins("L3")), Subsignal("P3", Pins("M2")),
Subsignal("P4", Pins("N2")), Subsignal("P7", Pins("K3")),
Subsignal("P8", Pins("M3")), Subsignal("P9", Pins("M1")),
Subsignal("P10", Pins("N1")), Attrs(IOSTANDARD="LVCMOS33")),
# Onboard SPI flash
*SPIFlashResources(0,
cs="K19",
clk="C11",
mosi="D18",
miso="D19",
wp="G18",
hold="F18",
attrs=Attrs(IOSTANDARD="LVCMOS33")),
]
def toolchain_program(self, products, name):
djtgcfg = os.environ.get("DJTGCFG", "djtgcfg")
with products.extract("{}.bit".format(name)) as bitstream_filename:
subprocess.run([
djtgcfg, "prog", "-d", "Basys3", "-i", "0", "-f",
bitstream_filename
],
check=True)
class ColorLite5A75E_V6_0_Platform(LatticeECP5Platform):
device = "LFE5U-25F"
package = "BG256"
speed = "6"
default_clk = "clk25"
lvcmos = Attrs(IO_TYPE="LVCMOS33")
resources = [
Resource("clk25", 0, Pins("P6", dir="i"), Clock(25e6), lvcmos),
Resource("led", 0, Pins("T6", dir="o"), lvcmos),
Resource("key", 0, PinsN("R7", dir="i"), lvcmos),
Resource("flash", 0, Subsignal("cs", Pins("N8", dir="o"), lvcmos),
Subsignal("so", Pins("T7", dir="i"), lvcmos),
Subsignal("si", Pins("T8", dir="o"), lvcmos)),
Resource("led_common", 0, Subsignal("a", Pins("N5", dir="o"), lvcmos),
Subsignal("b", Pins("N3", dir="o"), lvcmos),
Subsignal("c", Pins("P3", dir="o"), lvcmos),
Subsignal("d", Pins("P4", dir="o"), lvcmos),
Subsignal("e", Pins("N4", dir="o"), lvcmos),
Subsignal("clk", Pins("M3", dir="o"), lvcmos),
Subsignal("lat", Pins("N1", dir="o"), lvcmos),
Subsignal("oe", Pins("M4", dir="o"), lvcmos)),
Resource("eth_common", 0, Subsignal("mdc", Pins("R5", dir="o"),
lvcmos),
Subsignal("mdio", Pins("T4", dir="io"), lvcmos),
Subsignal("rst", PinsN("R6", dir="o"), lvcmos)),
Resource("phy", 0, Subsignal("txc", Pins("L1", dir="o"), lvcmos),
Subsignal("txd", Pins("M2 M1 P1 R1", dir="o"), lvcmos),
Subsignal("txctl", Pins("L2", dir="o"), lvcmos),
Subsignal("rxc", Pins("J1", dir="i"), lvcmos),
Subsignal("rxd", Pins("J3 K2 K1 K3", dir="i"), lvcmos),
Subsignal("rxctl", Pins("J2", dir="i"), lvcmos)),
Resource("phy", 1, Subsignal("txc", Pins("J16", dir="o"), lvcmos),
Subsignal("txd", Pins("K16 J15 J14 K15", dir="o"), lvcmos),
Subsignal("txctl", Pins("K14", dir="o"), lvcmos),
Subsignal("rxc", Pins("M16", dir="i"), lvcmos),
Subsignal("rxd", Pins("M15 R16 L15 L16", dir="i"), lvcmos),
Subsignal("rxctl", Pins("P16", dir="i"), lvcmos)),
Resource(
"sdram", 0, Subsignal("we", PinsN("B5", dir="o"), lvcmos),
Subsignal("cas", PinsN("A6", dir="o"), lvcmos),
Subsignal("ras", PinsN("B6", dir="o"), lvcmos),
Subsignal("ba", Pins("B7 A8", dir="o"), lvcmos),
Subsignal("a", Pins("A9 B9 B10 C10 D9 C9 E9 D8 E8 C7 B8", dir="o"),
lvcmos),
Subsignal(
"d",
Pins(
"D5 C5 E5 C6 D6 E6 D7 E7 D10 C11 D11 C12 E10 C13 "
"D13 E11 A5 B4 A4 B3 A3 C3 A2 B2 D14 B14 A14 B13 "
"A13 B12 B11 A11",
dir="io"), lvcmos),
Subsignal("clk", Pins("C8", dir="o"), lvcmos)),
]
connectors = []
# Used by __init__ to create each individual LED pin header
leds = [
# R0, G0, B0, R1, G1, B1
['C4', 'D4', 'E4', 'D3', 'E3', 'F4'], # J1
['F3', 'F5', 'G3', 'G4', 'H3', 'H4'], # J2
['G5', 'H5', 'J5', 'J4', 'B1', 'C2'], # J3
['C1', 'D1', 'E2', 'E1', 'F2', 'F1'], # J4
['G2', 'G1', 'H2', 'K5', 'K4', 'L3'], # J5
['L4', 'L5', 'P2', 'R2', 'T2', 'R3'], # J6
['T3', 'R4', 'M5', 'P5', 'N6', 'N7'], # J7
['P7', 'M7', 'P8', 'R8', 'M8', 'M9'], # J8
['P11', 'N11', 'M11', 'T13', 'R12', 'R13'], # J9
['R14', 'T14', 'D16', 'C15', 'C16', 'B16'], # J10
['B15', 'C14', 'T15', 'P15', 'R15', 'P12'], # J11
['P13', 'N12', 'N13', 'M12', 'P14', 'N14'], # J12
['H15', 'H14', 'G16', 'F16', 'G15', 'F15'], # J13
['E15', 'E16', 'L12', 'L13', 'M14', 'L14'], # J14
['J13', 'K13', 'J12', 'H13', 'H12', 'G12'], # J15
['G14', 'G13', 'F12', 'F13', 'F14', 'E14'], # J16
]
# Currently unknown inputs/outputs/bidirectional
inputs = ['A10', 'A12']
outputs = ['A7', 'A15', 'E12', 'E13', 'K12', 'M6', 'M13']
bidis = ['D12']
def __init__(self):
lvcmos = self.lvcmos
# Create resources for each LED header
for jidx, pins in enumerate(self.leds):
self.resources += [
Resource("led_rgb", jidx,
Subsignal("r0", Pins(pins[0], dir="o"), lvcmos),
Subsignal("g0", Pins(pins[1], dir="o"), lvcmos),
Subsignal("b0", Pins(pins[2], dir="o"), lvcmos),
Subsignal("r1", Pins(pins[3], dir="o"), lvcmos),
Subsignal("g1", Pins(pins[4], dir="o"), lvcmos),
Subsignal("b1", Pins(pins[5], dir="o"), lvcmos))
]
# Create resources for each unknown pin
for pin in self.outputs:
self.resources += [Resource(pin, 0, Pins(pin, dir="o"), lvcmos)]
for pin in self.inputs:
self.resources += [Resource(pin, 0, Pins(pin, dir="i"), lvcmos)]
for pin in self.bidis:
self.resources += [Resource(pin, 0, Pins(pin, dir="io"), lvcmos)]
super().__init__()
class OpenVizsla(XilinxSpartan6Platform):
""" Board description for OpenVizsla USB analyzer. """
name = "OpenVizsla"
device = "xc6slx9"
package = "tqg144"
speed = "3"
default_clk = "clk_12MHz"
# Provide the type that'll be used to create our clock domains.
clock_domain_generator = StubClockDomainGenerator
# We only have a single PHY; so use it directly.
default_usb_connection = "target_phy"
#
# I/O resources.
#
resources = [
# Clocks.
Resource("clk_12MHz", 0, Pins("P50", dir="i"), Clock(12e6),
Attrs(IOSTANDARD="LVCMOS33")),
# User button.
Resource("btn", 0, Pins("P67", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
# User LEDs.
Resource("led", 0, Pins("P57", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("led", 1, Pins("P58", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("led", 2, Pins("P59", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
# Core ULPI PHY.
ULPIResource(
"target_phy",
data_sites="P120 P119 P118 P117 P116 P115 P114 P112",
clk_site="P123",
dir_site="P124",
nxt_site="P121",
stp_site="P126",
reset_site="P127",
),
# Extra pins that the OpenVizsla calls the "spare" pins.
Resource("spare", 2, Pins("P102"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 3, Pins("P101"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 4, Pins("P100"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 5, Pins("P99"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 6, Pins("P98"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 7, Pins("P97"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 8, Pins("P95"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 9, Pins("P94"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 10, Pins("P93"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 11, Pins("P92"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 12, Pins("P88"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 13, Pins("P87"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 14, Pins("P85"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 15, Pins("P84"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 16, Pins("P83"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 17, Pins("P82"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 18, Pins("P81"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 19, Pins("P80"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 20, Pins("P79"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 21, Pins("P78"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 22, Pins("P75"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("spare", 23, Pins("P74"), Attrs(IOSTANDARD="LVCMOS33")),
# FTDI FIFO connection.
Resource("ftdi", 0, Subsignal("clk", Pins("P51")),
Subsignal("d", Pins("P65 P62 P61 P46 P45 P44 P43 P48")),
Subsignal("rxf_n", Pins("P55")),
Subsignal("txe_n",
Pins("P70")), Subsignal("rd_n", Pins("P41")),
Subsignal("wr_n", Pins("P40")),
Subsignal("siwua_n", Pins("P66")),
Subsignal("oe_n", Pins("P38")),
Attrs(IOSTANDARD="LVCMOS33", SLEW="FAST")),
# Trigger in/out pins.
# There's nothing stopping these from being used as I/O, so we'll allow them to be used either way.
Resource("trigger_in", 0, Pins("P75"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("trigger_out", 0, Pins("P74"), Attrs(IOSTANDARD="LVCMOS33")),
]
# TODO: detail the Spare connector here?
connectors = []
def toolchain_program(self, products, name):
""" Programs the OpenVizsla's FPGA. """
try:
from openvizsla import OVDevice
from openvizsla.libov import HW_Init
except ImportError:
raise ImportError(
"pyopenvizsla is required to program OpenVizsla boards")
# Connect to our OpenVizsla...
device = OVDevice()
failed = device.ftdi.open()
if failed:
raise IOError("Could not connect to OpenVizsla!")
# ... and pass it our bitstream.
try:
with products.extract(f"{name}.bit") as bitstream_file:
HW_Init(device.ftdi, bitstream_file.encode('ascii'))
finally:
device.ftdi.close()
def test_mmcm_calculation(self):
clocking = HdmiClocking(Clock(79.75e6))
clocking.find_valid_config()