def main():
# parser: add options
parser = argparse.ArgumentParser()
# add (extra) arguments
parser.add_argument("--config-file",
type=str,
help="configuration file",
required=True)
cli.main_parser(parser)
args = parser.parse_args()
# load the configuration file
configuration = cfg.Configuration(args.config_file)
# create the CPU
cpu = Bellatrix(configuration)
ports = [
# instruction port
cpu.iport.addr,
cpu.iport.dat_w,
cpu.iport.sel,
cpu.iport.we,
cpu.iport.cyc,
cpu.iport.stb,
cpu.iport.cti,
cpu.iport.bte,
cpu.iport.dat_r,
cpu.iport.ack,
cpu.iport.err,
# data port
cpu.dport.addr,
cpu.dport.dat_w,
cpu.dport.sel,
cpu.dport.we,
cpu.dport.cyc,
cpu.dport.stb,
cpu.dport.cti,
cpu.dport.bte,
cpu.dport.dat_r,
cpu.dport.ack,
cpu.dport.err,
# exceptions
cpu.external_interrupt,
cpu.timer_interrupt,
cpu.software_interrupt
]
# run
cli.main_runner(parser, args, cpu, name='bellatrix_core', ports=ports)
def formal(dut_mod, **kw_args):
parser = main_parser()
args = parser.parse_args()
m = Module()
m.submodules.dut = dut = dut_mod(**kw_args, FORMAL=True)
main_runner(parser, args, m, ports=dut.bus().ports())
def main(self):
m = Module()
ports = []
ports += self.verify_rtype(m)
ports += self.verify_itype(m)
ports += self.verify_stype(m)
ports += self.verify_btype(m)
ports += self.verify_utype(m)
ports += self.verify_jtype(m)
parser = main_parser()
args = parser.parse_args()
main_runner(parser, args, m, ports=ports)
def main():
m = Module()
clock = ClockInfo("i")
m.domains.i = clock.domain
m.submodules.core = core = Core(clock)
core.aux_ports.append(clock.clk)
core.aux_ports.append(clock.rst)
parser = main_parser()
parser.add_argument("--proof", type=str, help="generate signle proof")
args = parser.parse_args()
required_proof = args.proof
# RV32I
core.add_instruction(OpImmInstr())
core.add_instruction(JalrInstr())
core.add_instruction(JalInstr())
core.add_instruction(LuiInstr())
core.add_instruction(AuipcInstr())
core.add_instruction(BeqBneInstr())
core.add_instruction(BltBgeInstr())
core.add_instruction(BltuBgeuInstr())
core.add_instruction(LbLbuInstr())
core.add_instruction(LhLhuInstr())
core.add_instruction(LwInstr())
proof_instance = None
generate_proof = "generate" in sys.argv
all_proofs = [
proof for instruction in core.instructions
for proof in instruction.proofs()
]
if required_proof:
for proof_class in all_proofs:
proof_name = proof_class.__name__.lower()
if proof_name.startswith("proof"):
proof_name = proof_name[len("proof"):]
if required_proof == "ALL" or proof_name == required_proof:
proof_instance = proof_class()
if generate_proof:
proof_instance.run(m, core)
if required_proof is not None and not proof_instance:
raise Exception(f"Unknown proof {required_proof}")
if "generate" in sys.argv:
main_runner(parser, args, m, ports=core.ports())
else:
assert proof_instance, "use --proof proof to run simulation from proof/instruction"
core.simulate(m, clock, proof_instance.simulate())
def cocotb_parser():
parser = main_parser()
p_action = parser._subparsers._actions[1]
p_cocotb = p_action.add_parser("cocotb",
help="generate Verilog from the design and call COCOTB")
p_cocotb.add_argument("-m", "--module",
metavar="MODULE", type=str, required=True,
help="cocotb test module")
p_cocotb.add_argument("-v", "--vcd-file",
metavar="VCD-FILE", type=str, default=None,
help="write execution trace to VCD-FILE")
p_cocotb.add_argument("--clean",
action="store_true", default=False,
help="clean generated files after simulation")
return parser
self.formalData.read(m, self.Addr, self.Din)
return operand
def end_instr(self, m: Module, addr: Statement):
"""Ends the instruction.
Loads the PC and Addr register with the given addr, sets R/W mode
to read, and sets the cycle to 0 at the end of the current cycle.
"""
m.d.comb += self.end_instr_addr.eq(addr)
m.d.comb += self.end_instr_flag.eq(1)
if __name__ == "__main__":
parser = main_parser()
parser.add_argument("--insn")
args = parser.parse_args()
verification: Optional[Verification] = None
if args.insn is not None:
module = importlib.import_module(f"formal.formal_{args.insn}")
formal_class = getattr(module, "Formal")
verification = formal_class()
m = Module()
m.submodules.core = core = Core(verification)
m.domains.ph1 = ph1 = ClockDomain("ph1")
rst = Signal()
ph1clk = ClockSignal("ph1")
m.d.comb += m_imm.c_width.eq(m_imm.Width.IMM16)
return m
# -------------------------------------------------------------------------------------------------
import argparse
from nmigen import cli
if __name__ == "__main__":
from .alsru import ALSRU_4LUT
parser = argparse.ArgumentParser()
parser.add_argument("type", choices=["immediate", "instruction"])
cli.main_parser(parser)
args = parser.parse_args()
if args.type == "immediate":
dut = ImmediateDecoder()
ports = (
dut.i_pc,
dut.i_insn,
dut.o_imm16,
dut.c_exti,
dut.c_table,
dut.c_width,
dut.c_pcrel,
)
def main():
parser = argparse.ArgumentParser(
formatter_class=argparse.ArgumentDefaultsHelpFormatter)
parser.add_argument("--reset-addr",
type=lambda s: int(s, 16),
default="0x00000000",
help="reset vector address")
parser.add_argument("--with-icache",
default=False,
action="store_true",
help="enable the instruction cache")
parser.add_argument("--with-dcache",
default=False,
action="store_true",
help="enable the data cache")
parser.add_argument("--with-muldiv",
default=False,
action="store_true",
help="enable RV32M support")
parser.add_argument("--with-debug",
default=False,
action="store_true",
help="enable the Debug Module")
parser.add_argument("--with-trigger",
default=False,
action="store_true",
help="enable the Trigger Module")
parser.add_argument("--with-rvfi",
default=False,
action="store_true",
help="enable the riscv-formal interface")
icache_group = parser.add_argument_group("icache options")
icache_group.add_argument("--icache-nways",
type=int,
choices=[1, 2],
default=1,
help="number of ways")
icache_group.add_argument("--icache-nlines",
type=int,
default=32,
help="number of lines")
icache_group.add_argument("--icache-nwords",
type=int,
choices=[4, 8, 16],
default=4,
help="number of words in a line")
icache_group.add_argument("--icache-base",
type=lambda s: int(s, 16),
default="0x00000000",
help="base address")
icache_group.add_argument("--icache-limit",
type=lambda s: int(s, 16),
default="0x80000000",
help="limit address")
dcache_group = parser.add_argument_group("dcache options")
dcache_group.add_argument("--dcache-nways",
type=int,
choices=[1, 2],
default=1,
help="number of ways")
dcache_group.add_argument("--dcache-nlines",
type=int,
default=32,
help="number of lines")
dcache_group.add_argument("--dcache-nwords",
type=int,
choices=[4, 8, 16],
default=4,
help="number of words in a line")
dcache_group.add_argument("--dcache-base",
type=lambda s: int(s, 16),
default="0x00000000",
help="base address")
dcache_group.add_argument("--dcache-limit",
type=lambda s: int(s, 16),
default="0x80000000",
help="limit address")
trigger_group = parser.add_argument_group("trigger options")
trigger_group.add_argument("--nb-triggers",
type=int,
default=8,
help="number of triggers")
cli.main_parser(parser)
args = parser.parse_args()
if args.with_debug and not args.with_trigger:
warnings.warn(
"Support for hardware breakpoints requires --with-trigger")
cpu = Minerva(args.reset_addr, args.with_icache, args.icache_nways,
args.icache_nlines, args.icache_nwords, args.icache_base,
args.icache_limit, args.with_dcache, args.dcache_nways,
args.dcache_nlines, args.dcache_nwords, args.dcache_base,
args.dcache_limit, args.with_muldiv, args.with_debug,
args.with_trigger, args.nb_triggers, args.with_rvfi)
ports = [
cpu.external_interrupt, cpu.timer_interrupt, cpu.software_interrupt,
cpu.ibus.ack, cpu.ibus.adr, cpu.ibus.bte, cpu.ibus.cti, cpu.ibus.cyc,
cpu.ibus.dat_r, cpu.ibus.dat_w, cpu.ibus.sel, cpu.ibus.stb,
cpu.ibus.we, cpu.ibus.err, cpu.dbus.ack, cpu.dbus.adr, cpu.dbus.bte,
cpu.dbus.cti, cpu.dbus.cyc, cpu.dbus.dat_r, cpu.dbus.dat_w,
cpu.dbus.sel, cpu.dbus.stb, cpu.dbus.we, cpu.dbus.err
]
if args.with_debug:
ports += [cpu.jtag.tck, cpu.jtag.tdi, cpu.jtag.tdo, cpu.jtag.tms]
if args.with_rvfi:
ports += [
cpu.rvfi.valid, cpu.rvfi.order, cpu.rvfi.insn, cpu.rvfi.trap,
cpu.rvfi.halt, cpu.rvfi.intr, cpu.rvfi.mode, cpu.rvfi.ixl,
cpu.rvfi.rs1_addr, cpu.rvfi.rs2_addr, cpu.rvfi.rs1_rdata,
cpu.rvfi.rs2_rdata, cpu.rvfi.rd_addr, cpu.rvfi.rd_wdata,
cpu.rvfi.pc_rdata, cpu.rvfi.pc_wdata, cpu.rvfi.mem_addr,
cpu.rvfi.mem_rmask, cpu.rvfi.mem_wmask, cpu.rvfi.mem_rdata,
cpu.rvfi.mem_wdata
]
cli.main_runner(parser, args, cpu, name="minerva_cpu", ports=ports)
def __main():
m = Module()
xlen = 32
m.submodules.alu1 = alu1 = ALU(xlen, "A", include_invalid_op=True)
m.submodules.alu2 = alu2 = ALU(xlen, "B")
op = Signal(OpAlu)
en = Signal()
lhs = Signal(32)
rhs = Signal(32)
ports = [op, en, lhs, rhs]
m.d.comb += alu1.op.eq(op)
m.d.comb += alu2.op.eq(op)
m.d.comb += alu1.en.eq(en)
m.d.comb += alu2.en.eq(en)
m.d.comb += alu1.lhs.eq(lhs)
m.d.comb += alu1.rhs.eq(rhs)
m.d.comb += alu2.lhs.eq(rhs)
m.d.comb += alu2.rhs.eq(lhs)
lhs_signed = as_signed(m, lhs)
rhs_signed = as_signed(m, rhs)
with m.If(alu1.en):
with m.If(alu1.op == OpAlu.XOR):
m.d.comb += Assert(alu1.invalid_op == 0)
m.d.comb += Assert(alu1.output == alu2.output)
m.d.comb += Assert(alu1.output == (lhs ^ rhs))
# NOT instruction
with m.If(alu1.rhs == -1):
m.d.comb += Assert(alu1.output == ~alu1.lhs)
with m.Elif(alu1.op == OpAlu.ADD):
m.d.comb += Assert(alu1.invalid_op == 0)
m.d.comb += Assert(alu1.output == alu2.output)
m.d.comb += Assert(alu1.output == (lhs + rhs)[:xlen])
# MV instruction
with m.If(alu1.rhs == 0):
m.d.comb += Assert(alu1.output == alu1.lhs)
with m.Elif(alu1.op == OpAlu.SLT):
m.d.comb += Assert(alu1.invalid_op == 0)
with m.If(lhs_signed < rhs_signed):
m.d.comb += Assert(alu1.output == 1)
with m.Else():
m.d.comb += Assert(alu1.output == 0)
with m.Elif(alu1.op == OpAlu.SLTU):
m.d.comb += Assert(alu1.invalid_op == 0)
m.d.comb += Assert(alu1.output == (lhs < rhs))
# Explicit mention of rhs = 1
with m.If(rhs == 1):
with m.If(alu1.output == 1):
m.d.comb += Assert(lhs == 0)
with m.Elif(alu1.op == OpAlu.AND):
m.d.comb += Assert(alu1.invalid_op == 0)
m.d.comb += Assert(alu1.output == alu2.output)
m.d.comb += Assert(alu1.output == (lhs & rhs))
with m.Elif(alu1.op == OpAlu.OR):
m.d.comb += Assert(alu1.invalid_op == 0)
m.d.comb += Assert(alu1.output == alu2.output)
m.d.comb += Assert(alu1.output == (lhs | rhs))
with m.Else():
m.d.comb += Assert(alu1.invalid_op)
with m.Else():
m.d.comb += Assert(alu1.output == 0)
m.d.comb += Assert(alu2.output == 0)
parser = main_parser()
args = parser.parse_args()
main_runner(parser, args, m, ports=ports + alu1.ports() + alu2.ports())
