def elaborate(self, platform):
m = Module()
# This state machine recognizes sequences of 6 bits and drops the 7th
# bit. The fsm implements a counter in a series of several states.
# This is intentional to help absolutely minimize the levels of logic
# used.
m.submodules.stuff = stuff = DomainRenamer({'sync': 'usb_io'
})(FSM(reset_state="D0"))
drop_bit = Signal(1)
for i in range(6):
stuff.act(
"D%d" % i,
If(
self.i_valid,
If(
self.i_data,
# Receiving '1' increments the bitstuff counter.
NextState("D%d" % (i + 1))).Else(
# Receiving '0' resets the bitstuff counter.
NextState("D0"))),
)
stuff.act(
"D6",
If(
self.i_valid,
drop_bit.eq(1),
# Reset the bitstuff counter, drop the data.
NextState("D0")))
m.d.usb_io += [
self.o_data.eq(self.i_data),
self.o_stall.eq(drop_bit | ~self.i_valid),
self.o_error.eq(drop_bit & self.i_data & self.i_valid),
]
return m
def elaborate(self, platform: Platform) -> Module:
m = Module()
with m.FSM(reset="IDLE") as self.fsm:
with m.State("IDLE"):
self.Idle(m)
with m.State("START"):
self.Start(m)
with m.State("DATA"):
self.Data(m)
with m.State("STOP"):
self.Stop(m)
with m.State("DONE"):
self.Done(m)
# with m.State("ERROR"):
# self.Error(m)
return m
def elaborate(self, platform):
m = Module()
# PLL update
# Reset the PLLs if asked to.
with m.If(self.smode1_prst):
m.d.sync += [
self.r_hclk.eq(0),
self.r_vclk.eq(0),
self.r_hfp.eq(0),
self.r_hsync.eq(self.synch1_hfp),
self.r_hbp.eq(self.synch1_hfp + self.synch1_hs),
self.r_hact.eq(self.synch1_hfp + self.synch1_hs + self.synch1_hbp),
self.r_hend.eq(720),
self.r_vfp.eq(0),
self.r_vsync.eq(self.syncv_vfp + self.syncv_vfpe),
self.r_vbp.eq(self.syncv_vfp + self.syncv_vfpe + self.syncv_vs),
self.r_vact.eq(self.syncv_vfp + self.syncv_vfpe + self.syncv_vs + self.syncv_vbp + self.syncv_vbpe),
self.r_vend.eq(self.syncv_vfp + self.syncv_vfpe + self.syncv_vs + self.syncv_vbp + self.syncv_vbpe + self.syncv_vdp)
]
# Otherwise, update the counters when the PLLs are enabled.
with m.Elif(self.i_pixclk & self.smode1_sint):
m.d.sync += self.r_hclk.eq(self.r_hclk + 1)
with m.If(self.r_hclk == (self.r_hend - 1)):
m.d.sync += self.r_hclk.eq(0)
m.d.sync += self.r_vclk.eq(self.r_vclk + 1)
with m.If(self.r_vclk == (self.r_vend - 1)):
m.d.sync += self.r_vclk.eq(0)
m.d.sync += [
self.d_hfp.eq(self.r_hclk < self.r_hsync),
self.d_hsync.eq((self.r_hclk >= self.r_hsync) & (self.r_hclk < self.r_hbp)),
self.d_hbp.eq((self.r_hclk >= self.r_hbp) & (self.r_hclk < self.r_hact)),
self.d_hblank.eq(self.r_hclk < self.r_hact),
self.d_vfp.eq(self.r_vclk < self.r_vsync),
self.d_vsync.eq((self.r_vclk >= self.r_vsync) & (self.r_vclk < self.r_vbp)),
self.d_vbp.eq((self.r_vclk >= self.r_vbp) & (self.r_vclk < self.r_vact)),
self.d_vblank.eq(self.r_vclk < self.r_vact)
]
return m
def formal(cls) -> Tuple[Module, List[Signal]]:
"""Formal verification for my module."""
m = Module()
m.submodules.my_class = my_class = cls()
sync_clk = ClockSignal("sync")
sync_rst = ResetSignal("sync")
# Make sure that the output is always the same as the input
m.d.comb += Assert(my_class.my_input == my_class.my_output)
# Cover the case where the output is 1.
m.d.comb += Cover(my_class.my_output == 1)
# Make sure the clock is clocking
m.d.comb += Assume(sync_clk == ~Past(sync_clk))
# Include this only if you don't want to test resets
m.d.comb += Assume(~sync_rst)
# Ensure sync's clock and reset signals are manipulable.
return m, [sync_clk, sync_rst, my_class.my_input]
def elaborate(self, platform):
m = Module()
# Generate our domain clocks/resets.
m.submodules.car = platform.clock_domain_generator()
# Create our USB device interface...
ulpi = platform.request("target_phy")
m.submodules.usb = usb = USBDevice(bus=ulpi)
# Add our standard control endpoint to the device.
descriptors = self.create_descriptors()
control_ep = usb.add_standard_control_endpoint(descriptors)
# Add our custom request handlers.
control_ep.add_request_handler(LEDRequestHandler())
# Connect our device by default.
m.d.comb += usb.connect.eq(1)
return m
def elaborate(self, platform):
m = Module()
# Generate our domain clocks/resets.
m.submodules.car = platform.clock_domain_generator()
# Create the 32-bit counter we'll be using as our status signal.
counter = Signal(32)
m.d.usb += counter.eq(counter + 1)
# Create our USB device interface...
ulpi = platform.request(platform.default_usb_connection)
m.submodules.usb = usb = USBDevice(bus=ulpi)
# Add our standard control endpoint to the device.
descriptors = self.create_descriptors()
usb.add_standard_control_endpoint(descriptors)
# Create an interrupt endpoint which will carry the value of our counter to the host
# each time our interrupt EP is polled.
status_ep = USBSignalInEndpoint(width=32, endpoint_number=1, endianness="big")
usb.add_endpoint(status_ep)
m.d.comb += status_ep.signal.eq(counter)
# Connect our device as a high speed device by default.
m.d.comb += [
usb.connect .eq(1),
usb.full_speed_only .eq(1 if os.getenv('LUNA_FULL_ONLY') else 0),
]
# ... and for now, attach our LEDs to our most recent control request.
m.d.comb += [
platform.request('led', 0).eq(usb.tx_activity_led),
platform.request('led', 1).eq(usb.rx_activity_led),
platform.request('led', 2).eq(usb.suspended),
]
return m
def elaborate(self, platform):
m = Module()
# Create our domains...
m.domains.usb = ClockDomain()
m.domains.usb_io = ClockDomain()
m.domains.fast = ClockDomain()
# ... and create our 12 MHz USB clock.
clk12 = Signal()
m.submodules.pll = Instance(
"SB_PLL40_CORE",
i_REFERENCECLK=ClockSignal("sync"),
i_RESETB=Const(1),
i_BYPASS=Const(0),
o_PLLOUTCORE=clk12,
# Create a 24 MHz PLL clock...
p_FEEDBACK_PATH="SIMPLE",
p_DIVR=0,
p_DIVF=15,
p_DIVQ=5,
p_FILTER_RANGE=4,
# ... and divide it by half to get 12 MHz.
p_PLLOUT_SELECT="GENCLK_HALF")
# Relax the 12MHz clock down to 12MHz.
platform.add_clock_constraint(clk12, 12e6)
# We'll use our 48MHz clock for everything _except_ the usb domain...
m.d.comb += [
ClockSignal("usb").eq(clk12),
ClockSignal("usb_io").eq(ClockSignal("sync")),
ClockSignal("fast").eq(ClockSignal("sync"))
]
return m
def elaborate(self, platform):
m = Module()
self.invert = ControlSignal(
reset=is_signal_inverted(platform, self.pad))
oserdes = m.submodules.oserdes = _OSerdes(data_width=self.bit_width,
tristate_width=1,
data_rate_oq="ddr",
serdes_mode="master",
data_rate_tq="buf")
m.d.comb += oserdes.oce.eq(1)
m.d.comb += oserdes.clk.eq(ClockSignal(self.ddr_domain))
m.d.comb += oserdes.clkdiv.eq(ClockSignal())
m.d.comb += oserdes.rst.eq(ResetSignal())
m.d.comb += Cat(
oserdes.d[i]
for i in (range(1, 9) if self.msb_first else reversed(range(1, 9))
)).eq(self.value ^ self.invert)
m.d.comb += self.pad.eq(oserdes.oq)
return m
def peripherals_connect_hook(platform, top_fragment: Fragment, sames):
if platform.peripherals:
m = Module()
platform.ps7.fck_domain(domain_name="axi_lite", requested_frequency=100e6)
if not hasattr(platform, "is_sim"): # we are not in a simulation platform
axi_full_port: AxiEndpoint = platform.ps7.get_axi_gp_master(ClockSignal("axi_lite"))
axi_lite_bridge = m.submodules.axi_lite_bridge = DomainRenamer("axi_lite")(
AxiFullToLiteBridge(axi_full_port)
)
axi_lite_master = axi_lite_bridge.lite_master
else: # we are in a simulation platform
axi_lite_master = AxiEndpoint(addr_bits=32, data_bits=32, master=True, lite=True)
self.axi_lite_master = axi_lite_master
interconnect = m.submodules.interconnect = DomainRenamer("axi_lite")(
AxiInterconnect(axi_lite_master)
)
for peripheral in platform.peripherals:
controller = DomainRenamer("axi_lite")(AxiLitePeripheralConnector(peripheral))
m.d.comb += interconnect.get_port().connect_slave(controller.axi)
m.submodules += controller
platform.to_inject_subfragments.append((m, "axi_lite"))
def formal(cls) -> Tuple[Module, List[Signal]]:
m = Module()
ph = ClockDomain("ph")
clk = ClockSignal("ph")
m.domains += ph
m.d.sync += clk.eq(~clk)
s = IC_reg32_with_mux(clk="ph", N=2, faster=True)
m.submodules += s
sync_clk = ClockSignal("sync")
sync_rst = ResetSignal("sync")
with m.If(Rose(clk)):
with m.Switch(~Past(s.n_sel)):
with m.Case(0b11):
m.d.comb += Assert(0)
with m.Case(0b01):
m.d.comb += Assert(s.q == Past(s.d[0]))
with m.Case(0b10):
m.d.comb += Assert(s.q == Past(s.d[1]))
with m.Default():
m.d.comb += Assert(s.q == Past(s.q))
# Make sure the clock is clocking
m.d.comb += Assume(sync_clk == ~Past(sync_clk))
# Don't want to test what happens when we reset.
m.d.comb += Assume(~sync_rst)
m.d.comb += Assume(~ResetSignal("ph"))
m.d.comb += Assume(s.n_sel != 0)
return m, [sync_clk, sync_rst, s.d[0], s.d[1], s.n_sel, s.q]
def elaborate(self, platform):
m = Module()
led0 = platform.request("led", 0)
led1 = platform.request("led", 1)
m.submodules.rdport = rdport = self.mem.read_port()
with m.If(rdport.data == 255):
m.d.comb += led0.eq(0)
with m.Else():
m.d.comb += led0.eq(1)
timer = Signal(range(round(100E6)))
with m.If(timer > 100):
m.d.comb += rdport.addr.eq(100)
with m.Else():
m.d.comb += rdport.addr.eq(0)
m.d.sync += timer.eq(timer + 1)
m.d.comb += led1.o.eq(timer[-1])
return m
def elaborate(self, platform):
m = Module()
m.submodules.ila = self.ila
transaction_start = Rose(self.spi.cs)
# Connect up our SPI transciever to our public interface.
interface = SPIDeviceInterface(
word_size=self.bits_per_word,
clock_polarity=self.clock_polarity,
clock_phase=self.clock_phase
)
m.submodules.spi = interface
m.d.comb += [
interface.spi .connect(self.spi),
# Always output the captured sample.
interface.word_out .eq(self.ila.captured_sample)
]
# Count where we are in the current transmission.
current_sample_number = Signal(range(0, self.ila.sample_depth))
# Our first piece of data is latched in when the transaction
# starts, so we'll move on to sample #1.
with m.If(self.spi.cs):
with m.If(transaction_start):
m.d.sync += current_sample_number.eq(1)
# From then on, we'll move to the next sample whenever we're finished
# scanning out a word (and thus our current samples are latched in).
with m.Elif(interface.word_complete):
m.d.sync += current_sample_number.eq(current_sample_number + 1)
# Whenever CS is low, we should be providing the very first sample,
# so reset our sample counter to 0.
with m.Else():
m.d.sync += current_sample_number.eq(0)
# Ensure our ILA module outputs the right sample.
m.d.sync += [
self.ila.captured_sample_number .eq(current_sample_number)
]
return m
def handle_csrs(self, m: Module):
"""Adds the SYSTEM (CSR opcodes) logic to the given module.
Some points of interest:
* Attempts to write a read-only register
result in an illegal instruction exception.
* Attempts to access a CSR that doesn't exist
result in an illegal instruction exception.
* Attempts to write read-only bits to a read/write CSR
are ignored.
Because we're building this in hardware, which is
expensive, we're not implementing any CSRs that aren't
strictly necessary. The documentation for the misa, mvendorid,
marchid, and mimpid registers state that they can return zero if
unimplemented. This implies that unimplemented CSRs still
exist.
The mhartid, because we only have one HART, can just return zero.
"""
with m.Switch(self._funct3):
with m.Case(SystemFunc.CSRRW):
self.handle_CSRRW(m)
with m.Case(SystemFunc.CSRRWI):
self.handle_CSRRWI(m)
with m.Case(SystemFunc.CSRRS):
self.handle_CSRRS(m)
with m.Case(SystemFunc.CSRRSI):
self.handle_CSRRSI(m)
with m.Case(SystemFunc.CSRRC):
self.handle_CSRRC(m)
with m.Case(SystemFunc.CSRRCI):
self.handle_CSRRCI(m)
with m.Default():
self.handle_illegal_instr(m)
def elaborate(self, platform): m = Module() # Assuming a frame is composed of 2048 INCLK clocks. count = Signal(range(2048)) count_next = Signal(range(2048)) with m.If(self.enable): m.d.comb += count_next.eq(count + 1) with m.Else(): m.d.comb += count_next.eq(0) m.d.sync += [ count.eq(count_next), ] m.d.comb += [ self.frame_sync.eq((count == 2047) | (count == 0)), ] slot = Signal(range(32)) m.d.comb += [ self.f_bit.eq(count < 8), self.bit.eq((count >> 3) & 7), self.channel.eq((count & 7) >> 1), slot.eq(count >> 6), ] m.d.comb += [ self.slot_valid_t1.eq((slot & 3) != 0), self.slot_t1.eq((slot & 3)) ] with m.If(self.slot_valid_t1): m.d.comb += self.slot_t1.eq(((slot >> 2) * 3) + ((slot & 3) - 1)), with m.Else(): m.d.comb += self.slot_t1.eq(0) m.d.comb += [ self.slot_valid_e1.eq(1), self.slot_e1.eq(slot), ] return m
def elaborate(self, platform):
m = Module()
if platform is not None:
# platform.default_clk_frequency is in Hz
coeff = self._calc_freq_coefficients(
platform.default_clk_frequency / 1_000_000, self.freq_out)
# clk_pin = platform.request(platform.default_clk)
lock = Signal()
pll = Instance(
"SB_PLL40_CORE",
p_FEEDBACK_PATH='SIMPLE',
p_DIVR=coeff.divr,
p_DIVF=coeff.divf,
p_DIVQ=coeff.divq,
p_FILTER_RANGE=0b001,
p_DELAY_ADJUSTMENT_MODE_FEEDBACK='FIXED',
p_FDA_FEEDBACK=0b0000,
p_DELAY_ADJUSTMENT_MODE_RELATIVE='FIXED',
p_FDA_RELATIVE=0b0000,
p_SHIFTREG_DIV_MODE=0b00,
p_PLLOUT_SELECT='GENCLK',
p_ENABLE_ICEGATE=0b0,
i_REFERENCECLK=ClockSignal(),
o_PLLOUTCORE=ClockSignal(self.domain_name),
i_RESETB=ResetSignal(),
i_BYPASS=Const(0),
o_LOCK=lock,
)
rs = ResetSynchronizer(~lock, domain=self.domain_name)
m.submodules += [pll, rs]
m.domains += ClockDomain(self.domain_name)
return m
def elaborate(self, platform):
m = Module()
m.submodules.high = ir.Instance("VHI", o_Z=self._high)
m.submodules.low = ir.Instance("VLO", o_Z=self._low)
i2c1_kwargs = {}
for k in self.primary_i2c.kwargs:
i2c1_kwargs[k.format(1)] = self.primary_i2c.kwargs[k]
for k in self.secondary_i2c.kwargs:
i2c1_kwargs[k.format(2)] = self.secondary_i2c.kwargs[k]
m.submodules.efb = ir.Instance("EFB",
i_WBCLKI=self._clock,
p_EFB_WB_CLK_FREQ=self._freq,
p_EFB_I2C1="ENABLED",
p_EFB_I2C2="ENABLED",
p_GSR="ENABLED",
p_UFM_INIT_FILE_FORMAT="HEX",
p_UFM_INIT_FILE_NAME="NONE",
p_UFM_INIT_ALL_ZEROS="ENABLED",
p_UFM_INIT_START_PAGE=2038,
p_UFM_INIT_PAGES=8,
p_DEV_DENSITY="7000L",
p_EFB_UFM="ENABLED",
p_I2C1_WAKEUP="DISABLED",
p_I2C1_GEN_CALL="DISABLED",
p_I2C1_CLK_DIVIDER=8,
p_I2C1_BUS_PERF="100kHz",
p_I2C1_SLAVE_ADDR="0b1000001",
p_I2C1_ADDRESSING="7BIT",
p_I2C2_WAKEUP="DISABLED",
p_I2C2_GEN_CALL="DISABLED",
p_I2C2_CLK_DIVIDER=8,
p_I2C2_BUS_PERF="100kHz",
p_I2C2_SLAVE_ADDR="0b1000010",
p_I2C2_ADDRESSING="7BIT",
**i2c1_kwargs,
**self._kwargs)
print("EFB instance!")
return m
def formal(cls) -> Tuple[Module, List[Signal]]:
"""Formal verification for the active high 74182 chip.
Used with an active high 74181.
"""
m = Module()
m.submodules.clu = clu = IC_74182_active_high()
m.submodules.alu = alu = IC_74181()
add_mode = (alu.s == 9) & (alu.m == 0)
m.d.comb += Assume(add_mode)
m.d.comb += [
clu.x[0].eq(alu.x),
clu.y[0].eq(alu.y),
clu.x[1:].eq(0),
clu.y[1:].eq(0),
clu.n_carryin.eq(alu.n_carryin),
]
m.d.comb += Assert(clu.n_carryout_x == alu.n_carryout)
return m, clu.ports() + alu.ports()
def elaborate(self, platform):
m = Module()
m.submodules += self.ila
# Clock divider / counter.
m.d.sync += self.counter.eq(self.counter + 1)
# Set our ILA to trigger each time the counter is at a random value.
# This shows off our example a bit better than counting at zero.
m.d.comb += self.ila.trigger.eq(self.counter == 7)
# Grab our I/O connectors.
leds = [platform.request("led", i, dir="o") for i in range(0, 6)]
spi_bus = synchronize(m, platform.request('debug_spi'))
# Attach the LEDs and User I/O to the MSBs of our counter.
m.d.comb += Cat(leds).eq(self.counter[-7:-1])
# Connect our ILA up to our board's aux SPI.
m.d.comb += self.ila.spi.connect(spi_bus)
# Return our elaborated module.
return m
def elaborate(self, platform: Platform) -> Module:
m = Module()
m.submodules.alu = self.alu = ALU()
"""Fetch the opcode, common for all instr"""
m.d.sync += self.opcode.eq(Mux(self.cycle == 1, self.dout, self.opcode))
with m.Switch(Mux(self.cycle == 1, self.dout, self.opcode)):
for i in implemented.implemented:
with m.Case(i.opcode):
i.synth(self, m)
with m.Default():
m.d.comb += core.alu.oper.eq(Operation.NOP)
m.d.sync += [
core.reg.PC.eq(add16(core.reg.PC, 1)),
core.enable.eq(1),
core.addr.eq(add16(core.reg.PC, 1)),
core.RWB.eq(1),
core.cycle.eq(1),
]
if self.verification is not None:
self.verify(m)
with m.If(Initial()):
m.d.sync += [
self.reg.A.eq(AnyConst(8)),
self.reg.X.eq(AnyConst(8)),
self.reg.Y.eq(AnyConst(8)),
self.reg.SP.eq(AnyConst(16)),
self.reg.PC.eq(AnyConst(16)),
]
m.d.sync += [
self.reg.PSW.N.eq(AnyConst(1)),
self.reg.PSW.V.eq(AnyConst(1)),
self.reg.PSW.P.eq(AnyConst(1)),
self.reg.PSW.B.eq(AnyConst(1)),
self.reg.PSW.H.eq(AnyConst(1)),
self.reg.PSW.I.eq(AnyConst(1)),
self.reg.PSW.Z.eq(AnyConst(1)),
self.reg.PSW.C.eq(AnyConst(1)),
]
return m
def elaborate(self, platform):
m = Module()
ones = DigitPattern()
tens = DigitPattern()
drv = SevenSegDriver(
clk_freq=self.clk_freq,
min_refresh_freq=self.min_refresh_freq,
pwm_width=self.pwm_width,
)
m.submodules.ones = ones
m.submodules.tens = tens
m.submodules.drv = drv
m.d.comb += [
ones.digit_in.eq(self.i_data[:4]),
tens.digit_in.eq(self.i_data[4:]),
drv.pwm.eq(self.i_pwm),
drv.segment_patterns[0].eq(ones.segments_out),
drv.segment_patterns[1].eq(tens.segments_out),
self.o_seg7.eq(drv.seg7),
]
oo_seg7 = Signal(8)
m.d.comb += oo_seg7.eq(self.o_seg7)
return m
def elaborate(self, platform):
m = Module()
# create domains for the producer and consumer
m.domains.producer = ClockDomain()
m.domains.consumer = ClockDomain()
# attach submodules
m.submodules.producer = producer = self.producer
m.submodules.consumer = consumer = self.consumer
m.submodules.fifo = fifo = self.fifo
# producer <> fifo
m.d.comb += producer.w_rdy_i.eq(fifo.w_rdy)
m.d.comb += fifo.w_en.eq(producer.w_en_o)
m.d.comb += fifo.w_data.eq(producer.w_data_o)
# consumer <> fifo
m.d.comb += consumer.r_rdy_i.eq(fifo.r_rdy)
m.d.comb += consumer.r_data_i.eq(fifo.r_data)
m.d.comb += fifo.r_en.eq(consumer.r_en_o)
return m
def elaborate(self, platform):
m = Module()
idelay = m.submodules.idelay = _IDelay(delay_src="iDataIn",
signal_pattern="data",
cinvctrl_sel=False,
high_performance_mode=True,
refclk_frequency=200.0,
pipe_sel=False,
idelay_type="var_load",
idelay_value=0)
m.d.comb += idelay.c.eq(
ClockSignal()
) # this is really the clock to which the control inputs are syncronous!
m.d.comb += idelay.ld.eq(self.load)
m.d.comb += idelay.ldpipeen.eq(0)
m.d.comb += idelay.ce.eq(0)
m.d.comb += idelay.inc.eq(0)
m.d.comb += idelay.cntvalue.in_.eq(self.delay)
m.d.comb += idelay.idatain.eq(self.pin)
m.d.comb += self.output.eq(idelay.data.out)
return m
def elaborate(self, platform):
m = Module()
# Build our multiplexing logic.
is_first_entry = True
for bus in self.multiplexed_busses:
conditional = m.If if is_first_entry else m.Elif
is_first_entry = False
# Connect SDO only if this line is selected
with conditional(bus.cs):
m.d.comb += self.shared_lines.sdo.eq(bus.sdo)
# Connect each of our shared inputs.
for bus in self.multiplexed_busses:
m.d.comb += [
bus.sck .eq(self.shared_lines.sck),
bus.sdi .eq(self.shared_lines.sdi)
]
return m
def elaborate(self, platform):
m = Module()
# Get the ECP5 block that's responsible for driving the MCLK pin,
# and drive it using our SCK line.
user_mclk = Instance('USRMCLK', i_USRMCLKI=self.sck, i_USRMCLKTS=0)
m.submodules += user_mclk
# Connect up each of our other signals.
m.d.comb += [
self.bus.sdi .eq(self.sdi),
self.sdo .eq(self.bus.sdo)
]
if self.use_cs:
m.d.comb += [
self.bus.cs.o.eq(self.cs),
self.bus.cs.oe.eq(1)
]
else:
m.d.comb += self.bus.cs.oe.eq(0)
return m
def process(self, m: Module):
# Decode instruction
m.d.comb += [
self._opcode.eq(self.state._instr[:7]),
self._rs1.eq(self.state._instr[15:20]),
self._rs2.eq(self.state._instr[20:25]),
self._rd.eq(self.state._instr[7:12]),
self._funct3.eq(self.state._instr[12:15]),
self._funct7.eq(self.state._instr[25:]),
self._alu_func[:3].eq(self._funct3),
self._alu_func[3].eq(self._funct7[5]),
self._funct12.eq(self.state._instr[20:]),
]
if (self.chips):
self.decode_imm_chips(m)
else:
self.decode_imm(m)
# We don't evaluate the instruction for badness until after it's loaded.
ph2r_clk = ClockSignal("ph2r")
m.d.comb += self.bad_instr.eq(ph2r_clk & (
(self.state._instr[:16] == 0) |
(self.state._instr == 0xFFFFFFFF)))
with m.Switch(self._funct3):
with m.Case(BranchCond.EQ):
m.d.comb += self.branch_cond.eq(self.state._stored_alu_eq == 1)
with m.Case(BranchCond.NE):
m.d.comb += self.branch_cond.eq(self.state._stored_alu_eq == 0)
with m.Case(BranchCond.LT):
m.d.comb += self.branch_cond.eq(self.state._stored_alu_lt == 1)
with m.Case(BranchCond.GE):
m.d.comb += self.branch_cond.eq(self.state._stored_alu_lt == 0)
with m.Case(BranchCond.LTU):
m.d.comb += self.branch_cond.eq(
self.state._stored_alu_ltu == 1)
with m.Case(BranchCond.GEU):
m.d.comb += self.branch_cond.eq(
self.state._stored_alu_ltu == 0)
def elaborate(self, platform):
m = Module()
m.submodules += self.ila
# Generate our domain clocks/resets.
m.submodules.car = platform.clock_domain_generator()
# Clock divider / counter.
m.d.usb += self.counter.eq(self.counter + 1)
# Say "hello world" constantly over our ILA...
letters = Array(ord(i) for i in "Hello, world! \r\n")
current_letter = Signal(range(0, len(letters)))
m.d.sync += current_letter.eq(current_letter + 1)
m.d.comb += self.hello.eq(letters[current_letter])
# Set our ILA to trigger each time the counter is at a random value.
# This shows off our example a bit better than counting at zero.
m.d.comb += self.ila.trigger.eq(self.counter == 227)
# Return our elaborated module.
return m
def elaborate(self, platform): m = Module() bus = self.bus # Configure outputs m.d.comb += [ # Transmit data. bus.ser.eq(self.data), # Timing source of transmit line interface. bus.serclk.o.eq(self.base_rate_clock), bus.serclk.oe.eq(self.enable), # Transmit frame sync pulse. bus.sync.o.eq(self.start_of_frame), bus.sync.oe.eq(self.enable), # Transmit multiframe sync pulse. bus.msync.o.eq(self.start_of_multiframe), bus.msync.oe.eq(self.enable), ] return m
def elaborate(self, platform):
m = Module()
m.submodules += [self.sine_dac, self.cosine_dac]
m.submodules += [self.nco, self.picorv32]
m.d.comb += [
# self.dds.phase_step.eq(DDS.calculate_phase_step(clk_frequency=50e6, frequency=32_768)),
self.sine_dac.waveform.eq(self.nco.sin),
self.cosine_dac.waveform.eq(self.nco.cos),
self.nco.enable.eq(self.nco_ctrl.enable),
]
# m.d.sync += self.uart.tx_rdy.eq(0)
if platform is not None:
platform.add_resources([Resource("dac", 0, Pins("12 13", dir="o", conn=("gpio", 0)))])
dac_pins = platform.request("dac")
m.d.comb += dac_pins.o.eq(Cat(self.sine_dac.out, self.cosine_dac.out))
led_pin = platform.request("led")
m.d.comb += led_pin.o.eq(self.led)
return m
def elaborate(self, platform):
""" Generate the Blinky tester. """
m = Module()
# Grab our I/O connectors.
leds = [
platform.request_optional("led", i, dir="o") for i in range(0, 6)
]
user_io = [
platform.request_optional("user_io", i, dir="o")
for i in range(0, 4)
]
# Clock divider / counter.
counter = Signal(28)
m.d.sync += counter.eq(counter + 1)
# Attach the LEDs and User I/O to the MSBs of our counter.
m.d.comb += Cat(leds).eq(counter[-7:-1])
m.d.comb += Cat(user_io).eq(counter[7:21])
# Return our elaborated module.
return m
def elaborate(self, platform):
m = Module()
# Generate our domain clocks/resets.
m.submodules.car = platform.clock_domain_generator()
# Create our USB-to-serial converter.
ulpi = platform.request(platform.default_usb_connection)
m.submodules.usb_serial = usb_serial = \
USBSerialDevice(bus=ulpi, idVendor=0x16d0, idProduct=0x0f3b)
m.d.comb += [
# Place the streams into a loopback configuration...
usb_serial.tx.payload .eq(usb_serial.rx.payload),
usb_serial.tx.valid .eq(usb_serial.rx.valid),
usb_serial.tx.first .eq(usb_serial.rx.first),
usb_serial.tx.last .eq(usb_serial.rx.last),
usb_serial.rx.ready .eq(usb_serial.tx.ready),
# ... and always connect by default.
usb_serial.connect .eq(1)
]
return m
