def build(TheFirmware, mem_size=4096, sim=False, detail=False): # for programming from a firmware file if detail: print("Testing Spork") # TODO abstract this plaform set platform = TinyFPGABXPlatform() # FTDI on the tinybx platform.add_resources([ UARTResource(0, rx="A8", tx="B8", attrs=Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1)), Resource("reset_pin", 0, Pins("A9", dir="i"), Attrs(IO_STANDARD="SB_LVCMOS")), # *ButtonResources(pins="10", invert=True, attrs=Attrs(IO_STANDARD="SB_LVCMOS")), *LEDResources("blinky", pins="J1 H2 H9 D9", attrs=Attrs(IO_STANDARD="SB_LVCMOS")), ]) # Spork it up spork = TestSpork(platform, uart_speed=115200, mem_size=mem_size, sim=sim) # Build the firmware spork.build() if detail: print(spork.cpu.map.show()) f = TheFirmware(spork.cpu.map, start_window=mem_size) spork.fw = f if detail: f.show() # Sporkify it ! code = f.code() spork.cpu.firmware(code) if detail: print(f.hex()) spork.hex_blob = f.hex() return spork
m.d.comb += ply1_up.eq (platform.request ("pin_21")) m.d.comb += ply1_down.eq (platform.request ("pin_22")) m.d.comb += ply2_up.eq (platform.request ("pin_23")) m.d.comb += ply2_down.eq (platform.request ("pin_24")) return m #-------------------------------------------------------------- # Main with -> python3 game_pong.py #-------------------------------------------------------------- if __name__ == "__main__": # Create platform board. print ("\nGenerating 'game-pong' bitstream.") print ("1 - TinyFPGA-BX platform created.") platform = TinyFPGABXPlatform() # Define new pins to platform. print ('2 - Define new pins to platform.') platform.add_resources ([ # VGA Signals. Resource("pin_9", 0, Pins("E1", dir="o")), Resource("pin_10", 0, Pins("G2", dir="o")), Resource("pin_11", 0, Pins("H1", dir="o")), Resource("pin_12", 0, Pins("J1", dir="o")), Resource("pin_13", 0, Pins("H2", dir="o")), # LED test Resource("pin_14", 0, Pins("H9", dir="o")), # Audio signals.
from nmigen import * from minerva.core import Minerva from nmigen_boards.tinyfpga_bx import TinyFPGABXPlatform class minerva_core(Elaboratable): def elaborate(self, platform): clk16 = platform.request("clk16", 0) m = Module() m.domains.sync = ClockDomain() m.d.comb += ClockSignal().eq(clk16.i) cpu = Minerva(with_icache=False, with_dcache=False, with_muldiv=False) m.submodules.minerva = cpu return m if __name__ == "__main__": platform = TinyFPGABXPlatform() platform.build(minerva_core(),build_dir='minerva')
m.d.comb += self.left_ch.eq(tick_sound) m.d.comb += self.right_ch.eq(tick_sound) # New tick sound. m.d.sync += divcounter.eq(divcounter + 1) return m if __name__ == "__main__": print("\nPrueba del módulo de sonido en una TinyFPGA.\n") print("Conecta pines 19 y 20 de la TinyFPGA a los altavoces\n") print("derecho e izquierdo.\n") # Se elige la plataforma donde sintetizar el módulo. platform = TinyFPGABXPlatform() # Se conectan los pines (led2 al pin 14). platform.add_resources([ Resource("led2", 0, Pins("H9", dir="o")), Resource("pin_19", 0, Pins("B8", dir="o")), Resource("pin_20", 0, Pins("A8", dir="o")), ]) module = soundCard(platform) # Se elige un tono y el canal para probar. module.sound = SOUNDS.goal module.channel = CHANNEL.right platform.build(module, do_program=False)
from nmigen import * from boneless.gateware.core_fsm import BonelessFSMTestbench from nmigen_boards.tinyfpga_bx import TinyFPGABXPlatform class boneless_core(Elaboratable): def elaborate(self, platform): clk16 = platform.request("clk16", 0) user_led = platform.request("user_led", 0) m = Module() m.domains.sync = ClockDomain() m.d.comb += ClockSignal().eq(clk16.i) cpu = BonelessFSMTestbench(has_pins=True) m.d.sync += user_led.eq(cpu.pins[0]) m.submodules.cpu = cpu return m if __name__ == "__main__": platform = TinyFPGABXPlatform() platform.build(boneless_core(), do_program=True, build_dir='boneless')
dac_pins = platform.request("dac") m.d.comb += dac_pins.o.eq(Cat(self.sine_dac.out, self.cosine_dac.out)) led_pin = platform.request("led") m.d.comb += led_pin.o.eq(self.led) return m if __name__ == "__main__": from nmigen_boards.tinyfpga_bx import TinyFPGABXPlatform import sys if len(sys.argv) != 2: print("top.py <program|simulate>") elif sys.argv[1] == "build": platform = TinyFPGABXPlatform() products = platform.build(Top(), do_program=False) elif sys.argv[1] == "program": platform = TinyFPGABXPlatform() products = platform.build(Top(), do_program=True) elif sys.argv[1] == "generate": from nmigen.back import verilog top = Top() print(verilog.convert(top, name="top", ports=(top.led,))) # elif sys.argv[1] == "simulate": # from nmigen.sim import Simulator, Tick # dut = Top() # sim = Simulator(dut, engine="cxxsim") # sim.add_clock(1 / 16e6, domain="sync") # sim.add_clock(1 / 50e6, domain="pll")
# If the design does not create a "sync" clock domain, it is created by the nMigen build system # using the platform default clock (and default reset, if any). from nmigen import Elaboratable, Module, Signal from nmigen.build.dsl import Resource, Pins from nmigen_boards.tinyfpga_bx import TinyFPGABXPlatform from ice40_pll import ICE40_PLL class Blinky(Elaboratable): def elaborate(self, platform): timer = Signal(23) m = Module() m.d.sync += timer.eq(timer + 1) if platform is not None: led = platform.request("led", 0) m.d.comb += led.o.eq(timer[-1]) return m if __name__ == "__main__": platform = TinyFPGABXPlatform() products = platform.build(Blinky(), do_program=True)