def __init__(self):
family = PyFamily()
# Data registers
self.data = [(gen_register_mode(family, Data)())
for i in range(num_inputs)]
# Bit Registers
self.bit0 = gen_register_mode(family, Bit)()
self.bit1 = gen_register_mode(family, Bit)()
self.bit2 = gen_register_mode(family, Bit)()
def __init__(self, peak_generator):
pe = peak_generator(PyFamily())
assert issubclass(pe, peak.Peak)
self._model = pe()
#Lassen's name for the ISA is 'inst', so this is hardcoded
self.__instr_name = 'inst'
self.__instr_type = strip_modifiers(pe.input_t.field_dict['inst'])
self.__inputs = OrderedDict(pe.input_t.field_dict)
del self.__inputs['inst']
self.__outputs = OrderedDict(pe.output_t.field_dict)
circuit = peak_generator(MagmaFamily())
self.__asm = Assembler(self.__instr_type)
instr_magma_type = type(circuit.interface.ports[self.__instr_name])
self.__circuit = peak.wrap_with_disassembler(
circuit, self.__asm.disassemble, self.__asm.width,
HashableDict(self.__asm.layout), instr_magma_type)
data_gate(self.__circuit)
def test_wrapped_PE():
class HashableDict(dict):
def __hash__(self):
return hash(tuple(sorted(self.keys())))
pe = PE_fc(PyFamily())
#Lassen's name for the ISA is 'inst', so this is hardcoded
__instr_name = 'inst'
__instr_type = pe.input_t.field_dict['inst']
__inputs = OrderedDict(pe.input_t.field_dict)
__inputs['inst']
__outputs = OrderedDict(pe.output_t.field_dict)
circuit = PE_fc(MagmaFamily())
__asm = Assembler(__instr_type)
instr_magma_type = type(circuit.interface.ports[__instr_name])
__circuit = peak.wrap_with_disassembler(circuit, __asm.disassemble,
__asm.width,
HashableDict(__asm.layout),
instr_magma_type)
assert __circuit is not None
import math
import pytest
import random
import gmpy2
from hwtypes import BitVector, Bit, SIntVector
from peak.family import PyFamily
from lassen.common import DATAWIDTH, BFloat16_fc
from lassen.stdlib import *
from lassen.utils import float2bfbin, bfbin2float
SData = SIntVector[DATAWIDTH]
Data32 = SIntVector[DATAWIDTH * 2]
BFloat16 = BFloat16_fc(PyFamily())
RoundToZero = RoundToZero_fc(PyFamily())
RoundToZeroBounded = RoundToZeroBounded_fc(PyFamily())
FExp = FExp_fc(PyFamily())
Add32 = Add32_fc(PyFamily())
Sub32 = Sub32_fc(PyFamily())
FMA = FMA_fc(PyFamily())
FDiv = FDiv_fc(PyFamily())
FLN = FLN_fc(PyFamily())
NTESTS = 16
_BOUND = 2**15 - 2**6 - 1
_bounded_args = []
while len(_bounded_args) < NTESTS:
arg = BFloat16.random()
from collections import namedtuple
import random
import pytest
from hwtypes import SIntVector, UIntVector, BitVector, Bit
from peak.family import PyFamily
import lassen.asm as asm
from lassen import PE_fc, Inst_fc
from lassen.common import DATAWIDTH, BFloat16_fc
from lassen.utils import float2bfbin, bfbin2float
from rtl_utils import rtl_tester
Inst = Inst_fc(PyFamily())
Mode_t = Inst.rega
PE = PE_fc(PyFamily())
pe = PE()
BFloat16 = BFloat16_fc(PyFamily())
Data = BitVector[DATAWIDTH]
op = namedtuple("op", ["inst", "func"])
NTESTS = 16
#container for a floating point value easily indexed by sign, exp, and frac
fpdata = namedtuple("fpdata", ["sign", "exp", "frac"])
def is_nan_or_inf(fpdata):
return fpdata.exp==BitVector[8](-1)
from lassen.mode import Mode_t
from lassen.lut import LUT_t_fc
from lassen.alu import ALU_t, Signed_t
from lassen.asm import inst
from hwtypes import BitVector
from peak.family import PyFamily
import json
import os
import six
import subprocess
import tempfile
from memory_core.memory_mode import Mode as MemoryMode
import copy
family = PyFamily()
ALU, Signed = ALU_t, Signed_t
Mode = Mode_t
LUT = LUT_t_fc(family)
Cond = Cond_t
# LUT constants
B0 = BitVector[8]([0, 1, 0, 1, 0, 1, 0, 1])
B1 = BitVector[8]([0, 0, 1, 1, 0, 0, 1, 1])
B2 = BitVector[8]([0, 0, 0, 0, 1, 1, 1, 1])
def __get_alu_mapping(op_str):
if op_str == "add":
return ALU.Add, Signed.unsigned
elif op_str == "mux":
def _make_random(cls):
if issubclass(cls, hwtypes.BitVector):
return cls.random(len(cls))
if issubclass(cls, hwtypes.FPVector):
while True:
val = cls.random()
if val.fp_is_normal():
return val.reinterpret_as_bv()
return NotImplemented
_CAD_DIR = "/cad/synopsys/syn/P-2019.03/dw/sim_ver/"
_EXPENSIVE = {
"bits32.mul": ((umult0(),), "magma_Bits_32_mul_inst0", hwtypes.UIntVector[16]), # noqa
"bfloat16.mul": ((fp_mul(),), "magma_BFloat_16_mul_inst0", BFloat16_fc(PyFamily())), # noqa
"bfloat16.add": ((fp_add(),), "magma_BFloat_16_add_inst0", BFloat16_fc(PyFamily())), # noqa
}
@pytest.mark.parametrize("op", list(_EXPENSIVE.keys()))
def test_pe_data_gate(op, dw_files):
instrs, fu, BV = _EXPENSIVE[op]
is_float = issubclass(BV, hwtypes.FPVector)
if not irun_available() and is_float:
pytest.skip("Need irun to test fp ops")
core = PeakCore(PE_fc)
core.name = lambda: "PECore"
circuit = core.circuit()
def _make_random(cls):
if issubclass(cls, hwtypes.BitVector):
return cls.random(len(cls))
if issubclass(cls, hwtypes.FPVector):
while True:
val = cls.random()
if val.fp_is_normal():
return val.reinterpret_as_bv()
return NotImplemented
_EXPENSIVE = {
"bits32.mul":
((umult0(), ), "magma_Bits_32_mul_inst0", hwtypes.UIntVector[16]), # noqa
"bfloat16.mul": ((fp_mul(), ), "magma_BFloat_16_mul_inst0",
BFloat16_fc(PyFamily())), # noqa
"bfloat16.add": ((fp_add(), ), "magma_BFloat_16_add_inst0",
BFloat16_fc(PyFamily())), # noqa
}
@pytest.mark.parametrize("op", list(_EXPENSIVE.keys()))
def test_pe_data_gate(op, run_tb):
instrs, fu, BV = _EXPENSIVE[op]
is_float = issubclass(BV, hwtypes.FPVector)
if not irun_available() and is_float:
pytest.skip("Need irun to test fp ops")
# note to skip mul since CW BFloat is faulty
if op == "bfloat16.mul":
from collections import namedtuple
import operator
import random
import pytest
from hwtypes import SIntVector, UIntVector, BitVector, Bit
from peak.family import PyFamily
import lassen.asm as asm
from lassen import PE_fc, DATAWIDTH
PE = PE_fc(PyFamily())
Data = BitVector[DATAWIDTH]
op = namedtuple("op", ["name", "func"])
NTESTS = 32
@pytest.mark.parametrize("op", [
op('and', lambda x, y: x&y),
op('or', lambda x, y: x|y),
op('xor', lambda x, y: x^y),
])
def test_lut_binary(op):
pe = PE()
inst = getattr(asm, f"lut_{op.name}")()
for _ in range(NTESTS):
b0 = Bit(random.choice([0,1]))
b1 = Bit(random.choice([0,1]))
b2 = Bit(random.choice([0,1]))
data0 = UIntVector.random(DATAWIDTH)
from hwtypes import SIntVector, UIntVector, BitVector, Bit, FPVector, RoundingMode
from peak.family import PyFamily
from lassen import PE_fc, Inst_fc
import lassen.asm as asm
from lassen.common import *
class HashableDict(dict):
def __hash__(self):
return hash(tuple(sorted(self.keys())))
Data8 = BitVector[32]
Data = BitVector[DATAWIDTH]
PE = PE_fc(PyFamily())
Inst = Inst_fc(PyFamily())
pe = PE()
Mode_t = Inst.rega
NTESTS = 16
def write_data01(pe, data0: Data, data1: Data, instr=asm.add(), ra=Data(0)):
config_addr = Data8(DATA01_ADDR)
config_data = BitVector.concat(data0, data1)
config_en = Bit(1)
return pe(instr,
data0=ra,
config_addr=config_addr,
config_data=config_data,
from hwtypes import BitVector, Bit
from peak.family import PyFamily
from .isa import Inst_fc
Inst = Inst_fc(PyFamily())
LUT_t = Inst.lut
Cond_t = Inst.cond
Mode_t = Inst.rega
ALU_t = Inst.alu
Signed_t = Inst.signed
DataConst = Inst.data0
BitConst = Inst.bit0
#Lut Constants
B0 = BitVector[8]([0, 1, 0, 1, 0, 1, 0, 1])
B1 = BitVector[8]([0, 0, 1, 1, 0, 0, 1, 1])
B2 = BitVector[8]([0, 0, 0, 0, 1, 1, 1, 1])
def inst(alu,
signed=Signed_t.unsigned,
lut=0,
cond=Cond_t.Z,
ra_mode=Mode_t.BYPASS,
ra_const=0,
rb_mode=Mode_t.BYPASS,
rb_const=0,
rd_mode=Mode_t.BYPASS,
rd_const=0,
re_mode=Mode_t.BYPASS,