def declareInstance(self): out = TAB + "-------------------------\n" out = out + TAB + "-- declare instances\n" out = out + TAB + "-------------------------\n" for component in self.project.getInstancesList(): if component.getName() != "platform": out = out + "\n" + TAB+component.getInstanceName()\ +" : "\ +component.getName()\ +"\n" if component.getFPGAGenericsList() != []: out = out + TAB + "generic map (\n" for generic in component.getFPGAGenericsList(): out = out + TAB*3\ +generic.getName()+" => "\ +str(generic.getValue())\ +",\n" # suppress comma out = out[:-2]+"\n" out = out + TAB*2 + ")\n" out = out + TAB + "port map (\n" for interface in component.getInterfacesList(): out = out + TAB*3 + "-- " + interface.getName()+"\n" for port in interface.getPortsList(): if len(port.getPinsList())!=0: out=out+TAB*3\ +port.getName()\ +" => " out = out +component.getInstanceName()+"_"+port.getName() out = out +",\n" else: if int(port.getSize()) == 1: if port.getDir() == "out": out=out+TAB*3+port.getName()\ +" => open,\n" else: out=out+TAB*3+port.getName()\ +" => '0',\n" else: if port.getDir() == "out": out=out+TAB*3+port.getName()\ +" => open,\n" else: out=out+TAB*3+port.getName()\ +" => \""+sy.inttobin(0,int(port.getSize()))+"\",\n" # Suppress the #!@ last comma out = out[:-2] + "\n" out = out + TAB*3 + ");\n" out = out + "\n" return out
def addressdecoding(masterinterface, masterinstancename, intercon): """ generate VHDL for address decoding """ bus = masterinterface.bus masterinstance = masterinterface.parent masterinstancename = masterinstance.instancename rst_name = masterinstancename + "_" +\ masterinterface.get_port_by_type( bus.sig_name("master", "reset")).name clk_name = masterinstancename + "_" +\ masterinterface.get_port_by_type( bus.sig_name("master", "clock")).name masteraddressname = masterinstance.instancename + "_" +\ masterinterface.get_port_by_type( bus.sig_name("master", "address")).name masterstrobename = masterinstancename + "_" +\ masterinterface.get_port_by_type( bus.sig_name("master", "strobe")).name mastersizeaddr = masterinterface.addr_port_size out = ONETAB + "-----------------------\n" out = "\n" + ONETAB + "-- Address decoding --\n" out = out + ONETAB + "-----------------------\n" for slave in masterinterface.slaves: slaveinstance = slave.get_instance() slaveinterface = slave.get_interface() slavesizeaddr = slave.get_interface().addr_port_size slavebase_address = slaveinterface.base_addr if slavesizeaddr > 0: slaveaddressport = slave.get_interface().get_port_by_type( bus.sig_name("slave", "address")) slavename_addr = slaveinstance.instancename + "_" +\ slaveaddressport.name if slavesizeaddr == 1: out = out + ONETAB + slavename_addr +\ " <= " + masteraddressname + "(1);\n" elif slavesizeaddr > 1: out = out + ONETAB + slavename_addr + " <= " + masteraddressname +\ "(" + str(slavesizeaddr) + " downto 1);\n" out = out + "\n" out = out + ONETAB + "decodeproc : process(" + clk_name + ", " + rst_name +\ ", " + masteraddressname + ")\n" out = out + ONETAB + "begin\n" # initialize out = out + ONETAB*2 + "if " + rst_name + "='1' then\n" for slave in masterinterface.slaves: slaveinstance = slave.get_instance() slaveinterface = slave.get_interface() chipselectname = slaveinstance.instancename + "_" +\ slaveinterface.name + "_cs" out = out + ONETAB*3 + chipselectname + " <= '0';\n" out = out + ONETAB*2 + "elsif rising_edge(" + clk_name + ") then\n" for slave in masterinterface.slaves: slaveinstance = slave.get_instance() slaveinterface = slave.get_interface() chipselectname = slaveinstance.instancename + "_" +\ slaveinterface.name + "_cs" slavesizeaddr = slave.get_interface().addr_port_size slavebase_address = slaveinterface.base_addr if slavesizeaddr > 0: slaveaddressport = slave.get_interface().get_port_by_type( bus.sig_name("slave", "address")) slavename_addr = slaveinstance.instancename + "_" +\ slaveaddressport.name out = out + "\n" out = out + ONETAB*3 + "if " + masteraddressname + "(" +\ str(int(mastersizeaddr-1)) + " downto " + str(slavesizeaddr + 1) +\ ')="' +\ sy.inttobin(slavebase_address, int(mastersizeaddr))[:-(slavesizeaddr + 1)] +\ '"' + " and " + masterstrobename + "='1' then\n" out = out + ONETAB * 4 + chipselectname + " <= '1';\n" out = out + ONETAB * 3 + "else\n" out = out + ONETAB * 4 + chipselectname + " <= '0';\n" out = out + ONETAB * 3 + "end if;\n" out = out + "\n" + ONETAB * 2 + "end if;\n" +\ ONETAB + "end process decodeproc;\n\n" return out
def addressdecoding(masterif, masterinstance): """ generate VHDL for address decoding """ bus = masterif.bus mastername = masterinstance.instancename rst_name = gen_mst_sig(mastername, masterif, "reset") clk_name = gen_mst_sig(mastername, masterif, "clock") masteraddressname_r = "araddr_s" masteraddressname_w = "awaddr_s" masterstrobename_aw = gen_mst_sig(mastername, masterif, "awvalid") masterstrobename_w = gen_mst_sig(mastername, masterif, "wvalid") masterstrobename_ar = gen_mst_sig(mastername, masterif, "arvalid") masterstrobename_r = gen_mst_sig(mastername, masterif, "rready") mstsizeaddr = masterif.addr_size out = ONETAB + "-----------------------\n" out += "\n" + ONETAB + "-- Address decoding --\n" out += ONETAB + "-----------------------\n" for slave in masterif.slaves: slaveinstance = slave.get_instance() slaveif = slave.get_interface() slavesizeaddr = slaveif.addr_size slavebase_address = slaveif.base_addr slavebase_size = int(math.log(int(slaveif.data_size) / 8, 2)) if slavesizeaddr > 0: slavename_araddr = gen_slv_sig(slaveinstance.instancename, slaveif, bus, "araddress") slavename_awaddr = gen_slv_sig(slaveinstance.instancename, slaveif, bus, "awaddress") if slavesizeaddr == 1: out += ONETAB + slavename_araddr +\ " <= " + masteraddressname_r + "(1);\n" out += ONETAB + slavename_awaddr +\ " <= " + masteraddressname_w + "(1);\n" elif slavesizeaddr > 1: out += ONETAB + slavename_araddr + " <= " + \ masteraddressname_r + \ "(" + str(slavesizeaddr+slavebase_size-1) + " downto " + \ str(slavebase_size) + ");\n" out += ONETAB + slavename_awaddr + " <= " + \ masteraddressname_w +\ "(" + str(slavesizeaddr+slavebase_size-1) + " downto " + \ str(slavebase_size) + ");\n" out += "\n" out += ONETAB + "decodeproc : process(" + clk_name + ", " + \ rst_name + ")\n" out += ONETAB + "begin\n" # initialize out += ONETAB*2 + "if " + rst_name + "='1' then\n" for slave in masterif.slaves: slaveinstance = slave.get_instance() slaveif = slave.get_interface() csname = slaveinstance.instancename + "_" + \ slaveif.name + "_cs" out += ONETAB*3 + "aw_" + csname + " <= '0';\n" out += ONETAB*3 + "w_" + csname + " <= '0';\n" out += ONETAB*3 + "ar_" + csname + " <= '0';\n" out += ONETAB*3 + "r_" + csname + " <= '0';\n" out += ONETAB*2 + "elsif rising_edge(" + clk_name + ") then\n" gen_cond = lambda cond, mststrb, csname: cond + mststrb + \ "='1' then\n" + \ ONETAB * 4 + csname + " <= '1';\n" + \ ONETAB * 3 + "else\n" + \ ONETAB * 4 + csname + " <= '0';\n" + \ ONETAB * 3 + "end if;\n" for slave in masterif.slaves: slaveinstance = slave.get_instance() slaveif = slave.get_interface() csname = slaveinstance.instancename + "_" +\ slaveif.name + "_cs" slavesizeaddr = slave.get_interface().addr_size slavebase_address = slaveif.base_addr slavebase_size = int(math.log(int(slaveif.data_size) / 8, 2)) out += "\n" condw = ONETAB*3 + "if " + masteraddressname_w + "(" + \ str(int(mstsizeaddr-1)) + " downto " + \ str(slavesizeaddr + slavebase_size) + ')="' + \ sy.inttobin(slavebase_address, int(mstsizeaddr))[:-(slavesizeaddr + slavebase_size)] +\ '"' + " and " condr = ONETAB*3 + "if " + masteraddressname_r + "(" + \ str(int(mstsizeaddr-1)) + " downto " + \ str(slavesizeaddr + slavebase_size) + ')="' + \ sy.inttobin(slavebase_address, int(mstsizeaddr))[:-(slavesizeaddr + slavebase_size)] +\ '"' + " and " out += gen_cond(condw, masterstrobename_aw, "aw_" + csname) out += gen_cond(condw, masterstrobename_w, "w_" + csname) out += gen_cond(condr, masterstrobename_ar, "ar_" + csname) out += gen_cond(condr, masterstrobename_r, "r_" + csname) out += "\n" + ONETAB * 2 + "end if;\n" +\ ONETAB + "end process decodeproc;\n\n" return out
def addressdecoding(masterinterface,masterinstancename,intercon): """ generate VHDL for address decoding """ bus = masterinterface.getBus() masterinstance = masterinterface.getParent() masterinstancename = masterinstance.getInstanceName() rst_name = masterinstancename+"_"+masterinterface.getPortByType(bus.getSignalName("master","reset")).getName() clk_name = masterinstancename+"_"+masterinterface.getPortByType(bus.getSignalName("master","clock")).getName() masteraddressname = masterinstance.getInstanceName()+"_"+\ masterinterface.getPortByType( bus.getSignalName("master","address")).getName() masterstrobename = masterinstancename+"_"+\ masterinterface.getPortByType( bus.getSignalName("master","strobe")).getName() mastersizeaddr = masterinterface.getAddressSize() out =TAB + "-----------------------\n" out = "\n"+TAB + "-- Address decoding --\n" out = out + TAB + "-----------------------\n" for slave in masterinterface.getSlavesList(): slaveinstance = slave.getInstance() slaveinterface = slave.getInterface() slavesizeaddr = slave.getInterface().getAddressSize() slavebase_address = slaveinterface.getBaseInt() if slavesizeaddr > 0 : slaveaddressport = slave.getInterface().getPortByType( bus.getSignalName("slave","address")) slavename_addr = slaveinstance.getInstanceName() + "_" +\ slaveaddressport.getName() if slavesizeaddr == 1: out=out+TAB+slavename_addr+" <= "+masteraddressname+"(1);\n" elif slavesizeaddr > 1: out=out+TAB+slavename_addr+" <= "+masteraddressname\ +"("+str(slavesizeaddr) +" downto 1);\n" out = out + "\n" out = out+TAB+"decodeproc : process("+clk_name+","+rst_name+\ ","+masteraddressname+")\n" out = out+TAB+"begin\n" #initialize out = out+TAB*2+"if "+rst_name+"='1' then\n" for slave in masterinterface.getSlavesList(): slaveinstance = slave.getInstance() slaveinterface = slave.getInterface() chipselectname = slaveinstance.getInstanceName()+"_"+\ slaveinterface.getName()+"_cs" out = out+TAB*3+chipselectname+" <= '0';\n" out = out+TAB*2+"elsif rising_edge("+clk_name+") then\n" for slave in masterinterface.getSlavesList(): slaveinstance = slave.getInstance() slaveinterface = slave.getInterface() chipselectname = slaveinstance.getInstanceName()+"_"+\ slaveinterface.getName()+"_cs" slavesizeaddr = slave.getInterface().getAddressSize() slavebase_address = slaveinterface.getBaseInt() if slavesizeaddr > 0 : slaveaddressport = slave.getInterface().getPortByType( bus.getSignalName("slave","address")) slavename_addr = slaveinstance.getInstanceName() + "_" +\ slaveaddressport.getName() out=out+"\n" out=out+TAB*3+"if "+masteraddressname+"("\ +str(int(mastersizeaddr-1))\ +" downto "+str(slavesizeaddr+1)+')="'\ +sy.inttobin(slavebase_address, int(mastersizeaddr))[:-(slavesizeaddr+1)]+'"'\ +" and "+masterstrobename+"='1' then\n" out=out+TAB*4+chipselectname+" <= '1';\n" out=out+TAB*3+"else\n" out=out+TAB*4+chipselectname+" <= '0';\n" out=out+TAB*3+"end if;\n" out=out+"\n"+TAB*2+"end if;\n"+TAB+"end process decodeproc;\n\n" return out