def saveInstance(self): """ Save component in project directory files """ if not sy.dirExist(settings.projectpath + COMPONENTSPATH +"/"+ self.getInstanceName()): sy.makeDirectory(settings.projectpath + COMPONENTSPATH +"/"+ self.getInstanceName()) self.saveXml(settings.projectpath + COMPONENTSPATH +"/" +\ self.getInstanceName() + "/" + self.getInstanceName() + ".xml")
def generateProject(self): """ copy all hdl file in synthesis project directory """ for component in self.parent.getInstancesList(): if component.getNum() == "0": # Make directory compdir = settings.projectpath+SYNTHESISPATH+"/"+\ component.getName() if sy.dirExist(compdir): display.msg("Directory "+compdir+" exist, will be deleted") sy.delDirectory(compdir) sy.makeDirectory(compdir) display.msg("Make directory for "+component.getName()) # copy hdl files for hdlfile in component.getHdl_filesList(): try: sy.copyFile(settings.projectpath+\ COMPONENTSPATH+\ "/"+\ component.getInstanceName()+\ "/hdl/"+\ hdlfile.getFileName(), compdir+"/") except IOError,e: print display raise Error(str(e),0)
def generateIntercon(masterinterface,intercon): """Generate intercon VHDL code for wishbone16 bus """ masterinstance = masterinterface.getParent() syscon = masterinterface.getSysconInstance() project = masterinstance.getParent() ########################### #comment and header VHDLcode = header(settings.author,intercon) ########################### #entity VHDLcode = VHDLcode + entity(intercon) VHDLcode = VHDLcode + architectureHead(masterinterface,intercon) ########################### #Clock and Reset connection sysconinterface = syscon.getSysconInterface() listslave = masterinterface.getSlavesList() listinterfacesyscon = [] for slaveinstance in [slave.getInstance() for slave in listslave]: listinterfacesyscon.append(slaveinstance.getSysconInterface()) listinterfacesyscon.append(masterinstance.getSysconInterface()) VHDLcode = VHDLcode + connectClockandReset(syscon,listinterfacesyscon) ########################### #address decoding VHDLcode = VHDLcode +\ addressdecoding(masterinterface,sysconinterface,intercon) ########################### #controls slaves VHDLcode = VHDLcode + controlslave(masterinterface,intercon) ########################### #controls master VHDLcode = VHDLcode+controlmaster(masterinterface,intercon) ########################### #Foot VHDLcode = VHDLcode + architectureFoot(intercon) ########################### # saving if not sy.dirExist(settings.projectpath +COMPONENTSPATH+"/"+\ intercon.getInstanceName()+"/"+HDLDIR): sy.makeDirectory(settings.projectpath +COMPONENTSPATH+"/"+\ intercon.getInstanceName()+"/"+HDLDIR) file = open(settings.projectpath +COMPONENTSPATH+"/"+\ intercon.getInstanceName()+"/"+HDLDIR+"/"+\ intercon.getInstanceName()+VHDLEXT,"w") file.write(VHDLcode) file.close() #hdl file path hdl = Hdl_file(intercon, filename=intercon.getInstanceName()+\ VHDLEXT,istop=1,scope="both") intercon.addHdl_file(hdl) return VHDLcode
def generateProject(self): """ copy template drivers files """ project = self.project os = self.getName() if os == None: raise Error("Operating system must be selected",0) for component in project.getInstancesList(): if component.getNum() == "0": driverT = component.getDriver_Template(os) if driverT != None: display.msg("Create directory for "+component.getName()+" driver") # create component directory sy.makeDirectory(settings.projectpath+DRIVERSPATH+"/"+component.getName()) else: display.msg("No driver for "+component.getName())
def generateIntercon(masterinterface, intercon): """Generate intercon VHDL code for wishbone16 bus """ masterinstance = masterinterface.getParent() project = masterinstance.getParent() ########################### #comment and header VHDLcode = header(settings.author,intercon) ########################### #entity VHDLcode = VHDLcode + entity(intercon) VHDLcode = VHDLcode + architectureHead(masterinterface, intercon) ########################### #Clock and Reset connection VHDLcode = VHDLcode + connectClockandReset(masterinterface,intercon) #Foot VHDLcode = VHDLcode + architectureFoot(intercon) ########################### # saving if not sy.dirExist(settings.projectpath + COMPONENTSPATH+"/"+ intercon.getInstanceName()+"/"+HDLDIR): sy.makeDirectory(settings.projectpath+ COMPONENTSPATH+"/"+ intercon.getInstanceName()+"/"+HDLDIR) file = open(settings.projectpath +COMPONENTSPATH+"/"+ intercon.getInstanceName()+ "/"+HDLDIR+"/"+intercon.getInstanceName()+VHDLEXT,"w") file.write(VHDLcode) file.close() #hdl file path hdl = Hdl_file(intercon, filename=intercon.getInstanceName()+VHDLEXT, istop=1,scope="both") intercon.addHdl_file(hdl) return VHDLcode
def createComponent(self,componentname,libraryname,versionname): """ Creating new component 'componentname' for library 'libraryname' """ librarypath = settings.active_library.getLibraryPath(libraryname) componentpath = os.path.join(librarypath,componentname) # verify if component and version exist if sy.fileExist(os.path.join(componentpath,versionname+XMLEXT)): settings.active_component = None raise Error("Component version "+componentname+"."+versionname+\ " already exist") # make directories if component is really new if not sy.dirExist(componentpath): sy.makeDirectory(componentpath) sy.makeDirectory(os.path.join(componentpath,"hdl")) sy.makeDirectory(os.path.join(componentpath,"doc")) sy.makeDirectory(os.path.join(componentpath,"drivers_templates")) # create xml file WrapperXml.__init__(self,nodename="component") self.setName(componentname) self.saveComponent(os.path.join(componentpath,versionname)) self.setVersionName(versionname)