def main():
pico = PicoPlatform(1, bus_width=32, stream_width=128)
m = Top(pico)
so = dict(migen.build.xilinx.common.xilinx_special_overrides)
verilog.convert(m,
name="echo",
ios=pico.get_ios(),
special_overrides=so,
create_clock_domains=False).write("top.v")
def main():
pico = PicoPlatform(1, bus_width=32, stream_width=128)
m = Top(pico)
so = dict(migen.build.xilinx.common.xilinx_special_overrides)
verilog.convert(m,
name="echo",
ios=pico.get_ios(),
special_overrides=so,
create_clock_domains=False
).write("top.v")
def export(filename='echo.v'):
platform = PicoPlatform(bus_width=32, stream_width=128)
m = Top(platform)
so = dict(migen.build.xilinx.common.xilinx_special_overrides)
verilog.convert(m,
name="echo",
ios=platform.get_ios(),
special_overrides=so,
create_clock_domains=False).write(filename)
def export(filename='echo.v'):
platform = PicoPlatform(bus_width=32, stream_width=128)
m = Top(platform)
so = dict(migen.build.xilinx.common.xilinx_special_overrides)
verilog.convert(m,
name="echo",
ios=platform.get_ios(),
special_overrides=so,
create_clock_domains=False
).write(filename)
def sim(config):
config.platform = PicoPlatform(
0
if config.memtype == "BRAM" else config.addresslayout.num_pe_per_fpga,
create_hmc_ios=True,
bus_width=32,
init=(config.adj_val if config.memtype != "BRAM" else []),
init_elem_size_bytes=config.addresslayout.adj_val_entry_size_in_bytes)
tb = UnCore(config)
tb.submodules += config.platform
generators = config.platform.getSimGenerators()
generators["sys"].extend(
[core.gen_barrier_monitor(tb) for core in tb.cores])
generators["sys"].extend(get_simulators(tb, 'gen_selfcheck', tb))
generators["sys"].extend(get_simulators(tb, 'gen_simulation', tb))
# generators.extend([a.gen_stats(tb) for a in tb.apply])
# generators.extend([tb.gen_network_stats()])
run_simulation(tb,
generators,
clocks={
"sys": 10,
"bus": 480,
"stream": 8
},
vcd_name="{}.vcd".format(config.vcdname))
def sim(config):
config.platform = [
PicoPlatform(config.addresslayout.num_pe,
bus_width=32,
init=(config.adj_val if config.memtype != "BRAM" else []),
init_elem_size_bytes=config.addresslayout.
adj_val_entry_size_in_bytes)
for _ in range(config.addresslayout.num_fpga)
]
tb = SimTB(config)
tb.submodules += [p.logic for p in config.platform]
generators = config.platform[0].getSimGenerators()
for i in range(1, len(config.platform)):
g = config.platform[i].getSimGenerators()
for cd in generators:
generators[cd].extend(g[cd])
generators["sys"].extend(
[core.gen_barrier_monitor(tb) for core in tb.cores])
generators["sys"].extend(get_simulators(tb, 'gen_selfcheck', tb))
generators["sys"].extend(get_simulators(tb, 'gen_simulation', tb))
# generators.extend([a.gen_stats(tb) for a in tb.apply])
# generators.extend([tb.gen_network_stats()])
run_simulation(tb,
generators,
clocks={
"sys": 10,
"bus": 480,
"stream": 8
},
vcd_name="{}.vcd".format(config.vcdname))
def export(config, filename='top'):
logger = logging.getLogger('config')
config.platform = [
PicoPlatform(config.addresslayout.num_pe_per_fpga,
create_hmc_ios=True,
bus_width=32,
stream_width=128)
for _ in range(config.addresslayout.num_fpga)
]
m = [Top(config, i) for i in range(config.addresslayout.num_fpga)]
logger.info("Exporting design to files {0}[0-{1}]/{0}.v".format(
filename, config.addresslayout.num_fpga - 1))
for i in range(config.addresslayout.num_fpga):
iname = filename + "_" + str(i)
os.makedirs(iname, exist_ok=True)
with cd(iname):
verilog.convert(m[i],
name=filename,
ios=config.platform[i].get_ios()).write(filename +
".v")
if not config.memtype == "BRAM":
export_data(
config.adj_val,
"adj_val.data",
data_size=config.addresslayout.adj_val_entry_size_in_bytes * 8,
backup=config.alt_adj_val_data_name)
def __init__(self):
config = configparser.ConfigParser()
config['arch'] = {"num_pe": "1", "memtype": "HMCO"}
config['graph'] = {"nodes": "15", "edges": "30"}
config['app'] = {"algo": "sssp"}
config['logging'] = {"disable_logfile": True}
self.config = resolve_defaults(config=config, inverted=False)
self.adj_idx = self.config.adj_idx[0]
self.config.platform = PicoPlatform(
1,
bus_width=32,
stream_width=128,
init=self.config.adj_val,
init_elem_size_bytes=self.config.addresslayout.
adj_val_entry_size_in_bytes)
self.submodules.dut = Neighbors(pe_id=0, config=self.config)
def export(config, filename='top.v'):
config.platform = PicoPlatform(0 if config.memtype == "BRAM" else
config.addresslayout.num_pe_per_fpga,
create_hmc_ios=True,
bus_width=32,
stream_width=128)
m = Top(config)
so = dict(migen.build.xilinx.common.xilinx_special_overrides)
verilog.convert(m,
name="top",
ios=config.platform.get_ios(),
special_overrides=so,
create_clock_domains=False).write(filename)
if config.memtype != "BRAM":
export_data(
config.adj_val,
"adj_val.data",
data_size=config.addresslayout.adj_val_entry_size_in_bytes * 8,
backup=config.alt_adj_val_data_name)