def test(m):
clksleep(10)
for i in range(1, 6):
print(i)
x1 = m.o1_q.rd()
assert x1 == i
x2 = m.o2_q.rd()
assert x2 == i
def worker(self):
wait_value(True, self.start)
self.sub1.i.wr(10)
self.sub2.i.wr(20)
clksleep(10)
result1 = self.sub1.o.rd() == 20
result2 = self.sub2.o.rd() == 60
self.result.wr(result1 and result2)
def test(m):
datas = (0xdead, 0xbeef, 0xffff, 0x0000, 0x800)
for data in datas:
m.din.wr(data)
for i in range(5):
print(m.q.rd())
clksleep(10)
def sin_wave_worker(self, o_port, o_pulse):
v = 0
while polyphony.is_worker_running():
o_port(v)
o_pulse.wr(1)
print("o_pulse:", 1)
o_pulse.wr(0)
clksleep(1)
v = v + 1
def worker(self):
while polyphony.is_worker_running():
self.cs_n.wr(1)
self.sclk.wr(0)
clksleep(1)
data: uint16 = self.read_data()
clksleep(1)
self.data16.wr(data)
def test(sbus):
# sbus.ack(0)
# for i in range(5):
# wait_rising(sbus.stb)
# clksleep(1)
# sbus.ack(1)
# clkfence()
# sbus.ack(0)
clksleep(10)
def test(p02):
for i in range(8):
p02.clk1.wr(1)
p02.clk2.wr(1)
p02.clk1.wr(0)
p02.clk2.wr(0)
x1 = p02.out1.rd()
x2 = p02.out2.rd()
x3 = p02.out1.rd()
x4 = p02.out2.rd()
clksleep(2)
def worker(self):
#while polyphony.is_worker_running():
self.cs_n.wr(1)
self.sclk.wr(0)
clksleep(1)
self.write_data(0x34)
data: uint8 = self.read_data()
clksleep(1)
self.data8.wr(data)
def test(p03):
p03.i1.wr(2)
p03.i2.wr(2)
clkfence()
assert p03.o1.rd() == 2 + 1 + 2 + 3
assert p03.o2.rd() == 2 + 1 + 2 + 3
clksleep(10)
p03.i1.wr(3)
p03.i2.wr(3)
clkfence()
assert p03.o1.rd() == 3 + 1 + 2 + 3
assert p03.o2.rd() == 3 + 1 + 2 + 3
def test(spic):
f = 0
for i in range(12):
wait_falling(spic.sclk)
spic.miso.wr(f)
f = 1 - f
clkfence()
clksleep(2)
spic.miso.wr(0)
data = spic.data16.rd()
print("data0:", data)
def test(spi_master):
for i in range(7):
wait_value(1, spi_master.sclk)
f = 0
for i in range(8):
wait_value(0, spi_master.sclk)
clkfence()
spi_master.miso.wr(f)
f = 1 - f
clksleep(1)
spi_master.miso.wr(0)
data = spi_master.data8.rd()
print("data0:", data)
def main(self):
while polyphony.is_worker_running():
self.convst_n.wr(1)
self.cs_n.wr(1)
self.data_ready.wr(0)
clkfence()
self.convst_n.wr(0)
clksleep(CONVST_PULSE_CYCLE)
self.convst_n.wr(1)
clksleep(CONVERSION_CYCLE)
# starting ADC I/O
self.cs_n.wr(0)
sdo_tmp = 0
clksleep(1)
for i in range(16):
self.sclk.wr(0)
sdi_tmp = 1 if (self.din() & (1 << (15 - i))) else 0
self.sdi.wr(sdi_tmp)
clksleep(1)
self.sclk.wr(1)
sdo_tmp = sdo_tmp << 1 | self.sdo.rd()
self.sclk.wr(0)
self.dout.wr(sdo_tmp & 0x0fff)
self.chout.wr((sdo_tmp & 0x7000) >> 12)
self.cs_n.wr(1)
clkfence()
self.data_ready.wr(1)
def write_data(self, data):
self.cs_n.wr(0)
clkfence()
for i in range(8):
clkfence()
self.sclk.wr(0)
bit1 = (data >> (7 - i)) & 1
self.mosi.wr(bit1)
clksleep(1)
self.sclk.wr(1)
self.sclk.wr(0)
clkfence()
def test(m):
for i in range(10):
rv = 0
shift_n = 0
#b = [0] * 32
m.i_start.wr(1)
m.i_start.wr(0)
clkfence()
for i in range(32):
#b[i] = m.o_data.rd()
bb: bit32 = m.o_data.rd()
rv += (bb << shift_n)
print(bb, rv)
shift_n = shift_n + 1
print("xor shift:", rv)
clksleep(100)
def test(spic):
datas = (0xdead, 0xbeef, 0xffff, 0x0000, 0x800)
for data in datas:
print(data)
wait_falling(spic.convst_n)
print('convst_n fall', spic.convst_n())
wait_rising(spic.convst_n)
print('convst_n rise', spic.convst_n())
wait_falling(spic.cs_n)
print('cs_n fall', spic.cs_n())
spic.din.wr(0b1111000011110000)
for i in range(16):
databit = 1 if data & (1 << (15 - i)) else 0
spic.sdo.wr(databit)
wait_rising(spic.sclk)
wait_rising(spic.cs_n)
wait_rising(spic.data_ready)
clksleep(1)
assert spic.dout() == data & 0x0fff
assert spic.chout() == (data & 0x7000) >> 12
def read_data(self):
#self.cs_n.wr(0)
#clksleep(1)
data: uint8 = 0
#self.sclk.wr(0)
for i in range(8):
data <<= 1
clkfence()
self.sclk.wr(1)
clkfence()
bit1 = self.miso.rd() & 1
clkfence()
self.sclk.wr(0)
data |= bit1
clksleep(1)
self.cs_n.wr(1)
return data
def test(p):
for i in range(8):
x1_1 = p.out1.rd()
x1_2 = p.out2.rd()
x1_3 = p.out3.rd()
x2_1 = p.out1.rd()
x2_2 = p.out2.rd()
x2_3 = p.out3.rd()
x3_1 = p.out1.rd()
x3_2 = p.out2.rd()
x3_3 = p.out3.rd()
x4_1 = p.out1.rd()
x4_2 = p.out2.rd()
x4_3 = p.out3.rd()
print(x1_1, x2_1, x3_1, x4_1)
assert x1_1 == x1_2 == x1_3
assert x2_1 == x2_2 == x2_3
assert x3_1 == x3_2 == x3_3
assert x4_1 == x4_2 == x4_3
assert x1_1 <= x2_1 <= x3_1 <= x4_1
assert x1_2 <= x2_2 <= x3_2 <= x4_2
assert x1_3 <= x2_3 <= x3_3 <= x4_3
clksleep(2)
def write_data(self, addr, data):
self.cs_n.wr(0)
self.sclk.wr(0)
clksleep(1)
self.set_addr(0, 0, addr)
for i in range(8):
bit1 = (data >> (7 - i)) & 1
self.mosi.wr(bit1)
clksleep(1)
self.sclk.wr(1)
clksleep(1)
self.sclk.wr(0)
clksleep(2)
self.cs_n.wr(1)
self.mosi.wr(0)
return data
def read_data(self):
self.cs_n.wr(0)
clksleep(1)
data: uint16 = 0
self.sclk.wr(0)
for i in range(16):
data <<= 1
clksleep(1)
self.sclk.wr(1)
clksleep(1)
bit1 = self.miso.rd() & 1
clkfence()
self.sclk.wr(0)
data |= bit1
clksleep(1)
self.cs_n.wr(1)
return data
def read_data(self, addr):
self.cs_n.wr(0)
self.sclk.wr(0)
clksleep(1)
self.set_addr(1, 0, addr)
data = 0
for i in range(8):
data <<= 1
clksleep(1)
self.sclk.wr(1)
clksleep(1)
bit1 = self.miso.rd() & 1
clkfence()
self.sclk.wr(0)
data |= bit1
clksleep(1)
self.cs_n.wr(1)
return data
def main(self):
while polyphony.is_worker_running():
self.convst_n.wr(1)
self.cs_n.wr(1)
self.data_ready.wr(0)
clkfence()
self.convst_n.wr(0)
clksleep(10)
self.convst_n.wr(1)
clksleep(40)
# starting ADC I/O
self.cs_n.wr(0)
sdo_tmp = 0
clksleep(1)
for i in range(16):
self.sclk.wr(0)
clkfence()
sdi_tmp = 1 if (self.din() & (1 << (15 - i))) else 0
self.sdi.wr(sdi_tmp)
clksleep(1)
self.sclk.wr(1)
clkfence()
sdo_d = self.sdo.rd()
sdo_tmp = sdo_tmp << 1 | sdo_d
#print('sdo read!', i, sdo_d)
self.sclk.wr(0)
self.dout.wr(sdo_tmp & 0x0fff)
self.chout.wr((sdo_tmp & 0x7000) >> 12)
self.cs_n.wr(1)
clkfence()
self.data_ready.wr(1)
def test(m):
m.i_bit4.wr(0)
clksleep(5)
m.i_bit4.wr(0)
clksleep(5)
m.i_bit4.wr(1)
v = m.o_bit.rd()
clksleep(5)
if 1:
m.i_bit4.wr(0)
clksleep(5)
print("outv:", v)
if 0:
m.i_bit4.wr(0)
clksleep(5)
v = m.o_bit.rd()
print("outv:", v)
if 0:
m.i_bit4.wr(4)
v = m.o_bit.rd()
print("outv:", v)
m.i_bit4.wr(3)
v = m.o_bit.rd()
print("outv:", v)
m.i_bit4.wr(0)
v = m.o_bit.rd()
print("outv:", v)
m.i_bit4.wr(0)
v = m.o_bit.rd()
print("outv:", v)
m.i_bit4.wr(8)
v = m.o_bit.rd()
print("outv:", v)
print("-")
clksleep(10)
#
m.i_bit4.wr(0)
m.i_bit4.wr(0)
m.i_bit4.wr(2)
m.i_bit4.wr(1)
v = m.o_bit.rd()
print("outv:", v)
m.i_bit4.wr(1)
v = m.o_bit.rd()
print("outv:", v)
m.i_bit4.wr(1)
v = m.o_bit.rd()
print("outv:", v)
m.i_bit4.wr(7)
v = m.o_bit.rd()
print("outv:", v)
m.i_bit4.wr(0)
v = m.o_bit.rd()
print("outv:", v)
m.i_bit4.wr(0)
v = m.o_bit.rd()
print("outv:", v)
m.i_bit4.wr(8)
v = m.o_bit.rd()
print("outv:", v)
def test(m):
m.sub1.i.wr(10)
m.sub2.i.wr(20)
clksleep(10)
assert m.sub1.o.rd() == 20
assert m.sub2.o.rd() == 60
def test(m):
clksleep(10)
def missing_required_arg02():
clksleep()
def test0(m):
clksleep(10)
def test1(m):
clksleep(30)
def test(m):
print("Hello")
for i in range(100):
clksleep(1)
def set_addr(self, rw, ms, addr):
clksleep(1)
self.sclk.wr(0)
self.mosi.wr(rw)
clksleep(2)
self.sclk.wr(1)
clksleep(2)
self.sclk.wr(0)
self.mosi.wr(ms)
clksleep(2)
self.sclk.wr(1)
clksleep(2)
self.sclk.wr(0)
for i in range(6):
bit1 = (addr >> (5 - i)) & 1
self.mosi.wr(bit1)
clksleep(1)
self.sclk.wr(1)
clksleep(1)
self.sclk.wr(0)
clksleep(1)
def worker(self):
self.cs_n.wr(1)
self.sclk.wr(0)
clksleep(1)
self.write_data(0x20, 0x7F)
while polyphony.is_worker_running():
clksleep(20)
self.write_data(0x20, 0x7F)
clksleep(10)
data_who_am_i = self.read_data(0x0F)
clksleep(10)
data_x_l = self.read_data(0x29)
clksleep(10)
data_y_l = self.read_data(0x2B)
clksleep(10)
data_z_l = self.read_data(0x2D)
clksleep(10)
self.x_led.wr(1 if data_x_l > 0x30 else 0)
self.y_led.wr(1 if data_y_l > 0x30 else 0)
self.z_led.wr(1 if data_z_l > 0x30 else 0)
data_xyz = (data_x_l << 16) | (data_y_l << 8) | data_z_l
self.data24.wr(data_xyz)
