def cutback_phase(straight_length=100.0, bend_radius=10.0, n=2):
# Define sub components
bend180 = bend_circular(radius=bend_radius, start_angle=-90, theta=180)
pm_wg = phase_modulator_waveguide(length=straight_length)
wg_short = waveguide(length=1.0)
wg_short2 = waveguide(length=2.0)
wg_heater = waveguide_heater(length=10.0)
taper = _taper()
# Define a map between symbols and (component, input port, output port)
string_to_device_in_out_ports = {
"I": (taper, "1", "wg_2"),
"O": (taper, "wg_2", "1"),
"S": (wg_short, "W0", "E0"),
"P": (pm_wg, "W0", "E0"),
"A": (bend180, "W0", "W1"),
"B": (bend180, "W1", "W0"),
"H": (wg_heater, "W0", "E0"),
"-": (wg_short2, "W0", "E0"),
}
# Generate a sequence
# This is simply a chain of characters. Each of them represents a component
# with a given input and and a given output
repeated_sequence = "SIPOSASIPOSB"
heater_seq = "-H-H-H-H-"
sequence = repeated_sequence * n + "SIPO" + heater_seq
component = component_sequence(sequence, string_to_device_in_out_ports)
return component
def test_cutback_heater():
# Define subcomponents
bend_radius = 10.0
bend180 = bend_circular(radius=bend_radius, start_angle=-90, theta=180)
wg = waveguide(length=5.0)
wg_heater = waveguide_heater(length=20.0)
# Define a map between symbols and (component, input port, output port)
string_to_device_in_out_ports = {
"A": (bend180, "W0", "W1"),
"B": (bend180, "W1", "W0"),
"H": (wg_heater, "W0", "E0"),
"-": (wg, "W0", "E0"),
}
# Generate a sequence
# This is simply a chain of characters. Each of them represents a component
# with a given input and and a given output
sequence = "AB-H-H-H-H-BA"
component = component_sequence(sequence, string_to_device_in_out_ports)
assert component
return component
return pp.c.hline(length=length,
width=width,
layer=dummy_port.layer)
extension_factory = _ext_factory
dummy_ext = extension_factory(length=length, width=0.5)
port_labels = list(dummy_ext.ports.keys())
if input_port_ext is None:
input_port_ext = port_labels[0]
if output_port_ext is None:
output_port_ext = port_labels[-1]
for port_label in port_list:
port = component.ports.pop(port_label)
extension = c << extension_factory(length=length, width=port.width)
extension.connect(input_port_ext, port)
c.add_port(port_label, port=extension.ports[output_port_ext])
return c
if __name__ == "__main__":
import pp.components as pc
c = pc.bend_circular()
# ce = extend_ports(c, port_list=['W0'])
ce = extend_ports(c)
pp.show(ce)
name = component_name
elif type(port.parent) == pp.Component:
name = port.parent.name
else:
name = port.parent.ref_cell.name
text = "elec_{}_({})_{}".format(index, name, port.name)
gds_layer_label, gds_datatype_label = pd._parse_layer(layer_label)
label = pd.Label(
text=text,
position=port.midpoint,
anchor="o",
layer=gds_layer_label,
texttype=gds_datatype_label,
)
return label
if __name__ == "__main__":
# from pp.components import mmi1x2
from pp.components import bend_circular
from pp.add_grating_couplers import add_grating_couplers
# c = mmi1x2(width_mmi=5)
c = bend_circular()
cc = add_grating_couplers(c)
pp.show(cc)
def cutback_bend_circular(bend_radius=10.0, n_steps=3, n_stairs=4):
bend90 = bend_circular(radius=bend_radius)
c = cutback_bend(bend90=bend90, n_steps=n_steps, n_stairs=n_stairs)
cc = add_fiber_array(c, optical_routing_type=1)
return cc