def main():
segmk = Segmaker("design.bits", verbose=True)
# Load tags
with open("params.json", "r") as fp:
data = json.load(fp)
idelay_types = ["FIXED", "VARIABLE", "VAR_LOAD"]
delay_srcs = ["IDATAIN", "DATAIN"]
# Output tags
for params in data:
segmk.add_site_tag(params['IDELAY_IN_USE'], 'IN_USE', True)
segmk.add_site_tag(params['IDELAY_NOT_IN_USE'], 'IN_USE', False)
loc = verilog.unquote(params["LOC"])
# Delay type
value = verilog.unquote(params["IDELAY_TYPE"])
value = value.replace("_PIPE",
"") # VAR_LOAD and VAR_LOAD_PIPE are the same
add_site_group_zero(segmk, loc, "IDELAY_TYPE_", idelay_types, "FIXED",
value)
# Delay value
value = int(params["IDELAY_VALUE"])
for i in range(5):
segmk.add_site_tag(loc, "IDELAY_VALUE[%01d]" % i,
((value >> i) & 1) != 0)
segmk.add_site_tag(loc, "ZIDELAY_VALUE[%01d]" % i,
((value >> i) & 1) == 0)
# Delay source
value = verilog.unquote(params["DELAY_SRC"])
for x in delay_srcs:
segmk.add_site_tag(loc, "DELAY_SRC_%s" % x, int(value == x))
value = verilog.unquote(params["CINVCTRL_SEL"])
segmk.add_site_tag(loc, "CINVCTRL_SEL", int(value == "TRUE"))
value = verilog.unquote(params["PIPE_SEL"])
segmk.add_site_tag(loc, "PIPE_SEL", int(value == "TRUE"))
if "IS_C_INVERTED" in params:
segmk.add_site_tag(loc, "IS_C_INVERTED",
int(params["IS_C_INVERTED"]))
segmk.add_site_tag(loc, "ZINV_C", 1 ^ int(params["IS_C_INVERTED"]))
segmk.add_site_tag(loc, "IS_DATAIN_INVERTED",
int(params["IS_DATAIN_INVERTED"]))
if params['IBUF_IN_USE']:
value = verilog.unquote(params["HIGH_PERFORMANCE_MODE"])
segmk.add_site_tag(loc, "HIGH_PERFORMANCE_MODE",
int(value == "TRUE"))
segmk.add_site_tag(loc, "IS_IDATAIN_INVERTED",
int(params["IS_IDATAIN_INVERTED"]))
segmk.compile(bitfilter=bitfilter)
segmk.write()
def rw_width_tags(segmk, ps, site):
'''
Y0.READ_WIDTH_A
width 001_03 001_04 001_05
1 0 0 0
2 1 0 0
4 0 1 0
9 1 1 0
18 0 0 1
'''
params = ["READ_WIDTH_A", "READ_WIDTH_B", "WRITE_WIDTH_A", "WRITE_WIDTH_B"]
for param in params:
set_val = int(ps[param])
if set_val == 0:
set_val = 1
if set_val >= 36:
continue
def mk(x):
return '%s_%u' % (param, x)
segmaker.add_site_group_zero(
segmk, site, "",
[mk(1), mk(2), mk(4), mk(9), mk(18)], mk(1), mk(set_val))
def run():
segmk = Segmaker("design.bits")
print("Loading tags")
f = open('params.jl', 'r')
design = json.load(f)
for p in design:
ps = p["params"]
if p["site_type"] in "ICAP":
param = verilog.unquote(ps["ICAP_WIDTH"])
segmaker.add_site_group_zero(segmk, p["site"], "ICAP_WIDTH_",
["X32", "X8", "X16"], "X32", param)
elif p["site_type"] in "BSCAN":
param = str(ps["JTAG_CHAIN"])
segmaker.add_site_group_zero(segmk, p["site"], "JTAG_CHAIN_",
["1", "2", "3", "4"], param, param)
elif p["site_type"] in "CAPTURE":
param = verilog.unquote(ps["ONESHOT"])
segmk.add_site_tag(p["site"], "ONESHOT",
True if param in "TRUE" else False)
elif p["site_type"] in "STARTUP":
param = verilog.unquote(ps["PROG_USR"])
segmk.add_site_tag(p["site"], "PROG_USR",
True if param in "TRUE" else False)
elif p["site_type"] in "FRAME_ECC":
param = verilog.unquote(ps["FARSRC"])
segmaker.add_site_group_zero(segmk, p["site"], "FARSRC_",
["FAR", "EFAR"], param, param)
elif p["site_type"] in ["USR_ACCESS", "DCIRESET"]:
feature = "ENABLED"
segmk.add_site_tag(p["site"], feature,
True if ps["ENABLED"] else False)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
print("Loading tags")
segmk = Segmaker("design.bits")
'''
port,site,tile,pin,slew,drive,pulltype
di[0],IOB_X0Y107,LIOB33_X0Y107,A21,PULLDOWN
di[10],IOB_X0Y147,LIOB33_X0Y147,F14,PULLUP
'''
with open('params.jl', 'r') as f:
design = json.load(f)
for d in design:
site = d['site']
if skip_broken_tiles(d):
continue
iostandard = verilog.unquote(d['IOSTANDARD'])
stepdown = iostandard in STEPDOWN_IOSTANDARDS
segmk.add_site_tag(site, '_'.join(STEPDOWN_IOSTANDARDS), stepdown)
if d['type'] is None:
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
for drive in drives_for_iostandard(iostandard):
segmk.add_site_tag(
site,
'{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard,
drive), 0)
elif d['type'] == 'IBUF':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
for drive in drives_for_iostandard(iostandard):
segmk.add_site_tag(
site,
'{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard,
drive), 1)
elif d['type'] == 'OBUF':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
for drive in drives_for_iostandard(iostandard):
if drive == d['DRIVE']:
segmk.add_site_tag(
site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
iostandard, drive), 1)
else:
segmk.add_site_tag(
site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
iostandard, drive), 0)
elif d['type'] == 'IOBUF_INTERMDISABLE':
segmk.add_site_tag(site, 'INOUT', 1)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
if d['type'] is not None:
segmaker.add_site_group_zero(
segmk, site, "PULLTYPE.",
("NONE", "KEEPER", "PULLDOWN", "PULLUP"), "PULLDOWN",
verilog.unquote(d['PULLTYPE']))
if d['type'] == 'IBUF' or d['type'] is None:
continue
drive_opts = set()
for opt in ("LVCMOS25", "LVCMOS33", "LVCMOS18", "LVCMOS15",
"LVCMOS12", 'LVTTL'):
for drive_opt in ("4", "8", "12", "16", "24"):
if drive_opt == "16" and opt == "LVCMOS12":
continue
if drive_opt == "24" and opt not in ["LVCMOS18", 'LVTTL']:
continue
drive_opts.add(mk_drive_opt(opt, drive_opt))
segmaker.add_site_group_zero(segmk, site, '', drive_opts,
mk_drive_opt('LVCMOS25', '12'),
mk_drive_opt(iostandard, d['DRIVE']))
segmaker.add_site_group_zero(segmk, site, "SLEW.",
("SLOW", "FAST"), "FAST",
verilog.unquote(d['SLEW']))
if 'ibufdisable_wire' in d:
segmk.add_site_tag(site, 'IBUFDISABLE.I',
d['ibufdisable_wire'] != '0')
if 'intermdisable_wire' in d:
segmk.add_site_tag(site, 'INTERMDISABLE.I',
d['intermdisable_wire'] != '0')
segmk.compile(bitfilter=bitfilter)
segmk.write(allow_empty=True)
def run():
segmk = Segmaker("design.bits", verbose=True)
print("Loading tags")
with open('params.json', 'r') as fp:
data = json.load(fp)
used_dsps = set()
for params in data['instances']:
dsp = "DSP_0" if params['SITE'][-1] in "02468" else "DSP_1"
site = params['SITE']
if params['USE_DPORT'] == quote(
"TRUE") and params['USE_MULT'] != quote("NONE"):
add(segmk, site, dsp, 'ADREG', 0, to_int(params['ADREG']), 1)
add(segmk, site, dsp, 'ALUMODEREG', 0, to_int(params['ALUMODEREG']), 1)
if params['A_INPUT'] == quote("DIRECT"):
add(segmk, site, dsp, 'AREG_0', 0,
int(to_int(params['AREG']) == 0), 0, False)
add(segmk, site, dsp, 'AREG_2', 0,
int(to_int(params['AREG']) == 2), 0, False)
if params['B_INPUT'] == quote("DIRECT"):
add(segmk, site, dsp, 'BREG_0', 0,
int(to_int(params['BREG']) == 0), 0, False)
add(segmk, site, dsp, 'BREG_2', 0,
int(to_int(params['BREG']) == 2), 0, False)
if params['A_INPUT'] == quote("CASCADE"):
add(
segmk, site, dsp, 'AREG_2_ACASCREG_1', 0,
int(
to_int(params['AREG']) == 2
and to_int(params['ACASCREG']) == 1), 0, False)
add(
segmk, site, dsp, 'AREG_2_ACASCREG_1', 0,
int(
to_int(params['AREG']) == 2
and to_int(params['ACASCREG']) == 1), 1, False)
if params['B_INPUT'] == quote("CASCADE"):
add(
segmk, site, dsp, 'BREG_2_BCASCREG_1', 0,
int(
to_int(params['BREG']) == 2
and to_int(params['BCASCREG']) == 1), 0, False)
add(
segmk, site, dsp, 'BREG_2_BCASCREG_1', 0,
int(
to_int(params['BREG']) == 2
and to_int(params['BCASCREG']) == 1), 1, False)
add(segmk, site, dsp, 'CARRYINREG', 0, to_int(params['CARRYINREG']), 1)
add(segmk, site, dsp, 'CARRYINSELREG', 0,
to_int(params['CARRYINSELREG']), 1)
add(segmk, site, dsp, 'CREG', 0, to_int(params['CREG']), 1)
if params['USE_DPORT'] == quote(
"TRUE") and params['USE_MULT'] != quote("NONE"):
add(segmk, site, dsp, 'DREG', 0, to_int(params['DREG']), 1)
add(segmk, site, dsp, 'INMODEREG', 0, to_int(params['INMODEREG']), 1)
add(segmk, site, dsp, 'OPMODEREG', 0, to_int(params['OPMODEREG']), 1)
add(segmk, site, dsp, 'PREG', 0, to_int(params['PREG']), 1)
INPUT = {}
INPUT[quote('DIRECT')] = 0
INPUT[quote('CASCADE')] = 1
add(segmk, site, dsp, 'A_INPUT', 0, INPUT[params['A_INPUT']], 0)
add(segmk, site, dsp, 'B_INPUT', 0, INPUT[params['B_INPUT']], 0)
BOOL = {}
BOOL[quote('FALSE')] = 0
BOOL[quote('TRUE')] = 1
add(segmk, site, dsp, 'USE_DPORT', 0, BOOL[params['USE_DPORT']], 0)
add(segmk, site, dsp, 'USE_SIMD_FOUR12', 0,
params['USE_SIMD'] == quote("FOUR12"), 0, False)
add(segmk, site, dsp, 'USE_SIMD_FOUR12_TWO24', 0, params['USE_SIMD']
in (quote("TWO24"), quote("FOUR12")), 0, False)
MULT = {}
MULT[quote('NONE')] = 0
MULT[quote('MULTIPLY')] = 1
MULT[quote('DYNAMIC')] = 2
for i in range(2):
add(segmk, site, dsp, 'USE_MULT', i, MULT[params['USE_MULT']], 0)
add(segmk, site, dsp, 'MREG', 0, to_int(params['MREG']), 1)
AUTORESET = {}
AUTORESET[quote('NO_RESET')] = 0
AUTORESET[quote('RESET_NOT_MATCH')] = 1
AUTORESET[quote('RESET_MATCH')] = 2
add(segmk, site, dsp, 'AUTORESET_PATDET_RESET_NOT_MATCH', 0,
params['AUTORESET_PATDET'] == quote("RESET_NOT_MATCH"), 0, False)
add(
segmk, site, dsp, 'AUTORESET_PATDET_RESET', 0,
params['AUTORESET_PATDET']
in (quote("RESET_NOT_MATCH"), quote("RESET_MATCH")), 0, False)
for i in range(48):
add(segmk, site, dsp, 'MASK', i, to_int(params['MASK']), 0)
for i in range(48):
add(segmk, site, dsp, 'PATTERN', i, to_int(params['PATTERN']), 0)
if params['USE_PATTERN_DETECT'] == quote("PATDET"):
add_site_group_zero(segmk, site, dsp + ".", [
"SEL_MASK_%s" % x
for x in ["MASK", "C", "ROUNDING_MODE1", "ROUNDING_MODE2"]
], "SEL_MASK_MASK", "SEL_MASK_%s" % (params['SEL_MASK'][1:-1]))
USE_PATTERN_DETECT = {}
USE_PATTERN_DETECT[quote('NO_PATDET')] = 0
USE_PATTERN_DETECT[quote('PATDET')] = 1
add(segmk, site, dsp, 'USE_PATTERN_DETECT', 0,
USE_PATTERN_DETECT[params['USE_PATTERN_DETECT']], 0)
inv_ports = [
("ALUMODE", 4),
("CARRYIN", 1),
("CLK", 1),
("INMODE", 5),
("OPMODE", 7),
]
for port, width in inv_ports:
param = 'IS_{}_INVERTED'.format(port)
for i in range(width):
add(segmk, site, dsp, param, i, to_int(params[param]), 1,
width > 1)
segmk.compile()
segmk.write()
def main():
# Create map of iobank -> sites
iobanks = {}
site_to_iobank = {}
iobank_iostandards = {}
with open(os.path.join(os.getenv('FUZDIR'), 'build', 'iobanks.txt')) as f:
for l in f:
iob_site, iobank = l.strip().split(',')
iobank = int(iobank)
if iobank not in iobanks:
iobanks[iobank] = set()
iobanks[iobank].add(iob_site)
assert iob_site not in site_to_iobank
site_to_iobank[iob_site] = iobank
for iobank in iobanks:
iobank_iostandards[iobank] = set()
# Load a list of PUDC_B pin function tiles. They are configured differently
# by the vendor tools so need to be skipped
pudc_tiles = set()
with open(os.path.join(os.getenv('FUZDIR'), 'build',
'pudc_sites.csv')) as f:
for l in csv.DictReader(f):
pudc_tiles.add(l["tile"])
print("Loading tags")
segmk = Segmaker("design.bits")
'''
port,site,tile,pin,slew,drive,pulltype
di[0],IOB_X0Y107,LIOB33_X0Y107,A21,PULLDOWN
di[10],IOB_X0Y147,LIOB33_X0Y147,F14,PULLUP
'''
with open('params.json', 'r') as f:
design = json.load(f)
diff_pairs = set()
for d in design['tiles']:
iostandard = verilog.unquote(d['IOSTANDARD'])
if iostandard.startswith('DIFF_'):
diff_pairs.add(d['pair_site'])
for d in design['tiles']:
site = d['site']
if d['tile'] in pudc_tiles:
continue
if site in diff_pairs:
continue
iostandard = verilog.unquote(d['IOSTANDARD'])
if iostandard.startswith('DIFF_'):
iostandard = iostandard[5:]
iobank_iostandards[site_to_iobank[site]].add(iostandard)
segmk.add_site_tag(site,
'_'.join(STEPDOWN_IOSTANDARDS) + '.STEPDOWN',
iostandard in STEPDOWN_IOSTANDARDS)
if 'IN_TERM' in d:
segmaker.add_site_group_zero(segmk, site, 'IN_TERM.', [
'NONE', 'UNTUNED_SPLIT_40', 'UNTUNED_SPLIT_50',
'UNTUNED_SPLIT_60'
], 'NONE', d['IN_TERM'])
if d['type'] is None:
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.IN_ONLY'.format(iostandard), 0)
elif d['type'] == 'IBUF':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN_DIFF'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.IN_ONLY'.format(iostandard), 1)
segmk.add_tile_tag(d['tile'], 'IN_DIFF', 0)
if iostandard in IBUF_LOW_PWR_SUPPORTED:
segmk.add_site_tag(site, 'IBUF_LOW_PWR', d['IBUF_LOW_PWR'])
segmk.add_site_tag(site, 'ZIBUF_LOW_PWR',
1 ^ d['IBUF_LOW_PWR'])
elif d['type'] == 'IBUFDS':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN_DIFF'.format(iostandard), 1)
segmk.add_site_tag(d['pair_site'],
'{}.IN_DIFF'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.IN_ONLY'.format(iostandard), 1)
segmk.add_tile_tag(d['tile'], 'IN_DIFF', 1)
elif d['type'] == 'OBUF':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
segmk.add_tile_tag(d['tile'], 'OUT_DIFF', 0)
elif d['type'] == 'OBUFDS':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
segmk.add_tile_tag(d['tile'], 'OUT_DIFF', 1)
segmk.add_tile_tag(d['tile'], 'OUT_TDIFF', 0)
elif d['type'] == 'OBUFTDS':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
segmk.add_tile_tag(d['tile'], 'OUT_DIFF', 1)
segmk.add_tile_tag(d['tile'], 'OUT_TDIFF', 1)
elif d['type'] == 'IOBUF_INTERMDISABLE':
segmk.add_site_tag(site, 'INOUT', 1)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
if d['type'] is not None:
segmaker.add_site_group_zero(
segmk, site, "PULLTYPE.",
("NONE", "KEEPER", "PULLDOWN", "PULLUP"), "PULLDOWN",
verilog.unquote(d['PULLTYPE']))
if d['type'] in [None, 'IBUF', 'IBUFDS']:
continue
drive_opts = set()
for opt in ("LVCMOS25", "LVCMOS33", "LVCMOS18", "LVCMOS15",
"LVCMOS12", 'LVTTL'):
for drive_opt in ("4", "8", "12", "16", "24"):
if drive_opt == "16" and opt == "LVCMOS12":
continue
if drive_opt == "24" and opt not in ["LVCMOS18", 'LVTTL']:
continue
drive_opts.add(mk_drive_opt(opt, drive_opt))
drive_opts.add(mk_drive_opt("SSTL135", None))
segmaker.add_site_group_zero(segmk, site, '', drive_opts,
mk_drive_opt('LVCMOS25', '12'),
mk_drive_opt(iostandard, d['DRIVE']))
for opt in ["SLOW", "FAST"]:
segmk.add_site_tag(site, iostandard + ".SLEW." + opt,
opt == verilog.unquote(d['SLEW']))
if 'ibufdisable_wire' in d:
segmk.add_site_tag(site, 'IBUFDISABLE.I',
d['ibufdisable_wire'] != '0')
if 'intermdisable_wire' in d:
segmk.add_site_tag(site, 'INTERMDISABLE.I',
d['intermdisable_wire'] != '0')
site_to_cmt = {}
site_to_tile = {}
tile_to_cmt = {}
cmt_to_idelay = {}
with open(os.path.join(os.getenv('FUZDIR'), 'build',
'cmt_regions.csv')) as f:
for l in f:
site, tile, cmt = l.strip().split(',')
site_to_tile[site] = tile
site_to_cmt[site] = cmt
tile_to_cmt[tile] = cmt
# Given IDELAYCTRL's are only located in HCLK_IOI3 tiles, and
# there is only on HCLK_IOI3 tile per CMT, update
# CMT -> IDELAYCTRL / tile map.
if 'IDELAYCTRL' in site:
assert cmt not in cmt_to_idelay
cmt_to_idelay[cmt] = site, tile
# For each IOBANK with an active VREF set the feature
cmt_vref_active = set()
with open('iobank_vref.csv') as f:
for l in f:
iobank, vref = l.strip().split(',')
iobank = int(iobank)
cmt = None
for cmt_site in iobanks[iobank]:
if cmt_site in site_to_cmt:
cmt = site_to_cmt[cmt_site]
break
if cmt is None:
continue
cmt_vref_active.add(cmt)
_, hclk_cmt_tile = cmt_to_idelay[cmt]
opt = 'VREF.V_{:d}_MV'.format(int(float(vref) * 1000))
segmk.add_tile_tag(hclk_cmt_tile, opt, 1)
for iobank in iobank_iostandards:
if len(iobank_iostandards[iobank]) == 0:
continue
for cmt_site in iobanks[iobank]:
if cmt_site in site_to_cmt:
cmt = site_to_cmt[cmt_site]
break
if cmt is None:
continue
_, hclk_cmt_tile = cmt_to_idelay[cmt]
assert len(iobank_iostandards[iobank]) == 1, iobank_iostandards[iobank]
iostandard = list(iobank_iostandards[iobank])[0]
segmk.add_tile_tag(hclk_cmt_tile, 'STEPDOWN', iostandard
in STEPDOWN_IOSTANDARDS)
# For IOBANK's with no active VREF, clear all VREF options.
for cmt, (_, hclk_cmt_tile) in cmt_to_idelay.items():
if cmt in cmt_vref_active:
continue
for vref in (
.600,
.675,
.75,
.90,
):
opt = 'VREF.V_{:d}_MV'.format(int(vref * 1000))
segmk.add_tile_tag(hclk_cmt_tile, opt, 0)
segmk.compile(bitfilter=bitfilter)
segmk.write(allow_empty=True)
from prjxray import segmaker
segmk = Segmaker("design.bits")
print("Loading tags")
'''
port,site,tile,pin,val
di[0],IOB_X0Y107,LIOB33_X0Y107,A21,PULLDOWN
di[10],IOB_X0Y147,LIOB33_X0Y147,F14,PULLUP
'''
f = open('design.csv', 'r')
f.readline()
for l in f:
l = l.strip()
port, site, tile, pin, val = l.split(',')
'''
PULLTYPE 28 29 30
NONE X
KEEPER X X
PULLDOWN
PULLUP X X
'''
if val == "":
val = "NONE"
segmaker.add_site_group_zero(
segmk, site, "PULLTYPE.", ("NONE", "KEEPER", "PULLDOWN", "PULLUP"),
"PULLDOWN", val)
segmk.compile()
segmk.write()
#!/usr/bin/env python3
from prjxray.segmaker import Segmaker
from prjxray import segmaker
segmk = Segmaker("design.bits")
print("Loading params")
f = open('params.csv', 'r')
f.readline()
for l in f:
l = l.strip()
site, name, dir_, cell = l.split(',')
segmaker.add_site_group_zero(segmk, site, "MACRO.", ("INPUT", "OUTPUT"),
"", dir_.upper())
segmk.compile()
segmk.write()
def main():
segmk = Segmaker("design.bits")
fuz_dir = os.getenv("FUZDIR", None)
assert fuz_dir
with open(os.path.join(fuz_dir, "attrs.json"), "r") as attr_file:
attrs = json.load(attr_file)
print("Loading tags")
with open("params.json") as f:
primitives_list = json.load(f)
for primitive in primitives_list:
tile_type = primitive["tile_type"]
params_list = primitive["params"]
for params in params_list:
site = params["site"]
if "GTPE2_CHANNEL" not in site:
continue
in_use = params["IN_USE"]
segmk.add_site_tag(site, "IN_USE", in_use)
if in_use:
for param, param_info in attrs.items():
value = params[param]
param_type = param_info["type"]
param_digits = param_info["digits"]
param_values = param_info["values"]
if param_type == INT:
param_encodings = param_info["encoding"]
param_encoding = param_encodings[param_values.index(
value)]
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=param_encoding, digits=param_digits)
[::-1]
]
for i in range(param_digits):
segmk.add_site_tag(site, '%s[%u]' % (param, i),
bitstr[i])
elif param_type == BIN:
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=value, digits=param_digits)[::-1]
]
for i in range(param_digits):
segmk.add_site_tag(site, "%s[%u]" % (param, i),
bitstr[i])
elif param_type == BOOL:
segmk.add_site_tag(site, param, value == "TRUE")
else:
assert param_type == STR
# The RXSLIDE_MODE parameter has overlapping bits
# for its possible values. We need to treat it
# differently
if param == "RXSLIDE_MODE":
add_site_group_zero(segmk, site,
"{}.".format(param),
param_values, "OFF", value)
else:
for param_value in param_values:
segmk.add_site_tag(
site, "{}.{}".format(param, param_value),
value == param_value)
for param in [
"TXUSRCLK", "TXUSRCLK2", "TXPHDLYTSTCLK",
"SIGVALIDCLK", "RXUSRCLK", "RXUSRCLK2", "DRPCLK",
"DMONITORCLK", "CLKRSVD0", "CLKRSVD1"
]:
segmk.add_site_tag(site, "INV_" + param, params[param])
gtp_channel_x = [
"GTP_CHANNEL_0",
"GTP_CHANNEL_1",
"GTP_CHANNEL_2",
"GTP_CHANNEL_3",
]
gtp_channel_x_mid = [
"GTP_CHANNEL_0_MID_LEFT",
"GTP_CHANNEL_1_MID_LEFT",
"GTP_CHANNEL_2_MID_LEFT",
"GTP_CHANNEL_3_MID_LEFT",
"GTP_CHANNEL_0_MID_RIGHT",
"GTP_CHANNEL_1_MID_RIGHT",
"GTP_CHANNEL_2_MID_RIGHT",
"GTP_CHANNEL_3_MID_RIGHT",
]
if tile_type in gtp_channel_x:
bitfilter = bitfilter_gtp_channel_x
elif tile_type in gtp_channel_x_mid:
bitfilter = bitfilter_gtp_channel_x_mid
else:
assert False, tile_type
segmk.compile(bitfilter=bitfilter)
segmk.write()