def test_mem_ACL_is_correctly_matched_against_instructions(self):
"""Test comparing memory ACL against instructions.
`self` is this test case.
"""
res_util = (BagValDict(
{ICaseString("full system"): [InstrState(instr)]})
for instr in [0, 1])
assert simulate(
[
HwInstruction([], out_reg, ICaseString("ALU"))
for out_reg in ["R1", "R2"]
],
HwSpec(
processor_utils.load_proc_desc({
"units": [{
units.UNIT_NAME_KEY: "full system",
units.UNIT_WIDTH_KEY: 2,
units.UNIT_CAPS_KEY: ["ALU"],
**{
attr: True
for attr in [
units.UNIT_RLOCK_KEY, units.UNIT_WLOCK_KEY
]
}, units.UNIT_MEM_KEY: ["ALU"]
}],
"dataPath": []
}))) == list(res_util)
def test_capability_with_nonstandard_case_is_detected(
self, caplog, unit, acl_cap):
"""Test loading an ACL with a non-standard capability case.
`self` is this test case.
`caplog` is the log capture fixture.
`unit` is the loaded unit name.
`acl_cap` is the ACL capability to verify.
"""
caplog.set_level(WARNING)
ref_cap = acl_cap.upper()
assert load_proc_desc({
"units": [{
UNIT_NAME_KEY: unit,
UNIT_WIDTH_KEY: 1,
UNIT_CAPS_KEY: [ref_cap],
**{attr: True
for attr in [UNIT_RLOCK_KEY, UNIT_WLOCK_KEY]}, UNIT_MEM_KEY:
[acl_cap]
}],
"dataPath": []
}) == ProcessorDesc([], [], [
UnitModel(ICaseString(unit), 1, [ICaseString(ref_cap)],
LockInfo(True, True), [ICaseString(ref_cap)])
], [])
assert caplog.records
warn_msg = caplog.records[0].getMessage()
for token in [acl_cap, unit, ref_cap]:
assert token in warn_msg
def test_capability_case_is_checked_across_all_units(self, caplog, unit):
"""Test ACL capability cases are checked across all units.
`self` is this test case.
`caplog` is the log capture fixture.
"""
caplog.set_level(WARNING)
in_out_units = (UnitModel(ICaseString(name), 1, [ICaseString("ALU")],
LockInfo(True, True),
map(ICaseString, capabilities))
for name, capabilities in [(unit,
[]), ("core 2", ["ALU"])])
assert load_proc_desc({
"units": [{
UNIT_NAME_KEY: unit,
UNIT_WIDTH_KEY: 1,
UNIT_CAPS_KEY: ["ALU"],
**{attr: True
for attr in [UNIT_RLOCK_KEY, UNIT_WLOCK_KEY]}
}, {
UNIT_NAME_KEY: "core 2",
UNIT_WIDTH_KEY: 1,
UNIT_CAPS_KEY: ["ALU"],
**{attr: True
for attr in [UNIT_RLOCK_KEY, UNIT_WLOCK_KEY]}, UNIT_MEM_KEY:
["alu"]
}],
"dataPath": []
}) == ProcessorDesc([], [], in_out_units, [])
assert caplog.records
warn_msg = caplog.records[0].getMessage()
for token in ["alu", "core 2", "ALU", unit]:
assert token in warn_msg
def read_proc_file(proc_dir, file_name):
"""Read a processor description file.
`proc_dir` is the directory containing the processor description file.
`file_name` is the processor description file name.
The function returns the processor description.
"""
return processor_utils.load_proc_desc(_load_yaml(proc_dir, file_name))
def test_paths_with_multiple_locks_are_only_detected_per_capability(self):
"""Test detecting multi-lock paths per capability.
`self` is this test case.
The method asserts that multiple locks across a path with different
capabilities don't raise an exception as long as single-capability
paths don't have multiple locks.
"""
load_proc_desc(
{"units":
[{UNIT_NAME_KEY: "ALU input", UNIT_WIDTH_KEY: 1,
UNIT_CAPS_KEY: ["ALU"], UNIT_RLOCK_KEY: True},
{UNIT_NAME_KEY: "MEM input", UNIT_WIDTH_KEY: 1, UNIT_CAPS_KEY:
["MEM"]}, {UNIT_NAME_KEY: "center", UNIT_WIDTH_KEY: 1,
UNIT_CAPS_KEY: ["ALU", "MEM"]},
{UNIT_NAME_KEY: "ALU output", UNIT_WIDTH_KEY: 1, UNIT_CAPS_KEY: [
"ALU"], UNIT_WLOCK_KEY: True},
{UNIT_NAME_KEY: "MEM output", UNIT_WIDTH_KEY: 1,
UNIT_CAPS_KEY: ["MEM"], **{lock_prop: True for lock_prop in [
UNIT_RLOCK_KEY, UNIT_WLOCK_KEY]}}],
"dataPath": [["ALU input", "center"], ["MEM input", "center"],
["center", "ALU output"], ["center", "MEM output"]]})
def read_processor(proc_file: typing.IO[str]) -> HwDesc:
"""Read the processor description from the given file.
`proc_file` is the YAML file containing the processor description.
The function constructs necessary processing structures from the
given processor description file. It returns a processor
description.
"""
yaml_desc = yaml.safe_load(proc_file)
microarch_key = "microarch"
processor = processor_utils.load_proc_desc(yaml_desc[microarch_key])
isa_key = "ISA"
return HwDesc(processor, processor_utils.load_isa(
yaml_desc[isa_key].items(), processor_utils.get_abilities(processor)))
def test_processor_with_explicit_attributes(self):
"""Test loading a processor with explicitly defined attributes.
`self` is this test case.
"""
assert load_proc_desc({
"units": [{
UNIT_NAME_KEY: "full system",
UNIT_WIDTH_KEY: 1,
UNIT_CAPS_KEY: ["ALU"],
**{attr: True
for attr in [UNIT_RLOCK_KEY, UNIT_WLOCK_KEY]}, UNIT_MEM_KEY:
["ALU"]
}],
"dataPath": []
}) == ProcessorDesc([], [], [
UnitModel(ICaseString("full system"), 1, [ICaseString("ALU")],
LockInfo(True, True), [ICaseString("ALU")])
], [])
def test_partial_mem_access(self):
"""Test loading a processor with partial memory access.
`self` is this test case.
"""
assert load_proc_desc({
"units": [{
UNIT_NAME_KEY: "full system",
UNIT_WIDTH_KEY: 1,
UNIT_CAPS_KEY: ["ALU", "MEM"],
**{attr: True
for attr in [UNIT_RLOCK_KEY, UNIT_WLOCK_KEY]}, UNIT_MEM_KEY:
["MEM"]
}],
"dataPath": []
}) == ProcessorDesc([], [], [
UnitModel(ICaseString("full system"), 1,
map(ICaseString, ["ALU", "MEM"]), LockInfo(True, True),
[ICaseString("MEM")])
], [])