def _RunAnalysis(self, _): # create a RivieraPROVHDLCompiler instance vlib = self._toolChain.GetVHDLLibraryTool() for lib in self._pyIPCMIProject.VHDLLibraries: vlib.Parameters[vlib.SwitchLibraryName] = lib.Name try: vlib.CreateLibrary() except DryRunException: pass # create a RivieraPROVHDLCompiler instance vcom = self._toolChain.GetVHDLCompiler() vcom.Parameters[vcom.SwitchVHDLVersion] = repr(self._vhdlVersion) # run vcom compile for each VHDL file for file in self._pyIPCMIProject.Files(fileType=FileTypes.VHDLSourceFile): if (not file.Path.exists()): raise SimulatorException("Cannot analyse '{0!s}'.".format(file.Path)) from FileNotFoundError(str(file.Path)) vcomLogFile = self.Directories.Working / (file.Path.stem + ".vcom.log") vcom.Parameters[vcom.SwitchVHDLLibrary] = file.LibraryName vcom.Parameters[vcom.ArgSourceFile] = file.Path try: vcom.Compile() except DryRunException: pass except RivieraPROException as ex: raise SimulatorException("Error while compiling '{0!s}'.".format(file.Path)) from ex if vcom.HasErrors: raise SkipableSimulatorException("Error while compiling '{0!s}'.".format(file.Path))
def Run(self, testbench, board, vhdlVersion, vhdlGenerics=None, withCoverage=False): self._withCoverage = withCoverage # select modelsim.ini if board.Device.Vendor is Vendors.Altera: self.ModelSimIniDirectoryPath /= self.Host.Config[ 'CONFIG.DirectoryNames']['AlteraSpecificFiles'] elif board.Device.Vendor is Vendors.Lattice: self.ModelSimIniDirectoryPath /= self.Host.Config[ 'CONFIG.DirectoryNames']['LatticeSpecificFiles'] elif board.Device.Vendor is Vendors.Xilinx: self.ModelSimIniDirectoryPath /= self.Host.Config[ 'CONFIG.DirectoryNames']['XilinxSpecificFiles'] self.ModelSimIniPath = self.ModelSimIniDirectoryPath / self.ModelSimIniPath if not self.ModelSimIniPath.exists(): raise SimulatorException("ModelSim ini file '{0!s}' not found.".format(self.ModelSimIniPath)) \ from FileNotFoundError(str(self.ModelSimIniPath)) super().Run(testbench, board, vhdlVersion, vhdlGenerics)
def _RunSimulation(self, testbench): if (SimulationSteps.ShowWaveform in self._simulationSteps): return self._RunSimulationWithGUI(testbench) # tclBatchFilePath = self.Host.Directories.Root / self.Host.Config[testbench.ConfigSectionName]['aSimBatchScript'] # create a ActiveHDLSimulator instance asim = self._toolChain.GetSimulator() asim.Parameters[ asim. SwitchBatchCommand] = "asim -lib {0} {1}; run -all; bye".format( VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName) # asim.Optimization = True # asim.TimeResolution = "1fs" # asim.ComanndLineMode = True # asim.BatchCommand = "do {0}".format(str(tclBatchFilePath)) # asim.TopLevel = "{0}.{1}".format(VHDLTestbenchLibraryName, testbenchName) try: testbench.Result = asim.Simulate() except DryRunException: pass except ActiveHDLException as ex: raise SimulatorException( "Error while simulating '{0}.{1}'.".format( VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName)) from ex if asim.HasErrors: raise SkipableSimulatorException( "Error while simulating '{0}.{1}'.".format( VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName))
def _RunElaboration(self, testbench): exeFilePath = self.Directories.Working / (testbench.ModuleName + ".exe") prjFilePath = self.Directories.Working / (testbench.ModuleName + ".prj") self._WriteXilinxProjectFile(prjFilePath, "iSim") # create a ISELinker instance fuse = self._toolChain.GetFuse() fuse.Parameters[fuse.FlagIncremental] = True fuse.Parameters[fuse.SwitchTimeResolution] = "1fs" fuse.Parameters[fuse.SwitchMultiThreading] = "4" fuse.Parameters[fuse.FlagRangeCheck] = True fuse.Parameters[fuse.SwitchProjectFile] = str(prjFilePath) fuse.Parameters[fuse.SwitchOutputFile] = str(exeFilePath) fuse.Parameters[fuse.ArgTopLevel] = "{0}.{1}".format( VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName) try: fuse.Link() except DryRunException: pass except ISEException as ex: raise SimulatorException( "Error while analysing '{0!s}'.".format(prjFilePath)) from ex if fuse.HasErrors: raise SkipableSimulatorException( "Error while analysing '{0!s}'.".format(prjFilePath))
def _RunElaboration(self, testbench): """""" if (self._toolChain.Backend == "mcode"): return # create a GHDLElaborate instance ghdl = self._toolChain.GetGHDLElaborate() ghdl.Parameters[ghdl.FlagVerbose] = (self.Logger.LogLevel is Severity.Debug) ghdl.Parameters[ghdl.SwitchVHDLLibrary] = VHDL_TESTBENCH_LIBRARY_NAME ghdl.Parameters[ghdl.ArgTopLevel] = testbench.ModuleName ghdl.Parameters[ghdl.FlagExplicit] = True if (self._withCoverage is True): ghdl.Parameters[ghdl.SwitchLinkerOption] = ( "-L/opt/ghdl/0.34-dev-gcc4/lib/gcc/x86_64-unknown-linux-gnu/4.9.4", "-lgcov", "--coverage") self._SetVHDLVersionAndIEEEFlavor(ghdl) self._SetExternalLibraryReferences(ghdl) try: ghdl.Elaborate() except DryRunException: pass except GHDLException as ex: raise SimulatorException( "Error while elaborating '{0}.{1}'.".format( VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName)) from ex if ghdl.HasErrors: raise SkipableSimulatorException( "Error while elaborating '{0}.{1}'.".format( VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName))
def _RunSimulation(self, testbench): if (SimulationSteps.ShowWaveform in self._simulationSteps): return self._RunSimulationWithGUI(testbench) tclBatchFilePath = self.Host.Directories.Root / self.Host.Config[ testbench.ConfigSectionName]['vSimBatchScript'] tclDefaultBatchFilePath = self.Host.Directories.Root / self.Host.Config[ testbench.ConfigSectionName]['vSimDefaultBatchScript'] # create a VHDLSimulator instance vsim = self._toolChain.GetSimulator() vsim.Parameters[ vsim.SwitchModelSimIniFile] = self.ModelSimIniPath.as_posix() # vsim.Parameters[vsim.FlagEnableOptimization] = True # FIXME: vsim.Parameters[vsim.FlagReportAsError] = "3473" vsim.Parameters[vsim.SwitchTimeResolution] = "1fs" vsim.Parameters[vsim.FlagCommandLineMode] = True vsim.Parameters[vsim.SwitchTopLevel] = "{0}.{1}".format( VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName) if (self._withCoverage is True): vsim.Parameters[vsim.FlagEnableCoverage] = True vsim.Parameters[vsim.FlagEnableFSMDebugging] = True vsim.Parameters[ vsim.FlagEnableKeepAssertionCountsForCoverage] = True # find a Tcl batch script for the BATCH mode vsimBatchCommand = "" if (tclBatchFilePath.exists()): self.LogDebug("Found Tcl script for BATCH mode: '{0!s}'".format( tclBatchFilePath)) vsimBatchCommand += "do {0};".format(tclBatchFilePath.as_posix()) elif (tclDefaultBatchFilePath.exists()): self.LogDebug( "Falling back to default Tcl script for BATCH mode: '{0!s}'". format(tclDefaultBatchFilePath)) vsimBatchCommand += "do {0};".format( tclDefaultBatchFilePath.as_posix()) else: raise ModelSimException("No Tcl batch script for BATCH mode found.") \ from FileNotFoundError(str(tclDefaultBatchFilePath)) vsim.Parameters[vsim.SwitchBatchCommand] = vsimBatchCommand try: testbench.Result = vsim.Simulate() except DryRunException: pass except ModelSimException as ex: raise SimulatorException( "Error while simulating '{0}.{1}'.".format( VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName)) from ex if vsim.HasErrors: raise SkipableSimulatorException( "Error while simulating '{0}.{1}'.".format( VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName))
def _RunAnalysis(self, _): # create a ActiveHDLVHDLCompiler instance alib = self._toolChain.GetVHDLLibraryTool() for lib in self._pyIPCMIProject.VHDLLibraries: alib.Parameters[alib.SwitchLibraryName] = lib.Name try: alib.CreateLibrary() except DryRunException: pass except ActiveHDLException as ex: raise SimulatorException( "Error creating VHDL library '{0}'.".format( lib.Name)) from ex if alib.HasErrors: raise SimulatorException( "Error creating VHDL library '{0}'.".format(lib.Name)) # create a ActiveHDLVHDLCompiler instance acom = self._toolChain.GetVHDLCompiler() acom.Parameters[acom.SwitchVHDLVersion] = repr(self._vhdlVersion) # run acom compile for each VHDL file for file in self._pyIPCMIProject.Files( fileType=FileTypes.VHDLSourceFile): if (not file.Path.exists()): raise SimulatorException("Cannot analyse '{0!s}'.".format( file.Path)) from FileNotFoundError(str(file.Path)) acom.Parameters[acom.SwitchVHDLLibrary] = file.LibraryName acom.Parameters[acom.ArgSourceFile] = file.Path # set a per file log-file with '-l', 'vcom.log', try: acom.Compile() except DryRunException: pass except ActiveHDLException as ex: raise SimulatorException( "Error while compiling '{0!s}'.".format(file.Path)) from ex if acom.HasErrors: raise SkipableSimulatorException( "Error while compiling '{0!s}'.".format(file.Path))
def Run(self, testbench, board, vhdlVersion, vhdlGenerics=None): # TODO: refactor into a ModelSim module, shared by ModelSim and Cocotb (-> MixIn class)? # select modelsim.ini if board.Device.Vendor is Vendors.Altera: self.ModelSimIniDirectoryPath /= self.Host.Config['CONFIG.DirectoryNames']['AlteraSpecificFiles'] elif board.Device.Vendor is Vendors.Lattice: self.ModelSimIniDirectoryPath /= self.Host.Config['CONFIG.DirectoryNames']['LatticeSpecificFiles'] elif board.Device.Vendor is Vendors.Xilinx: self.ModelSimIniDirectoryPath /= self.Host.Config['CONFIG.DirectoryNames']['XilinxSpecificFiles'] self.ModelSimIniPath = self.ModelSimIniDirectoryPath / self.ModelSimIniPath if not self.ModelSimIniPath.exists(): raise SimulatorException("ModelSim ini file '{0!s}' not found.".format(self.ModelSimIniPath)) \ from FileNotFoundError(str(self.ModelSimIniPath)) super().Run(testbench, board, vhdlVersion, vhdlGenerics)
def _RunSimulation(self, testbench): iSimLogFilePath = self.Directories.Working / (testbench.ModuleName + ".iSim.log") exeFilePath = self.Directories.Working / (testbench.ModuleName + ".exe") tclBatchFilePath = self.Host.Directories.Root / self.Host.Config[ testbench.ConfigSectionName]['iSimBatchScript'] tclGUIFilePath = self.Host.Directories.Root / self.Host.Config[ testbench.ConfigSectionName]['iSimGUIScript'] wcfgFilePath = self.Host.Directories.Root / self.Host.Config[ testbench.ConfigSectionName]['iSimWaveformConfigFile'] # create a ISESimulator instance iSim = ISESimulator(self._host.Platform, self._host.DryRun, exeFilePath, self._toolChain._environment, logger=self.Logger) iSim.Parameters[iSim.SwitchLogFile] = str(iSimLogFilePath) if (SimulationSteps.ShowWaveform not in self._simulationSteps): iSim.Parameters[iSim.SwitchTclBatchFile] = str(tclBatchFilePath) else: iSim.Parameters[iSim.SwitchTclBatchFile] = str(tclGUIFilePath) iSim.Parameters[iSim.FlagGuiMode] = True # if iSim save file exists, load it's settings if wcfgFilePath.exists(): self.LogDebug( "Found waveform config file: '{0!s}'".format(wcfgFilePath)) iSim.Parameters[iSim.SwitchWaveformFile] = str(wcfgFilePath) else: self.LogDebug( "Didn't find waveform config file: '{0!s}'".format( wcfgFilePath)) try: testbench.Result = iSim.Simulate() except DryRunException: pass except ISEException as ex: raise SimulatorException( "Error while simulating '{0}.{1}'.".format( VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName)) from ex if iSim.HasErrors: raise SkipableSimulatorException( "Error while simulating '{0}.{1}'.".format( VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName))
def _RunSimulation(self, testbench): xSimLogFilePath = self.Directories.Working / (testbench.ModuleName + ".xSim.log") tclBatchFilePath = self.Host.Directories.Root / self.Host.Config[ testbench.ConfigSectionName]['xSimBatchScript'] tclGUIFilePath = self.Host.Directories.Root / self.Host.Config[ testbench.ConfigSectionName]['xSimGUIScript'] wcfgFilePath = self.Host.Directories.Root / self.Host.Config[ testbench.ConfigSectionName]['xSimWaveformConfigFile'] # create a VivadoSimulator instance xSim = self._toolChain.GetSimulator() xSim.Parameters[xSim.SwitchLogFile] = str(xSimLogFilePath) if (SimulationSteps.ShowWaveform not in self._simulationSteps): xSim.Parameters[ xSim.SwitchTclBatchFile] = tclBatchFilePath.as_posix() else: xSim.Parameters[ xSim.SwitchTclBatchFile] = tclGUIFilePath.as_posix() xSim.Parameters[xSim.FlagGuiMode] = True # if xSim save file exists, load it's settings if wcfgFilePath.exists(): self.LogDebug( "Found waveform config file: '{0!s}'".format(wcfgFilePath)) xSim.Parameters[xSim.SwitchWaveformFile] = str(wcfgFilePath) else: self.LogDebug( "Didn't find waveform config file: '{0!s}'".format( wcfgFilePath)) xSim.Parameters[xSim.SwitchSnapshot] = testbench.ModuleName try: testbench.Result = xSim.Simulate() except DryRunException: pass except VivadoException as ex: raise SimulatorException( "Error while simulating '{0}.{1}'.".format( VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName)) from ex if xSim.HasErrors: raise SkipableSimulatorException( "Error while simulating '{0}.{1}'.".format( VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName))
def _RunAnalysis(self, testbench): """""" # create a GHDLAnalyzer instance ghdl = self._toolChain.GetGHDLAnalyze() ghdl.Parameters[ghdl.FlagVerbose] = (self.Logger.LogLevel is Severity.Debug) ghdl.Parameters[ghdl.FlagExplicit] = True ghdl.Parameters[ghdl.FlagRelaxedRules] = True ghdl.Parameters[ghdl.FlagWarnBinding] = True ghdl.Parameters[ghdl.FlagNoVitalChecks] = True ghdl.Parameters[ghdl.FlagMultiByteComments] = True ghdl.Parameters[ghdl.FlagSynBinding] = True ghdl.Parameters[ghdl.FlagPSL] = True if (self._withCoverage is True): ghdl.Parameters[ghdl.FlagDebug] = True ghdl.Parameters[ghdl.FlagProfileArcs] = True ghdl.Parameters[ghdl.FlagTestCoverage] = True self._SetVHDLVersionAndIEEEFlavor(ghdl) self._SetExternalLibraryReferences(ghdl) # run GHDL analysis for each VHDL file for file in self._pyIPCMIProject.Files( fileType=FileTypes.VHDLSourceFile): if (not file.Path.exists()): raise SkipableSimulatorException( "Cannot analyse '{0!s}'.".format( file.Path)) from FileNotFoundError(str(file.Path)) ghdl.Parameters[ghdl.SwitchVHDLLibrary] = file.LibraryName ghdl.Parameters[ghdl.ArgSourceFile] = file.Path try: ghdl.Analyze() except DryRunException: pass except GHDLReanalyzeException as ex: raise SkipableSimulatorException( "Error while analysing '{0!s}'.".format(file.Path)) from ex except GHDLException as ex: raise SimulatorException( "Error while analysing '{0!s}'.".format(file.Path)) from ex if ghdl.HasErrors: raise SkipableSimulatorException( "Error while analysing '{0!s}'.".format(file.Path))
def _RunElaboration(self, testbench): xelabLogFilePath = self.Directories.Working / (testbench.ModuleName + ".xelab.log") prjFilePath = self.Directories.Working / (testbench.ModuleName + ".prj") self._WriteXilinxProjectFile(prjFilePath, "xSim", self._vhdlVersion) # create a VivadoLinker instance xelab = self._toolChain.GetElaborator() xelab.Parameters[ xelab. SwitchTimeResolution] = "1fs" # set minimum time precision to 1 fs xelab.Parameters[ xelab. SwitchMultiThreading] = "off" if self.Logger.LogLevel is Severity.Debug else "auto" # disable multithreading support in debug mode xelab.Parameters[xelab.FlagRangeCheck] = True xelab.Parameters[ xelab. SwitchOptimization] = "0" if self.Logger.LogLevel is Severity.Debug else "2" # set to "0" to disable optimization xelab.Parameters[xelab.SwitchDebug] = "typical" xelab.Parameters[xelab.SwitchSnapshot] = testbench.ModuleName xelab.Parameters[ xelab. SwitchVerbose] = "1" if self.Logger.LogLevel is Severity.Debug else "0" # set to "1" for detailed messages xelab.Parameters[xelab.SwitchProjectFile] = str(prjFilePath) xelab.Parameters[xelab.SwitchLogFile] = str(xelabLogFilePath) xelab.Parameters[xelab.ArgTopLevel] = "{0}.{1}".format( VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName) try: xelab.Link() except DryRunException: pass except VivadoException as ex: raise SimulatorException( "Error while analysing '{0!s}'.".format(prjFilePath)) from ex if xelab.HasErrors: raise SkipableSimulatorException( "Error while analysing '{0!s}'.".format(prjFilePath))
def _RunSimulation(self, testbench): # mccabe:disable=MC0001 # select modelsim.ini from precompiled precompiledModelsimIniPath = self.Directories.PreCompiled device_vendor = self._pyIPCMIProject.Board.Device.Vendor if device_vendor is Vendors.Altera: precompiledModelsimIniPath /= self.Host.Config[ 'CONFIG.DirectoryNames']['AlteraSpecificFiles'] elif device_vendor is Vendors.Lattice: precompiledModelsimIniPath /= self.Host.Config[ 'CONFIG.DirectoryNames']['LatticeSpecificFiles'] elif device_vendor is Vendors.Xilinx: precompiledModelsimIniPath /= self.Host.Config[ 'CONFIG.DirectoryNames']['XilinxSpecificFiles'] precompiledModelsimIniPath /= "modelsim.ini" if not precompiledModelsimIniPath.exists(): raise SimulatorException("ModelSim ini file '{0!s}' not found.".format(precompiledModelsimIniPath)) \ from FileNotFoundError(str(precompiledModelsimIniPath)) simBuildPath = self.Directories.Working / self.COCOTB_SIMBUILD_DIRECTORY # create temporary directory for Cocotb if not existent if (not (simBuildPath).exists()): self.LogVerbose("Creating build directory for simulator files.") self.LogDebug("Build directory: {0!s}".format(simBuildPath)) try: simBuildPath.mkdir(parents=True) except OSError as ex: raise SimulatorException( "Error while creating '{0!s}'.".format( simBuildPath)) from ex # write local modelsim.ini modelsimIniPath = simBuildPath / "modelsim.ini" if modelsimIniPath.exists(): try: modelsimIniPath.unlink() except OSError as ex: raise SimulatorException( "Error while deleting '{0!s}'.".format( modelsimIniPath)) from ex with modelsimIniPath.open('w') as fileHandle: fileContent = dedent("""\ [Library] others = {0!s} """).format(precompiledModelsimIniPath) fileHandle.write(fileContent) # self.LogNormal("Running simulation...") cocotbTemplateFilePath = self.Host.Directories.Root / \ self.Host.Config[testbench.ConfigSectionName]['CocotbMakefile'] # depends on testbench topLevel = testbench.TopLevel cocotbModule = testbench.ModuleName # create one VHDL line for each VHDL file vhdlSources = "" for file in self._pyIPCMIProject.Files( fileType=FileTypes.VHDLSourceFile): if (not file.Path.exists()): raise SimulatorException("Cannot add '{0!s}' to Cocotb Makefile.".format(file.Path)) \ from FileNotFoundError(str(file.Path)) vhdlSources += str(file.Path) + " " # copy Cocotb (Python) files to temp directory self.LogVerbose( "Copying Cocotb (Python) files into temporary directory.") cocotbTempDir = str(self.Directories.Working) for file in self._pyIPCMIProject.Files( fileType=FileTypes.CocotbSourceFile): if (not file.Path.exists()): raise SimulatorException("Cannot copy '{0!s}' to Cocotb temp directory.".format(file.Path)) \ from FileNotFoundError(str(file.Path)) self.LogDebug("copy {0!s} {1}".format(file.Path, cocotbTempDir)) try: shutil_copy(str(file.Path), cocotbTempDir) except OSError as ex: raise SimulatorException("Error while copying '{0!s}'.".format( file.Path)) from ex # read/write Makefile template self.LogVerbose("Generating Makefile...") self.LogDebug( "Reading Cocotb Makefile template file from '{0!s}'".format( cocotbTemplateFilePath)) with cocotbTemplateFilePath.open('r') as fileHandle: cocotbMakefileContent = fileHandle.read() cocotbMakefileContent = cocotbMakefileContent.format( pyIPCMIRootDirectory=str(self.Host.Directories.Root), VHDLSources=vhdlSources, TopLevel=topLevel, CocotbModule=cocotbModule) cocotbMakefilePath = self.Directories.Working / "Makefile" self.LogDebug( "Writing Cocotb Makefile to '{0!s}'".format(cocotbMakefilePath)) with cocotbMakefilePath.open('w') as fileHandle: fileHandle.write(cocotbMakefileContent) # execute make make = Make(self.Host.Platform, self.DryRun, logger=self.Logger) if (SimulationSteps.ShowWaveform in self._simulationSteps): make.Parameters[Make.SwitchGui] = 1 testbench.Result = make.RunCocotb()
def _RunAnalysis(self, _): # create a VHDLCompiler instance vlib = self._toolChain.GetVHDLLibraryTool() for lib in self._pyIPCMIProject.VHDLLibraries: vlib.Parameters[vlib.SwitchLibraryName] = lib.Name try: vlib.CreateLibrary() except DryRunException: pass # create a VHDLCompiler instance vcom = self._toolChain.GetVHDLCompiler() vcom.Parameters[vcom.FlagQuietMode] = True vcom.Parameters[vcom.FlagExplicit] = True vcom.Parameters[vcom.FlagRangeCheck] = True vcom.Parameters[ vcom.SwitchModelSimIniFile] = self.ModelSimIniPath.as_posix() vcom.Parameters[vcom.SwitchVHDLVersion] = repr(self._vhdlVersion) if (self._withCoverage is True): vcom.Parameters[ vcom. SwitchCoverage] = VHDLCompilerCoverageOptions.All and not VHDLCompilerCoverageOptions.Toggle vcom.Parameters[ vcom. SwitchFSMVerbosityLevel] = VHDLCompilerFSMVerbosityLevel.Default recompileScriptContent = dedent("""\ puts "Recompiling..." """) # run vcom compile for each VHDL file for file in self._pyIPCMIProject.Files( fileType=FileTypes.VHDLSourceFile): if (not file.Path.exists()): raise SimulatorException("Cannot analyse '{0!s}'.".format( file.Path)) from FileNotFoundError(str(file.Path)) vcomLogFile = self.Directories.Working / (file.Path.stem + ".vcom.log") vcom.Parameters[vcom.SwitchVHDLLibrary] = file.LibraryName vcom.Parameters[vcom.ArgLogFile] = vcomLogFile vcom.Parameters[vcom.ArgSourceFile] = file.Path try: vcom.Compile() except ModelSimException as ex: raise SimulatorException( "Error while compiling '{0!s}'.".format(file.Path)) from ex if vcom.HasErrors: raise SkipableSimulatorException( "Error while compiling '{0!s}'.".format(file.Path)) # delete empty log files if (vcomLogFile.exists() and vcomLogFile.stat().st_size == 0): try: vcomLogFile.unlink() except OSError as ex: raise SimulatorException( "Error while deleting '{0!s}'.".format( vcomLogFile)) from ex # collecting all compile commands in a buffer recompileScriptContent += dedent("""\ puts " Compiling '{file}'..." {tcl} """).format(file=file.Path.as_posix(), tcl=vcom.GetTclCommand()) recompileScriptContent += dedent("""\ puts "Recompilation done" puts "Restarting simulation..." restart -force puts "Simulation is restarted." """) recompileScriptContent = recompileScriptContent.replace( "\\", "/") # WORKAROUND: to convert all paths to Tcl compatible paths. recompileScriptPath = self.Directories.Working / "recompile.do" self.LogDebug( "Writing recompile script to '{0!s}'".format(recompileScriptPath)) with recompileScriptPath.open('w') as fileHandle: fileHandle.write(recompileScriptContent)
def _RunSimulationWithGUI(self, testbench): raise SimulatorException("GUI mode is not supported for Active-HDL.")
def _RunSimulationWithGUI(self, testbench): tclGUIFilePath = self.Host.Directories.Root / self.Host.Config[ testbench.ConfigSectionName]['vSimGUIScript'] tclWaveFilePath = self.Host.Directories.Root / self.Host.Config[ testbench.ConfigSectionName]['vSimWaveScript'] tclDefaultGUIFilePath = self.Host.Directories.Root / self.Host.Config[ testbench.ConfigSectionName]['vSimDefaultGUIScript'] tclDefaultWaveFilePath = self.Host.Directories.Root / self.Host.Config[ testbench.ConfigSectionName]['vSimDefaultWaveScript'] # create a VHDLSimulator instance vsim = self._toolChain.GetSimulator() vsim.Parameters[ vsim.SwitchModelSimIniFile] = self.ModelSimIniPath.as_posix() # vsim.Parameters[vsim.FlagEnableOptimization] = True # FIXME: vsim.Parameters[vsim.FlagReportAsError] = "3473" vsim.Parameters[vsim.SwitchTimeResolution] = "1fs" vsim.Parameters[vsim.FlagGuiMode] = True vsim.Parameters[vsim.SwitchTopLevel] = "{0}.{1}".format( VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName) # vsim.Parameters[vsim.SwitchTitle] = testbenchName vsimDefaultWaveCommands = "add wave *" # find a Tcl batch script to load predefined signals in the waveform window vsimBatchCommand = "" self.LogDebug("'{0!s}'\n '{1!s}'".format( tclWaveFilePath, self.Host.Directories.Root)) if (tclWaveFilePath != self.Host.Directories.Root): if (tclWaveFilePath.exists()): self.LogDebug( "Found waveform script: '{0!s}'".format(tclWaveFilePath)) vsimBatchCommand = "do {0};".format(tclWaveFilePath.as_posix()) elif (tclDefaultWaveFilePath != self.Host.Directories.Root): if (tclDefaultWaveFilePath.exists()): self.LogDebug( "Found default waveform script: '{0!s}'".format( tclDefaultWaveFilePath)) vsimBatchCommand = "do {0};".format( tclDefaultWaveFilePath.as_posix()) else: self.LogDebug( "Couldn't find default waveform script: '{0!s}'. Loading default command '{1}'." .format(tclDefaultWaveFilePath, vsimDefaultWaveCommands)) vsimBatchCommand = "{0};".format(vsimDefaultWaveCommands) else: self.LogDebug( "Couldn't find waveform script: '{0!s}'. Loading default command '{1}'." .format(tclWaveFilePath, vsimDefaultWaveCommands)) vsim.Parameters[vsim.SwitchBatchCommand] = "{0};".format( vsimDefaultWaveCommands) elif (tclDefaultWaveFilePath != self.Host.Directories.Root): if (tclDefaultWaveFilePath.exists()): self.LogDebug( "Falling back to default waveform script: '{0!s}'".format( tclDefaultWaveFilePath)) vsimBatchCommand = "do {0};".format( tclDefaultWaveFilePath.as_posix()) else: self.LogDebug( "Couldn't find default waveform script: '{0!s}'. Loading default command '{1}'." .format(tclDefaultWaveFilePath, vsimDefaultWaveCommands)) vsimBatchCommand = "{0};".format(vsimDefaultWaveCommands) else: self.LogWarning( "No waveform script specified. Loading default command '{0}'.". format(vsimDefaultWaveCommands)) vsimBatchCommand = "{0};".format(vsimDefaultWaveCommands) # find a Tcl batch script for the GUI mode vsimRunScript = "" if (tclGUIFilePath.exists()): self.LogDebug("Found Tcl script for GUI mode: '{0!s}'".format( tclGUIFilePath)) vsimRunScript = tclGUIFilePath.as_posix() vsimBatchCommand += "do {0};".format(vsimRunScript) elif (tclDefaultGUIFilePath.exists()): self.LogDebug( "Falling back to default Tcl script for GUI mode: '{0!s}'". format(tclDefaultGUIFilePath)) vsimRunScript = tclDefaultGUIFilePath.as_posix() vsimBatchCommand += "do {0};".format(vsimRunScript) else: raise ModelSimException("No Tcl batch script for GUI mode found.") \ from FileNotFoundError(str(tclDefaultGUIFilePath)) vsim.Parameters[vsim.SwitchBatchCommand] = vsimBatchCommand # writing a relaunch file recompileScriptPath = self.Directories.Working / "recompile.do" relaunchScriptPath = self.Directories.Working / "relaunch.do" saveWaveformScriptPath = self.Directories.Working / "saveWaveform.do" relaunchScriptContent = dedent("""\ puts "Loading recompile script '{recompileScript}'..." do {recompileScript} puts "Loading run script '{runScript}'..." do {runScript} """).format(recompileScript=recompileScriptPath.as_posix(), runScript=vsimRunScript) self.LogDebug( "Writing relaunch script to '{0!s}'".format(relaunchScriptPath)) with relaunchScriptPath.open('w') as fileHandle: fileHandle.write(relaunchScriptContent) # writing a saveWaveform file saveWaveformScriptContent = dedent("""\ puts "Saving waveform settings to '{waveformFile}'..." write format wave -window .main_pane.wave.interior.cs.body.pw.wf {waveformFile} """).format(waveformFile=tclWaveFilePath.as_posix()) self.LogDebug("Writing saveWaveform script to '{0!s}'".format( saveWaveformScriptPath)) with saveWaveformScriptPath.open('w') as fileHandle: fileHandle.write(saveWaveformScriptContent) try: testbench.Result = vsim.Simulate() except DryRunException: pass except ModelSimException as ex: raise SimulatorException( "Error while simulating '{0}.{1}'.".format( VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName)) from ex if vsim.HasErrors: raise SkipableSimulatorException( "Error while simulating '{0}.{1}'.".format( VHDL_TESTBENCH_LIBRARY_NAME, testbench.ModuleName))
def _RunSimulation(self, testbench): """""" # create a GHDLRun instance ghdl = self._toolChain.GetGHDLRun() ghdl.Parameters[ghdl.FlagVerbose] = (self.Logger.LogLevel is Severity.Debug) ghdl.Parameters[ghdl.FlagExplicit] = True ghdl.Parameters[ghdl.FlagRelaxedRules] = True ghdl.Parameters[ghdl.FlagWarnBinding] = True ghdl.Parameters[ghdl.FlagNoVitalChecks] = True ghdl.Parameters[ghdl.FlagMultiByteComments] = True ghdl.Parameters[ghdl.FlagSynBinding] = True ghdl.Parameters[ghdl.FlagPSL] = True ghdl.Parameters[ghdl.SwitchVHDLLibrary] = VHDL_TESTBENCH_LIBRARY_NAME ghdl.Parameters[ghdl.ArgTopLevel] = testbench.ModuleName self._SetVHDLVersionAndIEEEFlavor(ghdl) self._SetExternalLibraryReferences(ghdl) # configure RUNOPTS ghdl.RunOptions[ ghdl. SwitchIEEEAsserts] = "disable-at-0" # enable, disable, disable-at-0 # set dump format to save simulation results to *.vcd file if (SimulationSteps.ShowWaveform in self._simulationSteps): configSection = self.Host.Config[testbench.ConfigSectionName] testbench.WaveformOptionFile = Path( configSection['ghdlWaveformOptionFile']) testbench.WaveformFileFormat = configSection[ 'ghdlWaveformFileFormat'] if (testbench.WaveformFileFormat == "vcd"): waveformFilePath = self.Directories.Working / ( testbench.ModuleName + ".vcd") ghdl.RunOptions[ghdl.SwitchVCDWaveform] = waveformFilePath elif (testbench.WaveformFileFormat == "vcdgz"): waveformFilePath = self.Directories.Working / ( testbench.ModuleName + ".vcd.gz") ghdl.RunOptions[ghdl.SwitchVCDGZWaveform] = waveformFilePath elif (testbench.WaveformFileFormat == "fst"): waveformFilePath = self.Directories.Working / ( testbench.ModuleName + ".fst") ghdl.RunOptions[ghdl.SwitchFSTWaveform] = waveformFilePath elif (testbench.WaveformFileFormat == "ghw"): waveformFilePath = self.Directories.Working / ( testbench.ModuleName + ".ghw") ghdl.RunOptions[ghdl.SwitchGHDLWaveform] = waveformFilePath else: raise SimulatorException( "Unknown waveform file format for GHDL.") testbench.WaveformFile = waveformFilePath if testbench.WaveformOptionFile.exists(): ghdl.RunOptions[ ghdl. SwitchWaveformOptionFile] = testbench.WaveformOptionFile try: testbench.Result = ghdl.Run() except DryRunException: pass