def __init__(self, width, module_name, module_mif_filename):
print "Running vector test on module %s with mif file %s" % (module_name, module_mif_filename)
self.test_reset = pycdl.wire()
self.vector_input_0 = pycdl.wire(width)
self.vector_input_1 = pycdl.wire(width)
self.vector_output_0 = pycdl.wire(width)
self.vector_output_1 = pycdl.wire(width)
self.system_clock = pycdl.clock(0, 1, 1)
self.dut_0 = pycdl.module(module_name,
clocks={ "io_clock": self.system_clock },
inputs={ "io_reset": self.test_reset,
"vector_input_0": self.vector_input_0,
"vector_input_1": self.vector_input_1 },
outputs={ "vector_output_0": self.vector_output_0,
"vector_output_1": self.vector_output_1 })
self.test_harness_0 = vector_test_harness(clocks={ "clock": self.system_clock },
inputs={ "vector_output_0": self.vector_output_0,
"vector_output_1": self.vector_output_1 },
outputs={ "vector_input_0": self.vector_input_0,
"vector_input_1": self.vector_input_1 },
vectors_filename=module_mif_filename)
self.rst_seq = pycdl.timed_assign(self.test_reset, 1, 5, 0)
pycdl.hw.__init__(self, self.dut_0, self.test_harness_0, self.system_clock, self.rst_seq)
def __init__(self, sram_mif=""):
system_clock = pycdl.clock(0, 5, 5)
reset_n = pycdl.wire()
self.reset_driver = pycdl.timed_assign(signal=reset_n,
init_value=0,
wait=33,
later_value=1)
hw_forces = dict()
hw_forces = {
"imem.filename": sram_mif,
"imem.verbose": 0,
}
self.tb_6502 = pycdl.module(
"tb_6502",
clocks={
"clk": system_clock,
},
inputs={
"reset_n": reset_n,
},
forces=hw_forces,
)
self.th = cdl_test_th(clocks={"clk": system_clock},
inputs={},
outputs={})
pycdl.hw.__init__(self, self.tb_6502, self.th, system_clock,
self.reset_driver)
self.wave_hierarchies = [self.tb_6502]
pass
def __init__(self, bits_per_enable, mif_filename, tv_filename):
print "Regression batch arg mif:%s" % mif_filename
print "Regression batch arg bits_per_enable:%d" % bits_per_enable
print "Regression batch arg tv_file:%s" % tv_filename
print "Running dual port SRAM test on 1024x16 %d bits per enable mrw sram mif file %s test vector file %s" % (bits_per_enable, mif_filename, tv_filename)
if bits_per_enable == 8:
self.byte_enables_0 = pycdl.wire(2)
self.byte_enables_1 = pycdl.wire(2)
else:
self.byte_enables_0 = pycdl.wire(1)
self.byte_enables_1 = pycdl.wire(1)
self.test_reset = pycdl.wire()
self.sram_rd_0 = pycdl.wire(16)
self.address_0 = pycdl.wire(10)
self.read_not_write_0 = pycdl.wire()
self.write_data_0 = pycdl.wire(16)
self.sram_rd_1 = pycdl.wire(16)
self.address_1 = pycdl.wire(10)
self.read_not_write_1 = pycdl.wire()
self.write_data_1 = pycdl.wire(16)
self.system_clock = pycdl.clock(0, 1, 1)
sram_inputs={ "address_0": self.address_0,
"read_not_write_0": self.read_not_write_0,
"write_data_0": self.write_data_0,
"address_1": self.address_1,
"read_not_write_1": self.read_not_write_1,
"write_data_1": self.write_data_1 }
if bits_per_enable != 0:
sram_inputs["write_enable_0"] = self.byte_enables_0
sram_inputs["write_enable_1"] = self.byte_enables_1
self.sram = pycdl.module("se_sram_mrw",
options={ "filename": mif_filename,
"num_ports": 2,
"size": 1024,
"width": 16,
"bits_per_enable": bits_per_enable,
"verbose": 0 },
clocks={ "sram_clock_0": self.system_clock,
"sram_clock_1": self.system_clock },
inputs=sram_inputs,
outputs={ "data_out_0": self.sram_rd_0,
"data_out_1": self.sram_rd_1 })
self.test_harness_0 = dual_port_memory_th(clocks={ "clock": self.system_clock },
inputs={ "sram_rd_0": self.sram_rd_0,
"sram_rd_1": self.sram_rd_1 },
outputs={ "address_0": self.address_0,
"read_not_write_0": self.read_not_write_0,
"byte_enables_0": self.byte_enables_0,
"write_data_0": self.write_data_0,
"address_1": self.address_1,
"read_not_write_1": self.read_not_write_1,
"byte_enables_1": self.byte_enables_1,
"write_data_1": self.write_data_1 },
test_vector_mif=tv_filename)
self.rst_seq = pycdl.timed_assign(self.test_reset, 1, 5, 0)
pycdl.hw.__init__(self, self.sram, self.test_harness_0, self.system_clock, self.rst_seq)
def __init__(self, test):
system_clock = pycdl.clock(0, 10, 10) # 50MHz
reset_n = pycdl.wire()
self.drivers = [
pycdl.timed_assign(signal=reset_n,
init_value=0,
wait=33,
later_value=1),
]
hw_forces = dict()
hw_forces = {
"th.clock":
"clk",
"th.inputs":
("user_inputs__temperature_alarm " +
"user_inputs__touchpanel_irq " +
"user_inputs__right_dial__direction_pulse " +
"user_inputs__right_dial__direction " +
"user_inputs__right_dial__pressed " +
"user_inputs__left_dial__direction_pulse " +
"user_inputs__left_dial__direction " +
"user_inputs__left_dial__pressed " + "user_inputs__joystick__c " +
"user_inputs__joystick__r " + "user_inputs__joystick__l " +
"user_inputs__joystick__d " + "user_inputs__joystick__u " +
"user_inputs__diamond__y " + "user_inputs__diamond__x " +
"user_inputs__diamond__b " + "user_inputs__diamond__a " +
"user_inputs__updated_switches " + "inputs_control__sr_shift " +
"inputs_control__sr_clock " + ""),
"th.outputs": ("inputs_status__right_rotary__transition_pin " +
"inputs_status__right_rotary__direction_pin " +
"inputs_status__left_rotary__transition_pin " +
"inputs_status__left_rotary__direction_pin " +
"inputs_status__sr_data " + "sr_divider[8] " + ""),
"th.object":
test,
}
self.dut = pycdl.module(
"tb_de1_cl_controls",
clocks={
"clk": system_clock,
},
inputs={
"reset_n": reset_n,
},
forces=hw_forces,
)
pycdl.hw.__init__(
self,
thread_mapping=None,
children=[
self.dut,
system_clock,
] + self.drivers,
)
self.wave_hierarchies = [self.dut]
pass
def __init__(self, test):
test.set_hw(self)
self.test = test
self.wave_file = self.__class__.__module__ + ".vcd"
self.cdl_clocks = {}
self.clock_periods = {}
for clk_pin in self.clocks:
(delay, low, high) = self.clocks[clk_pin]
if low is None: low = self.system_clock_half_period
if high is None: high = self.system_clock_half_period
self.cdl_clocks[clk_pin] = pycdl.clock(delay, low, high)
self.clock_periods[clk_pin] = low + high
pass
reset_n = pycdl.wire()
self.drivers = [
pycdl.timed_assign(signal=reset_n,
init_value=0,
wait=33,
later_value=1),
]
hw_forces = dict(self.th_forces.items())
hw_forces["th.object"] = test
self.dut = pycdl.module(
self.module_name,
clocks=self.cdl_clocks,
inputs={"reset_n": reset_n},
forces=hw_forces,
)
children = [self.dut] + self.drivers
for clk_pin in self.cdl_clocks:
children.append(self.cdl_clocks[clk_pin])
pass
for l in self.loggers:
log_module = pycdl.module("se_logger", options=self.loggers[l])
children.append(log_module)
pass
pycdl.hw.__init__(
self,
thread_mapping=None,
children=children,
)
self.wave_hierarchies = [self.dut]
pass
def __init__(self, module_name, test_name, test_vectors, width):
print "Regression batch arg",module_name
print "Regression batch arg",test_name
#print "Running vector test on module %s with mif file %s" % (module_name, module_mif_filename)
system_clock = pycdl.clock(0, 1, 1)
test_reset = pycdl.wire( 1 )
vector_input_0 = pycdl.wire( width )
vector_input_1 = pycdl.wire( width )
vector_output_0 = pycdl.wire( width )
vector_output_1 = pycdl.wire( width )
self.reset_driver = pycdl.timed_assign( signal=test_reset,
init_value = 1,
wait=5,
later_value=0 )
self.th = vector_th( vectors = test_vectors,
clocks = { "clk": system_clock,
},
inputs = { "vector_output_0": vector_output_0,
"vector_output_1": vector_output_1,
},
outputs = { "vector_input_0": vector_input_0,
"vector_input_1": vector_input_1,
},
)
self.dut = pycdl.module( module_name,
clocks = { "io_clock": system_clock,
},
inputs = { "io_reset": test_reset,
"vector_input_0": vector_input_0,
"vector_input_1": vector_input_1,
},
outputs = { "vector_output_0": vector_output_0,
"vector_output_1": vector_output_1,
},
)
pycdl.hw.__init__(self, system_clock, self.th, self.dut, self.reset_driver )
def __init__(self,
os_rom_mif,
basic_rom_mif,
adfs_rom_mif,
teletext_rom_mif,
disk_mif="disks/elite.mif",
ps2_kbd_mif=""):
system_clock = pycdl.clock(0, 5, 5)
video_clock = pycdl.clock(0, 7, 7)
self.system_clock_div_2 = pycdl.clock(0, 10, 10)
reset_n = pycdl.wire()
hw_forces = dict()
hw_forces = {
"bbc.bbc.saa.character_rom.filename": teletext_rom_mif,
"bbc.bbc.saa.character_rom.verbose": 0,
"bbc.bbc.basic.filename": basic_rom_mif,
"bbc.bbc.basic.verbose": 0,
"bbc.bbc.adfs.filename": adfs_rom_mif,
"bbc.bbc.adfs.verbose": 0,
"bbc.bbc.ram_0.reset_type": 1,
"bbc.bbc.ram_0.reset_value": 0,
"bbc.bbc.os.filename": os_rom_mif,
"bbc.bbc.os.verbose": 0,
"bbc.io.bbc_ps2_kbd.kbd_map": ps2_kbd_mif,
"bbc.floppy.filename": disk_mif,
}
lcd = pycdl.wirebundle({
"vsync_n": 1,
"hsync_n": 1,
"display_enable": 1,
"red": 6,
"green": 7,
"blue": 6,
"backlight": 1,
})
switches = pycdl.wire(10)
leds = pycdl.wire(10)
keys = pycdl.wire(4)
video_locked = pycdl.wire(1)
led_data_pin = pycdl.wire(1)
inputs_status = pycdl.wirebundle({
"right_rotary": {
"transition_pin": 1,
"direction_pin": 1
},
"left_rotary": {
"transition_pin": 1,
"direction_pin": 1
},
})
inputs_control = pycdl.wirebundle({
"sr_shift": 1,
"sr_clock": 1,
})
self.drivers = [
pycdl.timed_assign(signal=reset_n,
init_value=0,
wait=33,
later_value=1),
pycdl.timed_assign(signal=keys,
init_value=7,
wait=33,
later_value=6),
pycdl.timed_assign(signal=video_locked,
init_value=0,
wait=133,
later_value=1),
pycdl.timed_assign(signal=switches,
init_value=0,
wait=233,
later_value=1), # remove cpu reset
]
self.bbc_micro = pycdl.module(
"bbc_micro_de1_cl",
clocks={
"clk": system_clock,
"video_clk": video_clock,
},
inputs={
"reset_n": reset_n,
"video_locked": video_locked,
"keys": keys,
"switches": switches,
"inputs_status": inputs_status,
},
outputs={
"lcd": lcd,
"leds": leds,
"inputs_control": inputs_control,
"led_data_pin": led_data_pin
},
forces=hw_forces,
)
self.th = cdl_test_th(clocks={"clk": system_clock},
inputs={},
outputs={})
self.th.bbc_hier = "bbc_micro.bbc.bbc"
self.log = pycdl.module(
"se_logger",
options={
"verbose": 1,
"filename": "itrace.log",
"modules": (
"bbc_micro.bbc.bbc.fdc "
#"bbc_micro.main_cpu "
),
})
thread_mapping = None
pycdl.hw.__init__(
self,
thread_mapping=thread_mapping,
children=[
self.bbc_micro,
self.th,
self.log,
system_clock,
self.system_clock_div_2,
] + self.drivers,
)
#self.wave_hierarchies = [self.bbc_micro]
#self.wave_hierarchies = [self.bbc_display_sram]
#self.wave_hierarchies = [self.bbc_display, self.bbc_floppy_sram, self.bbc_floppy]
self.wave_hierarchies = [self.bbc_micro]
pass
def __init__(self):
clk = pycdl.clock(0, 5, 5)
reset_n = pycdl.wire()
chip_select_n = pycdl.wire()
read_n = pycdl.wire()
write_n = pycdl.wire()
address = pycdl.wire(2)
data_in = pycdl.wire(8)
data_out = pycdl.wire(8)
data_ack_n = pycdl.wire()
ready = pycdl.wire(2)
track_0_n = pycdl.wire()
write_protect_n = pycdl.wire()
index_n = pycdl.wire()
nmi = pycdl.wire()
th_req_bus_to_drive = pycdl.wire()
th_req_drive_to_bus = pycdl.wire()
self.reset_driver = pycdl.timed_assign(signal=reset_n,
init_value=0,
wait=193,
later_value=1)
hw_forces = dict()
hw_forces = {}
bbc_drive_op = pycdl.wirebundle({
"sector_id": {
"deleted_data": 1,
"bad_data_crc": 1,
"bad_crc": 1,
"sector_length": 2,
"sector_number": 6,
"head": 1,
"track": 7,
},
"write_sector_id_enable": 1,
"write_data": 32,
"write_data_enable": 1,
"read_data_enable": 1,
"next_id": 1,
"step_in": 1,
"step_out": 1,
})
bbc_drive_response = pycdl.wirebundle({
"sector_id": {
"deleted_data": 1,
"bad_data_crc": 1,
"bad_crc": 1,
"sector_length": 2,
"sector_number": 6,
"head": 1,
"track": 7,
},
"index": 1,
"sector_id_valid": 1,
"read_data_valid": 1,
"read_data": 32,
"track_zero": 1,
"disk_ready": 1,
"write_protect": 1,
})
self.dut = pycdl.module(
"fdc8271",
clocks={
"clk": clk,
},
inputs={
"reset_n": reset_n,
"read_n": read_n,
"write_n": write_n,
"chip_select_n": chip_select_n,
"address": address,
"data_in": data_in,
"data_ack_n": data_ack_n,
"ready": ready,
"track_0_n": track_0_n,
"write_protect_n": write_protect_n,
"index_n": index_n,
"bbc_floppy_response": bbc_drive_response,
},
outputs={
"data_out": data_out,
"irq_n": nmi,
"bbc_floppy_op": bbc_drive_op,
},
forces=hw_forces,
)
self.th_drive = pycdl.module(
"bbc_floppy",
clocks={
"clk": clk,
},
inputs={
"floppy_op": bbc_drive_op,
#"th_acknowledge":th_req_bus_to_drive,
},
outputs={
"floppy_response": bbc_drive_response,
# "th_request":th_req_drive_to_bus,
},
)
self.th_bus = th_8271_bus(
clocks={
"clk": clk,
},
inputs={
"data_out": data_out,
"nmi": nmi,
},
outputs={
"read_n": read_n,
"write_n": write_n,
"chip_select_n": chip_select_n,
"address": address,
"data_in": data_in,
"data_ack_n": data_ack_n,
"ready": ready,
"track_0_n": track_0_n,
"write_protect_n": write_protect_n,
"index_n": index_n,
"th_request": th_req_bus_to_drive,
},
)
self.th_bus.hw = self
self.th_drive.hw = self
thread_mapping = None
pycdl.hw.__init__(
self,
thread_mapping=thread_mapping,
children=[
self.dut, self.th_drive, self.th_bus, clk, self.reset_driver
],
)
self.wave_hierarchies = [
self.dut,
self.th_bus,
self.th_drive,
]
pass
def __init__(self):
clk_2MHz = pycdl.clock(0, 5, 5)
clk_1MHz_falling = pycdl.clock(0, 10, 10)
reset_n = pycdl.wire()
read_not_write = pycdl.wire()
chip_select_n = pycdl.wire()
address = pycdl.wire()
data_in = pycdl.wire(8)
lpstb_n = pycdl.wire()
crtc_clock_enable = pycdl.wire()
ma = pycdl.wire(14)
ra = pycdl.wire(5)
data_out = pycdl.wire(8)
display_enable = pycdl.wire()
cursor = pycdl.wire()
hsync = pycdl.wire()
vsync = pycdl.wire()
th_req_bus_to_pixel = pycdl.wire()
th_req_pixel_to_bus = pycdl.wire()
self.reset_driver = pycdl.timed_assign(signal=reset_n,
init_value=0,
wait=193,
later_value=1)
hw_forces = dict()
hw_forces = {}
display = pycdl.wirebundle({
"clock_enable": 1,
"hsync": 1,
"vsync": 1,
"pixels_per_clock": 3,
"green": 8,
"red": 8,
"blue": 8
})
self.dut = pycdl.module(
"crtc6845",
clocks={
"clk_2MHz": clk_2MHz,
"clk_1MHz": clk_1MHz_falling,
},
inputs={
"reset_n": reset_n,
"read_not_write": read_not_write,
"chip_select_n": chip_select_n,
"rs": address,
"data_in": data_in,
"lpstb_n": lpstb_n,
"crtc_clock_enable": crtc_clock_enable,
},
outputs={
"data_out": data_out,
"ma": ma,
"ra": ra,
"de": display_enable,
"cursor": cursor,
"hsync": hsync,
"vsync": vsync,
},
forces=hw_forces,
)
self.th_pixels = th_6845_pixels(
clocks={"clk": clk_2MHz},
inputs={
"ma": ma,
"ra": ra,
"de": display_enable,
"cursor": cursor,
"hsync": hsync,
"vsync": vsync,
"th_acknowledge": th_req_bus_to_pixel,
},
outputs={
"lpstb_n": lpstb_n,
"crtc_clock_enable": crtc_clock_enable,
"th_request": th_req_pixel_to_bus,
},
)
self.th_bus = th_6845_bus(
clocks={
"clk": clk_1MHz_falling,
},
inputs={
"data_out": data_out,
"th_acknowledge": th_req_pixel_to_bus,
},
outputs={
"read_not_write": read_not_write,
"chip_select_n": chip_select_n,
"address": address,
"data_in": data_in,
"th_request": th_req_bus_to_pixel,
},
)
self.th_bus.hw = self
self.th_pixels.hw = self
thread_mapping = None
pycdl.hw.__init__(
self,
thread_mapping=thread_mapping,
children=[
self.dut, self.th_pixels, self.th_bus, clk_2MHz,
clk_1MHz_falling, self.reset_driver
],
)
self.wave_hierarchies = [self.dut, self.th_bus, self.th_pixels]
pass
