def test_openQL_config_valid(self):
test_config_fn = os.path.join(curdir, 'test_gen_cfg_CCL.json')
generate_config(filename=test_config_fn,
mw_pulse_duration=20, ro_duration=300,
init_duration=200000)
# If this compiles we conclude that the generated config is valid
sqo.AllXY(qubit_idx=0, platf_cfg=test_config_fn)
mqo.single_flux_pulse_seq(qubit_indices=(2, 0),
platf_cfg=test_config_fn)
def test_openQL_config_valid(self):
test_config_fn = os.path.join(curdir, 'test_gen_cfg_CCL.json')
generate_config(filename=test_config_fn,
mw_pulse_duration=20, ro_duration=300,
init_duration=200000)
# If this compiles we conclude that the generated config is valid
# A single qubit sequence
sqo.AllXY(qubit_idx=0, platf_cfg=test_config_fn)
# A sequence containing two-qubit gates
mqo.single_flux_pulse_seq(qubit_indices=(2, 0),
platf_cfg=test_config_fn)
# A sequence containing controlled operations
sqo.RTE(qubit_idx=0,
sequence_type='echo', net_gate='pi', feedback=True,
platf_cfg=test_config_fn)
def test_generate_qi_config(self):
test_config_fn = os.path.join(curdir, 'test_gen_qi_cfg.json')
rot_dict = generate_config_qi(filename=test_config_fn,
mw_pulse_duration=20, ro_duration=300,
init_duration=200000)
# If this compiles we conclude that the generated config is valid
# A single qubit sequence
sqo.AllXY(qubit_idx=0, platf_cfg=test_config_fn)
# A sequence containing two-qubit gates
mqo.single_flux_pulse_seq(qubit_indices=(2, 0),
platf_cfg=test_config_fn)
# conditional sequence does not work because of bad config
# # A sequence containing controlled operations
# sqo.RTE(qubit_idx=0,
# sequence_type='echo', net_gate='pi', feedback=True,
# platf_cfg=test_config_fn)
print(rot_dict)
def test_allxy(self):
# Only test if it compiles
p = sqo.AllXY(qubit_idx=0, platf_cfg=self.config_fn)
self.assertEqual(p.name, 'AllXY')
sel = int(sys.argv[1])
# constants
ip = '192.168.0.241'
qubit_idx = 10
curdir = os.path.dirname(__file__)
cfg_openql_platform_fn = os.path.join(curdir, 'demo1_cfg.json')
log = logging.getLogger(__name__)
log.setLevel(logging.DEBUG)
if sel == 0: # ALLXY
# based on CCL_Transmon.py::measure_allxy()
log.debug('compiling allxy')
p = sqo.AllXY(qubit_idx=qubit_idx,
double_points=True,
platf_cfg=cfg_openql_platform_fn)
print(p.filename)
if sel == 1: # Ramsey
# based on CCL_Transmon.py::measure_ramsey()
# funny default is because there is no real time sideband
# modulation
log.debug('compiling Ramsey')
T2_star = 20e-6
cfg_cycle_time = 20e-9
stepsize = (T2_star * 4 / 61) // (abs(cfg_cycle_time)) \
* abs(cfg_cycle_time)
times = np.arange(0, T2_star * 4, stepsize)
p = sqo.Ramsey(times,
qubit_idx=qubit_idx,
def test_allxy(self):
# Only test if it compiles
sqo.AllXY(qubit_idx=0, platf_cfg=config_fn)
