def drvgen(top, intfdef, outdir): xparams = [] for name, usr_axip in intfdef.items(): if usr_axip.t == 'axidma': xparams.append(f'"C_{name.upper()}_CTRL_BASEADDR"') elif usr_axip.t == 'axi': xparams.append(f'"C_{name.upper()}_BASEADDR"') modinst = reg['hdlgen/map'][top] drvname = modinst.module_name files_dir = os.path.join(os.path.dirname(__file__), '..', 'drivers') env = TemplateEnv(files_dir) context = {'module_name': drvname, 'params': ' '.join(xparams)} files = [] outdir = os.path.join(outdir, f'{drvname}_v1_0') datadir = os.path.join(outdir, 'data') srcdir = os.path.join(outdir, 'src') os.makedirs(datadir, exist_ok=True) os.makedirs(srcdir, exist_ok=True) files.append( save_file(f'{drvname}.mdd', datadir, env.render('.', 'drvgen_mdd.j2', context))) files.append( save_file(f'{drvname}.tcl', datadir, env.render('.', 'drvgen_tcl.j2', context))) context = {'module_name': drvname, 'intfdef': intfdef} files.append( save_file(f'{drvname}.h', srcdir, env.render('.', 'drvgen_new_h.j2', context))) files.append( save_file(f'{drvname}.c', srcdir, env.render('.', 'drvgen_new_c.j2', context))) files.append( copy_file('Makefile', srcdir, os.path.join(files_dir, 'Makefile'))) files.append( copy_file('pgaxi.c', srcdir, os.path.join(files_dir, 'pgaxi.c'))) files.append( copy_file('pgaxi.h', srcdir, os.path.join(files_dir, 'pgaxi.h'))) return files
def before_setup(self, sim): basedir = os.path.dirname(__file__) tenv = TemplateEnv(basedir) self.create_svrand_top() register_intf(SVServerModule(self.outdir, self.constraints, tenv)) for c in self.constraints: c.index = register_intf(SVServerIntf()) self.conn = reg['sim/svsock/server'] self.send_cmd = self.conn.send_cmd self.dtype_recv = self.conn.dtype_recv
def setup(self): basedir = os.path.dirname(__file__) tenv = TemplateEnv(basedir) tenv.snippets = tenv.load(basedir, 'svsock_intf.j2').module for cp in self.in_cosim_ports: sock_id = register_intf(SVServerIntf(cp.port, tenv)) self.handlers[cp.port.basename] = SimSocketInputDrv(cp.port, sock_id) for p in self.gear.out_ports: sock_id = register_intf(SVServerIntf(p, tenv)) self.handlers[p.basename] = SimSocketOutputDrv(p, sock_id) register_intf(SVServerModule(self.rtl_node, tenv, self.srcdir, rst=self.rst)) self.conn = reg['sim/svsock/server'] self.send_cmd = self.conn.send_cmd super().setup()
def generate(top, intfdef): files = set() if isinstance(top, str): top = find(top) modinst = reg['hdlgen/map'][top] sigs = [] for s in top.signals.values(): if s.name == 'clk': sigs.append(InSig('aclk', 1)) elif s.name == 'rst': sigs.append(InSig('aresetn', 1)) else: sigs.append(s) intfs = {p['name']: p for p in get_port_intfs(top)} for i in intfs.values(): dtype = i['type'] w_data = i['width'] w_eot = 0 if typeof(dtype, Queue): w_data = dtype.data.width w_eot = int(dtype.eot) i['w_data'] = w_data i['w_eot'] = w_eot defs = [] for name, p in intfdef.items(): if p.t == 'axidma': params = {n: c.params for n, c in p.comp.items()} defs.extend( axi_intfs.port_def(axi_intfs.AXI_MASTER, name, **params)) params = { n: c.params for n, c in intfdef[f'{name}_ctrl'].comp.items() } defs.extend( axi_intfs.port_def(axi_intfs.AXIL_SLAVE, f'{name}_ctrl', **params)) files.update({'sfifo.v', 'axi_addr.v', 'skidbuffer.v'}) if 'rdata' in p.comp: files.add('aximm2s.v') if 'wdata' in p.comp: files.add('axis2mm.v') elif p.t in ['bram', 'bram.req', 'axi']: params = {n: c.params for n, c in p.comp.items()} pdefs = axi_intfs.port_def(axi_intfs.AXI_SLAVE, name, **params) if 'rdata' in params: files.add('axi_slave_read.v') if 'wdata' in params: files.add('axi_slave_write.v') if 'rdata' in params or 'wdata' in params: files.update({'sfifo.v', 'axi_addr.v', 'skidbuffer.v'}) defs.extend(pdefs) elif p.t == 'axis': if p.direction == 'w': tmplt = axi_intfs.AXIS_SLAVE else: tmplt = axi_intfs.AXIS_MASTER params = {n: c.params for n, c in p.comp.items()} pdefs = axi_intfs.port_def(tmplt, name, **params) defs.extend(pdefs) context = { 'wrap_module_name': f'wrap_{modinst.module_name}', 'module_name': modinst.wrap_module_name, 'inst_name': modinst.wrap_module_name, 'intfs': intfs, 'sigs': sigs, 'param_map': modinst.params if not modinst.wrapped else {}, 'port_def': defs, 'ports': intfdef } context['pg_clk'] = 'aclk' tmplt = 'wrapper.j2' base_addr = os.path.dirname(__file__) lang_dir = os.path.join(os.path.dirname(base_addr), 'sv') env = TemplateEnv(lang_dir) env.jenv.globals.update(zip=zip, ceil_pow2=ceil_pow2, ceil_div=ceil_div, bitw=bitw, ceil_chunk=ceil_chunk, axi_intfs=axi_intfs) return env.render(base_addr, tmplt, context), files
def __init__(self, top, cons=Inject('sim/svrand/constraints')): basedir = os.path.dirname(__file__) self.tenv = TemplateEnv(basedir) self.tenv.cons = self.tenv.load(basedir, 'svrand_cons.j2').module super().__init__(top, cons)
def load_jenv(): jenv = TemplateEnv(os.path.dirname(__file__)) jenv.snippets = jenv.load(jenv.basedir, 'snippet.j2').module return jenv