def compile_gear_body(gear, outdir, template_env):
# ctx, hdl_ast = parse_gear_body(gear)
from pygears.hls.translate import translate_gear
ctx, hdl_ast = translate_gear(gear)
subsvmods = []
if ctx.submodules:
from pygears.hdl import hdlgen
hdlgen_map = reg['hdlgen/map']
for c in ctx.submodules:
rtl_top = hdlgen(c.gear, outdir=outdir, generate=False)
svmod = hdlgen_map[rtl_top]
subsvmods.append(svmod)
funcs = []
def _get_funcs_rec(block):
for f_ast, f_ctx in block.funcs:
funcs.append((f_ast, f_ctx))
_get_funcs_rec(f_ast)
_get_funcs_rec(hdl_ast)
writer = HDLWriter()
write_module(ctx,
hdl_ast,
writer,
subsvmods,
funcs,
template_env,
config=gear.meta_kwds.get('hdl', {}))
return '\n'.join(writer.lines), subsvmods
def test_update_after_in_loop():
@gear(hdl={'compile': True})
async def test(din: Queue[Uint]) -> b'din':
acc = din.dtype.data(0)
async for d, eot in din:
acc = d + acc
if eot:
yield acc, eot
test(Intf(Queue[Uint[8]]))
ctx, res = translate_gear(find('/test'))
assert ctx.scope['acc'].reg
def test_optional_loop_assign():
@gear
async def test(din: Queue[Bool]) -> b'din':
flag = False
async for d, eot in din:
if d:
flag = True
yield flag
test(Intf(Queue[Bool]))
ctx, res = translate_gear(find('/test'))
assert ctx.scope['flag'].reg
def test_augmented():
@gear
async def test(din: Bool) -> Uint[8]:
cnt = Uint[8](1)
while cnt != 0:
async with din as d:
if d:
cnt += 1
else:
cnt -= 1
yield cnt
test(Intf(Bool))
ctx, res = translate_gear(find('/test'))
assert ctx.scope['cnt'].reg
def test_update_after_in_loop_ifelse_trap():
@gear
async def test(din: Queue[Uint]) -> b'din':
acc = din.dtype.data(0)
async for d, eot in din:
if d > 0:
acc = 1
else:
acc = 0
acc = d + acc
if eot:
yield acc, eot
test(Intf(Queue[Uint[8]]))
ctx, res = translate_gear(find('/test'))
assert 'acc' not in ctx.scope