def test_delay(cosim_cls, din_delay, dout_delay):
def bitfield(n):
return [int(digit) for digit in bin(n)[2:]]
seq = [bitfield(0x73), bitfield(0x00)]
init = [1, 0]
dut = get_decoupled_dut(dout_delay, reduce(f=lambda x, y: x ^ y))
verif(drv(t=Queue[Bool], seq=seq) | delay_rng(din_delay, din_delay),
drv(t=Uint[8], seq=init),
f=dut(sim_cls=cosim_cls),
ref=reduce(name='ref_model', f=lambda x, y: x ^ y),
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_accum_saturate_gear_directed(cosim_cls):
def add(x, y):
return saturate(x + y, Uint[8])
@gear
async def add_gear(x, y) -> Uint[8]:
async with x as dx, y as dy:
yield saturate(dx + dy, t=Uint[8])
accum_test(reduce(f=add_gear, sim_cls=cosim_cls), add)
def test_uint_directed(sim_cls):
init = [7, 45]
seq = [list(range(0, 100, 10)), list(range(2))]
def add(x, y):
return saturate(x + y, Uint[8])
directed(drv(t=Queue[Uint[8]], seq=seq),
drv(t=Uint[8], seq=init),
f=reduce(f=add, sim_cls=sim_cls),
ref=[freduce(add, s, i) for s, i in zip(seq, init)])
sim()
from pygears.lib import reduce, drv, check
from pygears.typing import Queue, Uint
(drv(t=Queue[Uint[8]], seq=[[0, 1, 0, 1, 0, 1, 0]]),
drv(t=Uint[8], seq=[1])) \
| reduce(f=lambda x, y: (x << 1) | y) \
| check(ref=[0xaa])
from pygears.lib import reduce, drv, check
from pygears.typing import Queue, Uint
drv(t=Queue[Uint[8]], seq=[[0xff, 0xff, 0xff, 0xff]]) \
| reduce(init=Uint[8](0), f=lambda x, y: x ^ y) \
| check(ref=[0])
