def test_zext(do_test): class A(Component): def construct(s): s.in_ = InPort(Bits32) s.out = OutPort(Bits64) @s.update def upblk(): s.out = zext(s.in_, 64) a = A() a._ref_upblk_srcs = { 'upblk' : \ """\ always_comb begin : upblk out = { { 32 { 1'b0 } }, in_ }; end\ """ } # TestVectorSimulator properties def tv_in(m, tv): m.in_ = Bits32(tv[0]) def tv_out(m, tv): assert m.out == Bits64(tv[1]) a._test_vectors = [ [42, zext(Bits32(42), 64)], [-1, zext(Bits32(-1), 64)], [-2, zext(Bits32(-2), 64)], [2, zext(Bits32(2), 64)], ] a._tv_in, a._tv_out = tv_in, tv_out a._ref_upblk_srcs_yosys = a._ref_upblk_srcs do_test(a)
def upblk(): x = zext(s)
def upblk(): s.out = zext(s, 1)
def upblk(): s.out = zext(s.in_, 4)
def upblk(): s.out = zext(s.b.out_b, 64)
def assign( a, b ): s.a = a + zext( s.counter_assign < 0, 32) assignb( b )
def assignb( b ): s.b @= b + zext(s.counter_assign < 0, 32) # never -1