def construct(s):
s.in_ = InPort(Bits32)
s.out = OutPort(Bits32)
s.config_placeholder = VerilogPlaceholderConfigs(
src_file=dirname(__file__) + '/VReg.v',
top_module='VReg',
port_map={
"in_": "d",
"out": "q",
})
s.verilog_translate_import = True
def construct(s):
s.in_ = InPort(Bits32)
s.out = OutPort(Bits32)
s.config_placeholder = VerilogPlaceholderConfigs(
src_file=dirname(__file__) + '/VUninit.v',
top_module='VUninit',
port_map={
"in_": "d",
"out": "q",
})
s.config_verilog_import = VerilatorImportConfigs(vl_xinit='ones', )
s.verilog_translate_import = True
def construct(s, data_width, num_entries, count_width):
s.count = OutPort(mk_bits(count_width))
s.deq_en = InPort(Bits1)
s.deq_rdy = OutPort(Bits1)
s.deq_msg = OutPort(mk_bits(data_width))
s.enq_en = InPort(Bits1)
s.enq_rdy = OutPort(Bits1)
s.enq_msg = InPort(mk_bits(data_width))
s.config_placeholder = VerilogPlaceholderConfigs(
src_file=dirname(__file__) + '/VQueue.v',
top_module='VQueue',
)
s.verilog_translate_import = True
def construct(s, nports, nbits):
s.in_ = [InPort(mk_bits(nbits)) for _ in range(nports)]
s.out = [OutPort(mk_bits(nbits)) for _ in range(nports)]
s.config_placeholder = VerilogPlaceholderConfigs(
src_file=dirname(__file__) + '/VPassThrough.v',
params={
'num_ports': nports,
'bitwidth': nbits,
},
has_clk=False,
has_reset=False,
)
s.verilog_translate_import = True
def construct(s):
s.in_ = InPort(Bits32)
s.out = OutPort(Bits32)
s.config_placeholder = VerilogPlaceholderConfigs(
src_file=dirname(__file__) + '/VReg.v',
port_map={
"clk": "clk",
"reset": "reset",
"in_": "d",
"out": "q",
})
s.config_verilog_translate = TranslationConfigs(
explicit_module_name='VReg_imported', )
s.verilog_translate_import = True
def construct(s, nbits=8):
DataType = mk_bits(nbits)
#---------------------------------------------------------------------
# Interface
#---------------------------------------------------------------------
s.in_val = InPort()
s.in_ = [InPort(DataType) for _ in range(4)]
s.out_val = OutPort()
s.out = [OutPort(DataType) for _ in range(4)]
#---------------------------------------------------------------------
# Configurations
#---------------------------------------------------------------------
s.config_placeholder = VerilogPlaceholderConfigs(
# Path to the Verilog source file
src_file=os.path.dirname(__file__) + '/SortUnitStructRTL.v',
# Name of the Verilog top level module
top_module='tut4_verilog_sort_SortUnitStructRTL',
# Parameters of the Verilog module
params={'p_nbits': nbits},
# Port name map
port_map={
'in_val': 'in_val',
'in_[0]': 'in0',
'in_[1]': 'in1',
'in_[2]': 'in2',
'in_[3]': 'in3',
'out_val': 'out_val',
'out[0]': 'out0',
'out[1]': 'out1',
'out[2]': 'out2',
'out[3]': 'out3',
},
)
s.config_verilog_import = VerilatorImportConfigs(
# Enable native Verilog line trace through Verilator
vl_line_trace=False, )
s.config_verilog_translate = TranslationConfigs(
translate=False,
explicit_module_name=f'SortUnitStructRTL_{nbits}bit',
)
def construct( s, image_column,image_row,window_size,window_size_ext):
#def construct( s ):
# Interface
s.xcel = XcelMinionIfcRTL( XcelReqMsg, XcelRespMsg )
s.mem = MemMasterIfcRTL( *mk_mem_msg(8,32,32) )
from os import path
s.config_placeholder = VerilogPlaceholderConfigs(
# Path to the Verilog source file
src_file = path.dirname(__file__) + '/Optical_flowVRTL.v',
# Name of the Verilog top level module
top_module = 'Final_Project_Optical_flowVRTL',
# Port name map
params={
'image_column':image_column,
'image_row' :image_row,
'window_size' :window_size,
'window_size_ext':window_size_ext,
},
port_map = {
'xcel.req.en' : 'xcelreq_en',
'xcel.req.rdy' : 'xcelreq_rdy',
'xcel.req.msg' : 'xcelreq_msg',
'xcel.resp.en' : 'xcelresp_en',
'xcel.resp.rdy' : 'xcelresp_rdy',
'xcel.resp.msg' : 'xcelresp_msg',
'mem.req.en' : 'memreq_en',
'mem.req.rdy' : 'memreq_rdy',
'mem.req.msg' : 'memreq_msg',
'mem.resp.en' : 'memresp_en',
'mem.resp.rdy' : 'memresp_rdy',
'mem.resp.msg' : 'memresp_msg',
},
)
s.config_verilog_import = VerilatorImportConfigs(
# Enable native Verilog line trace through Verilator
vl_line_trace = True,
)
def construct(s, nbits, nelems, nbits_cnt):
s.count = OutPort(mk_bits(nbits_cnt))
s.deq_en = InPort(Bits1)
s.deq_rdy = OutPort(Bits1)
s.deq_msg = OutPort(mk_bits(nbits))
s.enq_en = InPort(Bits1)
s.enq_rdy = OutPort(Bits1)
s.enq_msg = InPort(mk_bits(nbits))
s.config_placeholder = VerilogPlaceholderConfigs(
src_file=dirname(__file__) + '/VQueue.v',
top_module='VQueue',
params={
'data_width': nbits,
'num_entries': nelems,
'count_width': nbits_cnt,
},
)
s.verilog_translate_import = True
def construct(s):
s.imm_type = InPort(Bits3)
s.inst = InPort(Bits32)
s.imm = OutPort(Bits32)
# Verilog module setup
s.config_placeholder = VerilogPlaceholderConfigs(
src_file=path.dirname(__file__) + '/ProcDpathComponentsVRTL.v',
top_module='proc_ImmGenVRTL',
has_clk=False,
has_reset=False,
)
s.config_verilog_translate = TranslationConfigs(
translate=False,
explicit_module_name='proc_ImmGenRTL',
)
def construct(s):
# Interface
s.in_ = InPort(Bits8)
s.out = OutPort(Bits4)
# Configurations
from os import path
s.config_placeholder = VerilogPlaceholderConfigs(
# Path to the Verilog source file
src_file=path.dirname(__file__) + '/IntMulVarLatCalcShamtVRTL.v',
# Name of the Verilog top level module
top_module='lab1_imul_IntMulVarLatCalcShamtVRTL',
# Step unit does not have clk and reset pins
has_clk=False,
has_reset=False,
)
def construct(s):
# Interface
s.req_go = InPort(mk_bits(1))
s.in_x = [InPort(mk_bits(32)) for _ in range(9)]
s.in_y = [InPort(mk_bits(32)) for _ in range(9)]
s.in_t = [InPort(mk_bits(32)) for _ in range(9)]
s.vx = OutPort(mk_bits(32))
s.vy = OutPort(mk_bits(32))
s.de = OutPort(mk_bits(32))
s.result_ok = OutPort(mk_bits(32))
#s.req_msg_a=InPort(Bits32)
#s.req_msg_b=InPort(Bits1)
#s.presum =InPort(Bits32)
#s.resp_msg =OutPort(Bits32)
#s.a_shift =OutPort(Bits32)
#s.in_ = InPort (Bits8)
#s.out = OutPort (Bits4)
# Configurations
from os import path
s.config_placeholder = VerilogPlaceholderConfigs(
# Path to the Verilog source file
src_file=path.dirname(__file__) + '/matrix_operaVRTL.v',
#src_file = path.dirname(__file__) + '/IntMulVarLatCalcShamtVRTL.v',
# Name of the Verilog top level module
top_module='matrix_operaVRTL',
#top_module = 'lab1_imul_IntMulVarLatCalcShamtVRTL',
# Step unit does not have clk and reset pins
params={},
has_clk=True,
has_reset=True,
)
#edit here
s.config_verilog_translate = TranslationConfigs(
# You can leave this option unset if your rtl_language is Verilog
translate=False,
# Use the xRTL module name instead of xVRTL
explicit_module_name=f'matrix_opera',
)
def construct(s, side):
# Interface
s.en = InPort(Bits1)
s.current_frame = [
InPort(mk_bits(32)) for _ in range((side + 2) * (side + 2))
]
s.next_frame = [
InPort(mk_bits(32)) for _ in range((side + 2) * (side + 2))
]
s.Ix = [OutPort(mk_bits(32)) for _ in range(side * side)]
s.Iy = [OutPort(mk_bits(32)) for _ in range(side * side)]
s.It = [OutPort(mk_bits(32)) for _ in range(side * side)]
s.valid = OutPort(Bits1)
#s.in_ = InPort (Bits8)
#s.out = OutPort (Bits4)
# Configurations
from os import path
s.config_placeholder = VerilogPlaceholderConfigs(
# Path to the Verilog source file
src_file=path.dirname(__file__) + '/GradientVRTL.v',
#src_file = path.dirname(__file__) + '/IntMulVarLatCalcShamtVRTL.v',
# Name of the Verilog top level module
top_module='GradientVRTL',
#top_module = 'lab1_imul_IntMulVarLatCalcShamtVRTL',
# Step unit does not have clk and reset pins
params={
'side': side,
},
has_clk=False,
has_reset=False,
)
#edit here
s.config_verilog_translate = TranslationConfigs(
# You can leave this option unset if your rtl_language is Verilog
translate=False,
# Use the xRTL module name instead of xVRTL
explicit_module_name=f'Gradient',
)
def construct(s):
s.in0 = InPort(Bits32)
s.in1 = InPort(Bits32)
s.fn = InPort(Bits4)
s.out = OutPort(Bits32)
s.ops_eq = OutPort()
s.ops_lt = OutPort()
s.ops_ltu = OutPort()
# Verilog module setup
s.config_placeholder = VerilogPlaceholderConfigs(
src_file=path.dirname(__file__) + '/ProcDpathComponentsVRTL.v',
top_module='proc_AluVRTL',
has_clk=False,
has_reset=False,
)
s.config_verilog_translate = TranslationConfigs(
translate=False,
explicit_module_name='proc_AluRTL',
)
def construct(s, nports, nbits):
s.in_ = InPort(mk_bits(nbits * nports))
s.out = OutPort(mk_bits(nbits * nports))
from os import path
s.config_placeholder = VerilogPlaceholderConfigs(
src_file=path.dirname(__file__) + '/PassThroughV2VRTL.v',
# If the top module name is the same as the component class
# name it is safe to not set it.
# top_module = 'PassThroughV2VRTL',
params={
'num_ports': nports,
'bitwidth': nbits,
},
# The Verilog module does not have clk and reset
has_clk=False,
has_reset=False,
)
s.config_verilog_translate = TranslationConfigs(
# You can leave this option unset if your rtl_language is Verilog
translate=False,
# Use the xRTL module name instead of xVRTL
explicit_module_name='PassThroughV2RTL',
)
def construct(s, num_cores=1):
# Configurations
MemReqMsg, MemRespMsg = mk_mem_msg(8, 32, 32)
#---------------------------------------------------------------------
# Interface
#---------------------------------------------------------------------
# Starting F16 we turn core_id into input ports to
# enable module reusability. In the past it was passed as arguments.
s.core_id = InPort(Bits32)
# Proc/Mngr Interface
s.mngr2proc = RecvIfcRTL(Bits32)
s.proc2mngr = SendIfcRTL(Bits32)
# Instruction Memory Request/Response Interface
s.imem = MemMasterIfcRTL(MemReqMsg, MemRespMsg)
# Data Memory Request/Response Interface
s.dmem = MemMasterIfcRTL(MemReqMsg, MemRespMsg)
# Accelerator Request/Response Interface
s.xcel = XcelMasterIfcRTL(XcelReqMsg, XcelRespMsg)
# val_W port used for counting commited insts.
s.commit_inst = OutPort()
# stats_en
s.stats_en = OutPort()
from os import path
s.config_placeholder = VerilogPlaceholderConfigs(
# Path to the Verilog source file
src_file=path.dirname(__file__) + '/ProcVRTL.v',
# Name of the Verilog top level module
top_module='proc_ProcVRTL',
# Parameters of the Verilog module
params={'p_num_cores': num_cores},
# Port name map
port_map={
'core_id': 'core_id',
'commit_inst': 'commit_inst',
'stats_en': 'stats_en',
'imem.req.en': 'imemreq_en',
'imem.req.rdy': 'imemreq_rdy',
'imem.req.msg': 'imemreq_msg',
'imem.resp.en': 'imemresp_en',
'imem.resp.rdy': 'imemresp_rdy',
'imem.resp.msg': 'imemresp_msg',
'dmem.req.en': 'dmemreq_en',
'dmem.req.rdy': 'dmemreq_rdy',
'dmem.req.msg': 'dmemreq_msg',
'dmem.resp.en': 'dmemresp_en',
'dmem.resp.rdy': 'dmemresp_rdy',
'dmem.resp.msg': 'dmemresp_msg',
'xcel.req.en': 'xcelreq_en',
'xcel.req.rdy': 'xcelreq_rdy',
'xcel.req.msg': 'xcelreq_msg',
'xcel.resp.en': 'xcelresp_en',
'xcel.resp.rdy': 'xcelresp_rdy',
'xcel.resp.msg': 'xcelresp_msg',
'proc2mngr.en': 'proc2mngr_en',
'proc2mngr.rdy': 'proc2mngr_rdy',
'proc2mngr.msg': 'proc2mngr_msg',
'mngr2proc.en': 'mngr2proc_en',
'mngr2proc.rdy': 'mngr2proc_rdy',
'mngr2proc.msg': 'mngr2proc_msg',
},
)
s.config_verilog_import = VerilatorImportConfigs(
# Enable native Verilog line trace through Verilator
vl_line_trace=True, )