def test_L1_part_selection():
a = CaseConnectSliceToOutComp.DUT()
a.elaborate()
a.apply(StructuralRTLIRGenL1Pass(gen_connections(a)))
connections = a.get_metadata(StructuralRTLIRGenL1Pass.connections)
comp = sexp.CurComp(a, 's')
assert connections == \
[(sexp.PartSelection(sexp.CurCompAttr(comp, 'in_'), 4, 8), sexp.CurCompAttr(comp, 'out'))]
def test_L1_bit_selection():
a = CaseConnectBitSelToOutComp.DUT()
a.elaborate()
a.apply(StructuralRTLIRGenL1Pass(gen_connections(a)))
connections = a.get_metadata(StructuralRTLIRGenL1Pass.connections)
comp = sexp.CurComp(a, 's')
# PyMTL DSL converts bit selection into 1-bit part selection!
assert connections == \
[(sexp.PartSelection(sexp.CurCompAttr(comp, 'in_'), 0, 1), sexp.CurCompAttr(comp, 'out'))]
def test_L1_part_selection():
class A(dsl.Component):
def construct(s):
s.in_ = dsl.InPort(Bits32)
s.out = dsl.OutPort(Bits4)
dsl.connect(s.in_[4:8], s.out)
a = A()
a.elaborate()
a.apply(StructuralRTLIRGenL1Pass(*gen_connections(a)))
ns = a._pass_structural_rtlir_gen
comp = sexp.CurComp(a, 's')
assert ns.connections == \
[(sexp.PartSelection(sexp.CurCompAttr(comp, 'in_'), 4, 8), sexp.CurCompAttr(comp, 'out'))]
def test_L1_bit_selection():
class A(dsl.Component):
def construct(s):
s.in_ = dsl.InPort(Bits32)
s.out = dsl.OutPort(Bits1)
dsl.connect(s.in_[0], s.out)
a = A()
a.elaborate()
a.apply(StructuralRTLIRGenL1Pass(*gen_connections(a)))
ns = a._pass_structural_rtlir_gen
comp = sexp.CurComp(a, 's')
# PyMTL DSL converts bit selection into 1-bit part selection!
assert ns.connections == \
[(sexp.PartSelection(sexp.CurCompAttr(comp, 'in_'), 0, 1), sexp.CurCompAttr(comp, 'out'))]