def construct( s, proc_cls, xcel_cls=NullXcelRTL, dump_vcd=False,
src_delay=0, sink_delay=0,
mem_stall_prob=0, mem_latency=1 ):
s.commit_inst = OutPort( Bits1 )
req, resp = mk_mem_msg( 8, 32, 32 )
s.src = TestSrcCL ( Bits32, [], src_delay, src_delay )
s.sink = TestSinkCL( Bits32, [], sink_delay, sink_delay )
s.proc = proc_cls()
s.xcel = xcel_cls()
s.mem = MemoryCL(2, latency = mem_latency)
connect_pairs(
s.proc.commit_inst, s.commit_inst,
# Processor <-> Proc/Mngr
s.src.send, s.proc.mngr2proc,
s.proc.proc2mngr, s.sink.recv,
# Processor <-> Memory
s.proc.imem, s.mem.ifc[0],
s.proc.dmem, s.mem.ifc[1],
)
connect( s.proc.xcel, s.xcel.xcel )
def connect(s, other, parent):
# We are doing DeqIfcRTL (s) -> [ AND ] -> RecvIfcRTL (other)
# Basically we AND the rdy of both sides for enable
if isinstance(other, RecvIfcRTL):
connect(s.msg, other.msg)
m = And(Bits1)
if hasattr(parent, "deq_recv_ander_cnt"):
cnt = parent.deq_recv_ander_cnt
setattr(parent, "deq_recv_ander_" + str(cnt), m)
else:
parent.deq_recv_ander_cnt = 0
parent.deq_recv_ander_0 = m
connect_pairs(
m.in0,
s.rdy,
m.in1,
other.rdy,
m.out,
s.en,
m.out,
other.en,
)
parent.deq_recv_ander_cnt += 1
return True
return False
def connect(s, other, parent):
# We are doing SendFL (s) -> [ RecvFL -> SendCL ] -> RecvCL (s)
# SendCL is a caller interface
# FIXME direction
if isinstance( other, NonBlockingCallerIfc ) or \
isinstance( other, NonBlockingCalleeIfc ):
m = RecvFL2SendCL()
if hasattr(parent, "RecvFL2SendCL_count"):
count = parent.RecvFL2SendCL_count
setattr(parent, "RecvFL2SendCL_" + str(count), m)
else:
parent.RecvFL2SendCL_count = 0
parent.RecvFL2SendCL_0 = m
connect_pairs(
s,
m.recv,
m.send,
other,
)
parent.RecvFL2SendCL_count += 1
return True
return False
def connect(s, other, parent):
# We are doing SendRTL (s) -> [ RecvRTL -> SendCL ] -> RecvCL (other)
# RecvCL is a callee interface
if isinstance(other, NonBlockingCalleeIfc):
m = RecvRTL2SendCL(s.MsgType)
if hasattr(parent, "RecvRTL2SendCL_count"):
count = parent.RecvRTL2SendCL_count
setattr(parent, "RecvRTL2SendCL_" + str(count), m)
else:
parent.RecvRTL2SendCL_count = 0
parent.RecvRTL2SendCL_0 = m
connect_pairs(
m.send,
other,
s.msg,
m.recv.msg,
s.en,
m.recv.en,
s.rdy,
m.recv.rdy,
)
parent.RecvRTL2SendCL_count += 1
return True
return False
def connect(s, other, parent):
# We are doing GiveIfcRTL (s) -> [ AND ] -> RecvIfcRTL (other)
# Basically we AND the rdy of both sides for enable
if isinstance(other, RecvIfcRTL):
connect(s.ret, other.msg)
m = And(Bits1)
if hasattr(parent, "give_recv_ander_cnt"):
cnt = parent.give_recv_ander_cnt
setattr(parent, "give_recv_ander_" + str(cnt), m)
else:
parent.give_recv_ander_cnt = 0
parent.give_recv_ander_0 = m
connect_pairs(
m.in0,
s.rdy,
m.in1,
other.rdy,
m.out,
s.en,
m.out,
other.en,
)
parent.give_recv_ander_cnt += 1
return True
elif isinstance(other, CalleeIfcCL):
if s._dsl.level <= other._dsl.level:
raise InvalidConnectionError(
"CL2RTL connection is not supported between RecvIfcRTL"
" and CalleeIfcCL.\n"
" - level {}: {} (class {})\n"
" - level {}: {} (class {})".format(
s._dsl.level, repr(s), type(s), other._dsl.level,
repr(other), type(other)))
m = GetRTL2GiveCL(s.MsgType)
if hasattr(parent, "GetRTL2GiveCL_count"):
count = parent.GetRTL2GiveCL_count
setattr(parent, "GetRTL2GiveCL_" + str(count), m)
else:
parent.GetRTL2GiveCL_count = 0
parent.GetRTL2GiveCL_0 = m
connect_pairs(
s,
m.get,
m.give,
other,
)
parent.GetRTL2GiveCL_count += 1
return True
return False
def construct( s, DutType, src_msgs, sink_msgs ):
s.src = TestSrcCL( Bits128, src_msgs )
s.dut = DutType()
s.sink = TestSinkCL( Bits32, sink_msgs )
connect_pairs(
s.src.send, s.dut.recv,
s.dut.send, s.sink.recv,
)
def construct( s, DutType=ChecksumCL ):
s.recv = CalleeIfcCL( Type=Bits128 )
s.give = CalleeIfcCL( Type=Bits32 )
s.checksum_unit = DutType()
s.out_q = BypassQueueCL( num_entries=1 )
connect_pairs(
s.recv, s.checksum_unit.recv,
s.checksum_unit.send, s.out_q.enq,
s.out_q.deq, s.give,
)
def construct( s ):
s.recv = CalleeIfcCL( Type=Req )
s.give = CalleeIfcCL( Type=Resp )
s.checksum_xcel = ChecksumXcelCL()
s.out_q = BypassQueueCL( num_entries=1 )
connect_pairs(
s.recv, s.checksum_xcel.xcel.req,
s.checksum_xcel.xcel.resp, s.out_q.enq,
s.out_q.deq, s.give,
)
def connect( s, other, parent ):
# We are doing SendCL (other) -> [ RecvCL -> SendRTL ] -> RecvRTL (s)
# SendCL is a caller interface
if isinstance( other, CallerIfcCL ):
m = RecvCL2SendRTL( s.MsgType )
if hasattr( parent, "RecvCL2SendRTL_count" ):
count = parent.RecvCL2SendRTL_count
setattr( parent, "RecvCL2SendRTL_" + str( count ), m )
else:
parent.RecvCL2SendRTL_count = 0
parent.RecvCL2SendRTL_0 = m
connect_pairs(
other, m.recv,
m.send.msg, s.msg,
m.send.en, s.en,
m.send.rdy, s.rdy
)
parent.RecvCL2SendRTL_count += 1
return True
elif isinstance( other, CalleeIfcCL ):
if s._dsl.level <= other._dsl.level:
raise InvalidConnectionError(
"CL2RTL connection is not supported between RecvIfcRTL"
" and CalleeIfcCL.\n"
" - level {}: {} (class {})\n"
" - level {}: {} (class {})".format(
s._dsl.level, repr( s ), type( s ), other._dsl.level,
repr( other ), type( other ) ) )
m = RecvCL2SendRTL( s.MsgType )
if hasattr( parent, "RecvCL2SendRTL_count" ):
count = parent.RecvCL2SendRTL_count
setattr( parent, "RecvCL2SendRTL_" + str( count ), m )
else:
parent.RecvCL2SendRTL_count = 0
parent.RecvCL2SendRTL_0 = m
connect_pairs(
other, m.recv,
m.send.msg, s.msg,
m.send.en, s.en,
m.send.rdy, s.rdy
)
parent.RecvCL2SendRTL_count += 1
return True
return False
def construct( s, ReqType, RespType ):
s.left = XcelMinionIfcFL ()
s.right = XcelMasterIfcRTL( ReqType, RespType )
s.fl2cl = XcelIfcFL2CLAdapter( ReqType, RespType )
s.req_cl2rtl = RecvCL2SendRTL( ReqType )
s.resp_rtl2cl = RecvRTL2SendCL( RespType)
connect( s.left, s.fl2cl.left )
connect_pairs(
s.fl2cl.right.req, s.req_cl2rtl.recv,
s.req_cl2rtl.send, s.right.req,
)
connect_pairs(
s.fl2cl.right.resp, s.resp_rtl2cl.send,
s.resp_rtl2cl.recv, s.right.resp,
)
def connect(s, other, parent):
# We are doing SendCL (other) -> [ RecvCL -> GiveIfcFL ] -> GetIfcFL (s)
# SendCL is a caller interface
if isinstance(other, NonBlockingCallerIfc):
m = RecvCL2GiveFL()
if hasattr(parent, "RecvCL2GiveFL_count"):
count = parent.RecvCL2GiveFL_count
setattr(parent, "RecvCL2GiveFL_" + str(count), m)
else:
parent.RecvCL2GiveFL_count = 0
parent.RecvCL2GiveFL_0 = m
connect_pairs(other, m.recv, m.give, s)
parent.RecvCL2GiveFL_count += 1
return True
return False
def connect(s, other, parent):
if isinstance(other, XcelMasterIfcRTL):
m = XcelIfcRTL2FLAdapter(other.ReqType, other.RespType)
if hasattr(parent, "XcelIfcRTL2FL_count"):
count = parent.XcelIfcRTL2FL_count
setattr(parent, "XcelIfcRTL2FL_" + str(count), m)
else:
parent.XcelIfcRTL2FL_count = 0
parent.XcelIfcRTL2FL_0 = m
connect_pairs(
other,
m.left,
m.right,
s,
)
parent.XcelIfcRTL2FL_count += 1
return True
elif isinstance(other, XcelMasterIfcCL):
m = XcelIfcCL2FLAdapter(other.ReqType, other.RespType)
if hasattr(parent, "XcelIfcCL2FL_count"):
count = parent.XcelIfcCL2FL_count
setattr(parent, "XcelIfcCL2FL_" + str(count), m)
else:
parent.XcelIfcCL2FL_count = 0
parent.XcelIfcCL2FL_0 = m
connect_pairs(
other,
m.left,
m.right,
s,
)
parent.XcelIfcCL2FL_count += 1
return True
return False
def connect(s, other, parent):
if isinstance(other, MemMinionIfcCL):
m = MemIfcFL2CLAdapter(other.ReqType, other.RespType)
if hasattr(parent, "MemIfcFL2CL_count"):
count = parent.MemIfcFL2CL_count
setattr(parent, "MemIfcFL2CL_" + str(count), m)
else:
parent.MemIfcFL2CL_count = 0
parent.MemIfcFL2CL_0 = m
connect_pairs(
s,
m.left,
m.right,
other,
)
parent.MemIfcFL2CL_count += 1
return True
elif isinstance(other, MemMinionIfcRTL):
m = MemIfcFL2RTLAdapter(other.ReqType, other.RespType)
if hasattr(parent, "MemIfcFL2RTL_count"):
count = parent.MemIfcFL2RTL_count
setattr(parent, "MemIfcFL2RTL_" + str(count), m)
else:
parent.MemIfcFL2RTL_count = 0
parent.MemIfcFL2RTL_0 = m
connect_pairs(
s,
m.left,
m.right,
other,
)
parent.MemIfcFL2RTL_count += 1
return True
return False
def construct(s, ProcClass, XcelClass):
req_class, resp_class = mk_mem_msg(8, 32, 32)
s.commit_inst = OutPort(Bits1)
# Instruction Memory Request/Response Interface
s.proc = ProcClass()(commit_inst=s.commit_inst)
s.xcel = XcelClass()(xcel=s.proc.xcel)
if isinstance(s.proc.imem, MemMasterIfcRTL): # RTL proc
s.mngr2proc = RecvIfcRTL(Bits32)
s.proc2mngr = SendIfcRTL(Bits32)
s.imem = MemMasterIfcRTL(req_class, resp_class)
s.dmem = MemMasterIfcRTL(req_class, resp_class)
elif isinstance(s.proc.imem, MemMasterIfcCL): # CL proc
s.mngr2proc = NonBlockingCalleeIfc(Bits32)
s.proc2mngr = NonBlockingCallerIfc(Bits32)
s.imem = MemMasterIfcCL(req_class, resp_class)
s.dmem = MemMasterIfcCL(req_class, resp_class)
elif isinstance(s.proc.imem, MemMasterIfcFL): # FL proc
s.mngr2proc = GetIfcFL()
s.proc2mngr = SendIfcFL()
s.imem = MemMasterIfcFL()
s.dmem = MemMasterIfcFL()
connect_pairs(
s.mngr2proc,
s.proc.mngr2proc,
s.proc2mngr,
s.proc.proc2mngr,
s.imem,
s.proc.imem,
s.dmem,
s.proc.dmem,
)
def connect( s, other, parent ):
if isinstance( other, MemMasterIfcCL ):
m = MemIfcCL2FLAdapter( other.req_class, other.resp_class )
if hasattr( parent, "MemIfcCL2FL_count" ):
count = parent.MemIfcCL2FL_count
setattr( parent, "MemIfcCL2FL_" + str( count ), m )
else:
parent.MemIfcCL2FL_count = 0
parent.MemIfcCL2FL_0 = m
connect_pairs(
other, m.left,
m.right, other,
)
parent.MemIfcCL2FL_count += 1
return True
elif isinstance( other, MemMasterIfcRTL ):
m = MemIfcRTL2FLAdapter( other.req_class, other.resp_class )
if hasattr( parent, "MemIfcRTL2FL_count" ):
count = parent.MemIfcRTL2FL_count
setattr( parent, "MemIfcRTL2FL_" + str( count ), m )
else:
parent.MemIfcRTL2FL_count = 0
parent.MemIfcRTL2FL_0 = m
connect_pairs(
other, m.left,
m.right, s,
)
parent.MemIfcRTL2FL_count += 1
return True
return False
def construct(s):
req_class, resp_class = mk_mem_msg(8, 32, 32)
# Proc/Mngr Interface
s.mngr2proc = RecvIfcRTL(Bits32)
s.proc2mngr = SendIfcRTL(Bits32)
# Instruction Memory Request/Response Interface
s.imem = MemMasterIfcRTL(req_class, resp_class)
# Data Memory Request/Response Interface
s.dmem = MemMasterIfcRTL(req_class, resp_class)
# Xcel Request/Response Interface
xreq_class, xresp_class = mk_xcel_msg(5, 32)
s.xcel = XcelMasterIfcRTL(xreq_class, xresp_class)
# val_W port used for counting commited insts.
s.commit_inst = OutPort(Bits1)
# imem drop unit
s.imemresp_drop = m = DropUnitRTL(Bits32)
connect_pairs(
m.in_.en,
s.imem.resp.en,
m.in_.rdy,
s.imem.resp.rdy,
m.in_.msg,
s.imem.resp.msg.data,
)
# Bypass queues
s.imemreq_q = BypassQueue2RTL(req_class, 2)(deq=s.imem.req)
# We have to turn input receive interface into get interface
s.imemresp_q = BypassQueueRTL(Bits32, 1)(enq=s.imemresp_drop.out)
s.dmemresp_q = BypassQueueRTL(resp_class, 1)(enq=s.dmem.resp)
s.mngr2proc_q = BypassQueueRTL(Bits32, 1)(enq=s.mngr2proc)
s.xcelresp_q = BypassQueueRTL(xresp_class, 1)(enq=s.xcel.resp)
# Control
s.ctrl = ProcCtrl()(
# imem port
imemresp_drop=s.imemresp_drop.drop,
imemreq_en=s.imemreq_q.enq.en,
imemreq_rdy=s.imemreq_q.enq.rdy,
imemresp_en=s.imemresp_q.deq.en,
imemresp_rdy=s.imemresp_q.deq.rdy,
# dmem port
dmemreq_en=s.dmem.req.en,
dmemreq_rdy=s.dmem.req.rdy,
dmemreq_type=s.dmem.req.msg.type_,
dmemresp_en=s.dmemresp_q.deq.en,
dmemresp_rdy=s.dmemresp_q.deq.rdy,
# xcel port
xcelreq_en=s.xcel.req.en,
xcelreq_rdy=s.xcel.req.rdy,
xcelresp_en=s.xcelresp_q.deq.en,
xcelresp_rdy=s.xcelresp_q.deq.rdy,
# proc2mngr and mngr2proc
proc2mngr_en=s.proc2mngr.en,
proc2mngr_rdy=s.proc2mngr.rdy,
mngr2proc_en=s.mngr2proc_q.deq.en,
mngr2proc_rdy=s.mngr2proc_q.deq.rdy,
# commit inst for counting
commit_inst=s.commit_inst)
# Dpath
s.dpath = ProcDpath()(
# imem ports
imemreq_addr=s.imemreq_q.enq.msg.addr,
imemresp_data=s.imemresp_q.deq.msg,
# dmem ports
dmemreq_addr=s.dmem.req.msg.addr,
dmemreq_data=s.dmem.req.msg.data,
dmemresp_data=s.dmemresp_q.deq.msg.data,
# xcel ports
xcelresp_data=s.xcelresp_q.deq.msg.data,
# mngr
mngr2proc_data=s.mngr2proc_q.deq.msg,
proc2mngr_data=s.proc2mngr.msg,
)
@s.update
def up_xcelreq():
s.xcel.req.msg = xreq_class(
s.ctrl.xcelreq_type,
s.dpath.xcelreq_addr,
s.dpath.xcelreq_data,
)
# Ctrl <-> Dpath
connect_pairs(
s.ctrl.reg_en_F,
s.dpath.reg_en_F,
s.ctrl.pc_sel_F,
s.dpath.pc_sel_F,
s.ctrl.reg_en_D,
s.dpath.reg_en_D,
s.ctrl.op1_byp_sel_D,
s.dpath.op1_byp_sel_D,
s.ctrl.op2_byp_sel_D,
s.dpath.op2_byp_sel_D,
s.ctrl.op1_sel_D,
s.dpath.op1_sel_D,
s.ctrl.op2_sel_D,
s.dpath.op2_sel_D,
s.ctrl.imm_type_D,
s.dpath.imm_type_D,
s.ctrl.reg_en_X,
s.dpath.reg_en_X,
s.ctrl.alu_fn_X,
s.dpath.alu_fn_X,
s.ctrl.reg_en_M,
s.dpath.reg_en_M,
s.ctrl.wb_result_sel_M,
s.dpath.wb_result_sel_M,
s.ctrl.mask_sel_W,
s.dpath.mask_sel_W,
s.ctrl.reg_en_W,
s.dpath.reg_en_W,
s.ctrl.rf_waddr_W,
s.dpath.rf_waddr_W,
s.ctrl.rf_wen_W,
s.dpath.rf_wen_W,
s.dpath.inst_D,
s.ctrl.inst_D,
s.dpath.ne_X,
s.ctrl.ne_X,
)
