def test_ram(record_speed=False, width=8): print("\n\n------ TEST RAM READ / WRITE SPEED [%s] ------" % test_config) test_addr = ram_start test_size = ram_size data = [randrange(1, 50) for x in range(test_size)] start = time() if width == 8: target.write_memory_block8(test_addr, data) elif width == 32: target.write_memory_block32( test_addr, conversion.byte_list_to_u32le_list(data)) target.flush() stop = time() diff = stop - start if diff == 0: print("Unexpected ram write elapsed time of 0!") write_speed = 0 else: write_speed = test_size / diff if record_speed: result.write_speed = write_speed print("Writing %i byte took %.3f seconds: %.3f B/s" % (test_size, diff, write_speed)) start = time() if width == 8: block = target.read_memory_block8(test_addr, test_size) elif width == 32: block = conversion.u32le_list_to_byte_list( target.read_memory_block32(test_addr, test_size // 4)) target.flush() stop = time() diff = stop - start if diff == 0: print("Unexpected ram read elapsed time of 0!") read_speed = 0 else: read_speed = test_size / diff if record_speed: result.read_speed = read_speed print("Reading %i byte took %.3f seconds: %.3f B/s" % (test_size, diff, read_speed)) error = False if len(block) != len(data): error = True print("ERROR: read length (%d) != write length (%d)!" % (len(block), len(data))) if not error: for i in range(len(block)): if (block[i] != data[i]): error = True print("ERROR: 0x%X, 0x%X, 0x%X!!!" % ((addr + i), block[i], data[i])) if error: print("TEST FAILED") else: print("TEST PASSED") return not error
def test_byteListToU32leList(self): data = range(32) assert byte_list_to_u32le_list(data) == [ 0x03020100, 0x07060504, 0x0B0A0908, 0x0F0E0D0C, 0x13121110, 0x17161514, 0x1B1A1918, 0x1F1E1D1C, ]
def test_byte_list_to_u32le_list_unaligned(self): assert byte_list_to_u32le_list([1]) == [0x00000001] assert byte_list_to_u32le_list([1, 2, 3]) == [0x00030201] assert byte_list_to_u32le_list([1, 2, 3, 4, 5]) == [0x04030201, 0x00000005] assert byte_list_to_u32le_list([1], pad=0xcc) == [0xcccccc01] assert byte_list_to_u32le_list([1, 2, 3], pad=0xdd) == [0xdd030201] assert byte_list_to_u32le_list([1, 2, 3, 4, 5], pad=0xff) == [0x04030201, 0xffffff05]
def test_ram(record_speed=False, width=8): print("\n\n------ TEST RAM READ / WRITE SPEED [%s] ------" % test_config) test_addr = ram_start test_size = ram_size data = [randrange(1, 50) for x in range(test_size)] start = time() if width == 8: target.write_memory_block8(test_addr, data) elif width == 32: target.write_memory_block32(test_addr, conversion.byte_list_to_u32le_list(data)) target.flush() stop = time() diff = stop - start if diff == 0: print("Unexpected ram write elapsed time of 0!") write_speed = 0 else: write_speed = test_size / diff if record_speed: result.write_speed = write_speed print("Writing %i byte took %.3f seconds: %.3f B/s" % (test_size, diff, write_speed)) start = time() if width == 8: block = target.read_memory_block8(test_addr, test_size) elif width == 32: block = conversion.u32le_list_to_byte_list(target.read_memory_block32(test_addr, test_size // 4)) target.flush() stop = time() diff = stop - start if diff == 0: print("Unexpected ram read elapsed time of 0!") read_speed = 0 else: read_speed = test_size / diff if record_speed: result.read_speed = read_speed print("Reading %i byte took %.3f seconds: %.3f B/s" % (test_size, diff, read_speed)) error = False if len(block) != len(data): error = True print("ERROR: read length (%d) != write length (%d)!" % (len(block), len(data))) if not error: for i in range(len(block)): if (block[i] != data[i]): error = True print("ERROR: 0x%X, 0x%X, 0x%X!!!" % ((addr + i), block[i], data[i])) if error: print("TEST FAILED") else: print("TEST PASSED") return not error
def commands_test(board_id): with ConnectHelper.session_with_chosen_probe( unique_id=board_id, **get_session_options()) as session: board = session.board target = session.target target_type = board.target_type test_params = get_target_test_params(session) session.probe.set_clock(test_params['test_clock']) memory_map = board.target.get_memory_map() boot_region = memory_map.get_boot_memory() ram_region = memory_map.get_default_region_of_type(MemoryType.RAM) ram_base = ram_region.start boot_start_addr = boot_region.start boot_end_addr = boot_region.end boot_blocksize = boot_region.blocksize binary_file = get_test_binary_path(board.test_binary) # Generate an Intel hex file from the binary test file. temp_test_hex_name = binary_to_hex_file(binary_file, boot_region.start) temp_bin_file = tempfile.mktemp('.bin') with open(binary_file, "rb") as f: test_data = list(bytearray(f.read())) test_data_length = len(test_data) test_file_sectors = round_up_div(test_data_length, boot_blocksize) boot_first_free_block_addr = boot_start_addr + test_file_sectors * boot_blocksize reset_handler_addr = conversion.byte_list_to_u32le_list( test_data[4:8])[0] test_pass_count = 0 test_count = 0 failed_commands = [] result = CommandsTestResult() context = CommandExecutionContext() context.attach_session(session) COMMANDS_TO_TEST = [ "status", "reset", "reset halt", "reg", "reg general", "reg all", "reg r0", "wreg r0 0x12345678", "d pc", "d --center pc 32", "read64 0x%08x" % ((boot_start_addr + boot_blocksize) & ~7), "read32 0x%08x" % ((boot_start_addr + boot_blocksize) & ~3), "read16 0x%08x" % ((boot_start_addr + boot_blocksize) & ~1), "read8 0x%08x" % (boot_start_addr + boot_blocksize), "rd 0x%08x 16" % ram_base, "rw 0x%08x 16" % ram_base, "rh 0x%08x 16" % ram_base, "rb 0x%08x 16" % ram_base, "write64 0x%08x 0x1122334455667788 0xaabbccddeeff0011" % ram_base, "write32 0x%08x 0x11223344 0x55667788" % ram_base, "write16 0x%08x 0xabcd" % (ram_base + 8), "write8 0x%08x 0 1 2 3 4 5 6" % (ram_base + 10), "savemem 0x%08x 128 '%s'" % (boot_start_addr, fix_windows_path(temp_bin_file)), "loadmem 0x%08x '%s'" % (ram_base, fix_windows_path(temp_bin_file)), "loadmem 0x%08x '%s'" % (boot_start_addr, fix_windows_path(binary_file)), "load '%s'" % fix_windows_path(temp_test_hex_name), "load '%s' 0x%08x" % (fix_windows_path(binary_file), boot_start_addr), "compare 0x%08x '%s'" % (ram_base, fix_windows_path(temp_bin_file)), "compare 0x%08x 32 '%s'" % (ram_base, fix_windows_path(temp_bin_file)), "fill 0x%08x 128 0xa5" % ram_base, "fill 16 0x%08x 64 0x55aa" % (ram_base + 64), "find 0x%08x 128 0xaa 0x55" % ram_base, # find that will pass "find 0x%08x 128 0xff" % ram_base, # find that will fail "erase 0x%08x" % (boot_first_free_block_addr), "erase 0x%08x 1" % (boot_first_free_block_addr + boot_blocksize), "go", "halt", "step", "s 4", "continue", "h", "break 0x%08x" % reset_handler_addr, "lsbreak", "rmbreak 0x%08x" % reset_handler_addr, "watch 0x%08x" % ram_base, "lswatch", "rmwatch 0x%08x" % ram_base, "watch 0x%08x rw 2" % ram_base, "rmwatch 0x%08x" % ram_base, "core", "core 0", "readdp 0", # read DPIDR "writedp 0 0x1e", # write ABORT to clear error flags "readap 0xfc", # read IDR "readap 0 0xfc", # read IDR of AP#0 "writeap 0x4 0", # set TAR to 0 "writeap 0 0x4 0", # set TAR to 0 on AP#0 "gdbserver start", "gdbserver status", "gdbserver stop", "probeserver start", "probeserver status", "probeserver stop", "show probe-uid", "show target", "show cores", "show map", "show peripherals", "show fault", "show nreset", "set nreset 1", "show option reset_type", "set option reset_type=sw", "show mem-ap", "set mem-ap 0", "show hnonsec", "set hnonsec 0", "show hprot", "set hprot 0x3", # set default hprot: data, priv "show graph", "show locked", "show register-groups", "show vector-catch", "set vector-catch all", "show step-into-interrupts", "set step-into-interrupts 1", "set log info", "set frequency %d" % test_params['test_clock'], # Semicolon-separated commands. 'rw 0x%08x ; rw 0x%08x' % (ram_base, ram_base + 4), 'rb 0x%08x;rb 0x%08x' % (ram_base, ram_base + 1), 'rb 0x%08x; rb 0x%08x' % (ram_base, ram_base + 1), # Python and system commands. '$2+ 2', '$ target', '!echo hello', '!echo hi ; echo there', # semicolon in a sytem command (because semicolon separation is not supported for Python/system command lines) ' $ " ".join(["hello", "there"])', ' ! echo "yo dude" ', # Commands not tested: # "list", # "erase", # chip erase # "unlock", # "exit", # "initdp", # "makeap", # "reinit", # "where", # "symbol", ] # For now we just verify that the commands run without raising an exception. print("\n------ Testing commands ------") def test_command(cmd): try: print("\nTEST: %s" % cmd) context.process_command_line(cmd) except: print("TEST FAILED") failed_commands.append(cmd) traceback.print_exc(file=sys.stdout) return False else: print("TEST PASSED") return True for cmd in COMMANDS_TO_TEST: if test_command(cmd): test_pass_count += 1 test_count += 1 print("\n\nTest Summary:") print("Pass count %i of %i tests" % (test_pass_count, test_count)) if failed_commands: for c in failed_commands: print(" - '" + c + "'") if test_pass_count == test_count: print("COMMANDS TEST SCRIPT PASSED") else: print("COMMANDS TEST SCRIPT FAILED") target.reset() result.passed = test_count == test_pass_count return result
def read_memory_block32(self, addr, size): return conversion.byte_list_to_u32le_list(self.read_memory_block8(addr, size*4))
def test_byte_list_to_u32le_list_bytearray(self): assert byte_list_to_u32le_list(bytearray(b'abcd')) == [0x64636261] assert byte_list_to_u32le_list(bytearray(b'a')) == [0x00000061]
def test_byte_list_to_u32le_list_empty(self): assert byte_list_to_u32le_list([]) == []
def send(self, data): self.target.write_memory_block32(self.base + 0x10, byte_list_to_u32le_list(data)) self.target.write32(self.base + 0x0, 0x12121212) self.sent += len(data)