def test_simple_probe_debug(self): pyrtl.set_debug_mode() i = pyrtl.Input(1) o = pyrtl.Output(1) output = six.StringIO() sys.stdout = output o <<= pyrtl.probe(i + 1, name="probe0") sys.stdout = sys.__stdout__ self.assertTrue(output.getvalue().startswith("Probe: probe0")) pyrtl.set_debug_mode(False)
def test_print_trace_single_dig_notcompact(self): self.out <<= pyrtl.probe(self.in1, "in1_probe") + self.in2 sim_trace = pyrtl.SimulationTrace() sim = self.sim(tracer=sim_trace) for i in range(5): sim.step({self.in1: i, self.in2: 5 - i}) correct_outp = (" --- Values in base 10 ---\n" "in1 0 1 2 3 4\n" "in1_probe 0 1 2 3 4\n" "in2 5 4 3 2 1\n" "out 5 5 5 5 5\n") output = six.StringIO() sim_trace.print_trace(output) self.assertEqual(output.getvalue(), correct_outp)
def test_print_trace_base16(self): self.out <<= pyrtl.probe(self.in1, "in1_probe") * self.in2 sim_trace = pyrtl.SimulationTrace() sim = self.sim(tracer=sim_trace) for i in range(5): sim.step({self.in1: 9 * i, self.in2: 9 * (5 - i)}) correct_outp = (" --- Values in base 16 ---\n" "in1 0 9 12 1b 24\n" "in1_probe 0 9 12 1b 24\n" "in2 2d 24 1b 12 9\n" "out 0 144 1e6 1e6 144\n") output = six.StringIO() sim_trace.print_trace(output, base=16) self.assertEqual(output.getvalue(), correct_outp)
def test_print_trace_base2(self): self.out <<= pyrtl.probe(self.in1, "in1_probe") + self.in2 sim_trace = pyrtl.SimulationTrace() sim = self.sim(tracer=sim_trace) for i in range(5): sim.step({self.in1: 4 * i, self.in2: 4 * (5 - i)}) correct_outp = (" --- Values in base 2 ---\n" "in1 0 100 1000 1100 10000\n" "in1_probe 0 100 1000 1100 10000\n" "in2 10100 10000 1100 1000 100\n" "out 10100 10100 10100 10100 10100\n") output = six.StringIO() sim_trace.print_trace(output, base=2) self.assertEqual(output.getvalue(), correct_outp)
def test_print_trace_base8(self): self.out <<= pyrtl.probe(self.in1, "in1_probe") + self.in2 sim_trace = pyrtl.SimulationTrace() sim = self.sim(tracer=sim_trace) for i in range(5): sim.step({self.in1: 6 * i, self.in2: 6 * (5 - i)}) correct_outp = (" --- Values in base 8 ---\n" "in1 0 6 14 22 30\n" "in1_probe 0 6 14 22 30\n" "in2 36 30 22 14 6\n" "out 36 36 36 36 36\n") output = six.StringIO() sim_trace.print_trace(output, base=8) self.assertEqual(output.getvalue(), correct_outp)
def test_print_trace_single_dig_notcompact(self): self.out <<= pyrtl.probe(self.in1, "in1_probe") + self.in2 sim_trace = pyrtl.SimulationTrace() sim = self.sim(tracer=sim_trace) for i in range(5): sim.step({ self.in1: i, self.in2: 5-i }) correct_outp = (" --- Values in base 10 ---\n" "in1 0 1 2 3 4\n" "in1_probe 0 1 2 3 4\n" "in2 5 4 3 2 1\n" "out 5 5 5 5 5\n") output = six.StringIO() sim_trace.print_trace(output) self.assertEqual(output.getvalue(), correct_outp)
def test_print_trace_base16(self): self.out <<= pyrtl.probe(self.in1, "in1_probe") * self.in2 sim_trace = pyrtl.SimulationTrace() sim = self.sim(tracer=sim_trace) for i in range(5): sim.step({ self.in1: 9*i, self.in2: 9*(5 - i) }) correct_outp = (" --- Values in base 16 ---\n" "in1 0 9 12 1b 24\n" "in1_probe 0 9 12 1b 24\n" "in2 2d 24 1b 12 9\n" "out 0 144 1e6 1e6 144\n") output = six.StringIO() sim_trace.print_trace(output, base=16) self.assertEqual(output.getvalue(), correct_outp)
def test_print_trace_base8(self): self.out <<= pyrtl.probe(self.in1, "in1_probe") + self.in2 sim_trace = pyrtl.SimulationTrace() sim = self.sim(tracer=sim_trace) for i in range(5): sim.step({ self.in1: 6*i, self.in2: 6*(5 - i) }) correct_outp = (" --- Values in base 8 ---\n" "in1 0 6 14 22 30\n" "in1_probe 0 6 14 22 30\n" "in2 36 30 22 14 6\n" "out 36 36 36 36 36\n") output = six.StringIO() sim_trace.print_trace(output, base=8) self.assertEqual(output.getvalue(), correct_outp)
def test_print_trace_base2(self): self.out <<= pyrtl.probe(self.in1, "in1_probe") + self.in2 sim_trace = pyrtl.SimulationTrace() sim = self.sim(tracer=sim_trace) for i in range(5): sim.step({ self.in1: 4*i, self.in2: 4*(5 - i) }) correct_outp = (" --- Values in base 2 ---\n" "in1 0 100 1000 1100 10000\n" "in1_probe 0 100 1000 1100 10000\n" "in2 10100 10000 1100 1000 100\n" "out 10100 10100 10100 10100 10100\n") output = six.StringIO() sim_trace.print_trace(output, base=2) self.assertEqual(output.getvalue(), correct_outp)
def test_simple_probe_debug(self): pyrtl.set_debug_mode() i = pyrtl.Input(1) o = pyrtl.Output(1) o <<= pyrtl.probe(i + 1) pyrtl.set_debug_mode(False)
def test_probe_wire(self): i = pyrtl.Input(1) x = pyrtl.probe(i) self.assertIs(x, i)
def test_simple_probe(self): i = pyrtl.Input(1) o = pyrtl.Output(1) o <<= pyrtl.probe(i + 1)
# --- Probe --- # clear all hardware from current working block pyrtl.reset_working_block() print("---- Using Probes ----") # In this example, we will be multiplying two numbers using tree_multiplier() # Again, create the two inputs and an output in1, in2 = (pyrtl.Input(8, "in" + str(x)) for x in range(1, 3)) out1, out2 = (pyrtl.Output(8, "out" + str(x)) for x in range(1, 3)) multout = multipliers.tree_multiplier(in1, in2) # The following line will create a probe named 'std_probe" for later use, like an output. pyrtl.probe(multout, 'std_probe') # The probe returns multout, the original wire, and multout * 2 will be assigned to out1 out1 <<= pyrtl.probe(multout, 'stdout_probe') * 2 # probe can also be used with other operations like this: pyrtl.probe(multout + 32, 'adder_probe') # or this: pyrtl.probe(multout[2:7], 'select_probe') # or, similarly: # (this will create a probe of multout while passing multout[2:16] to out2) out2 <<= pyrtl.probe(multout)[2:16] # probe can be used on any wire any time, even before or during its operation, assignment, etc.
# Now that we have built some stuff, let's clear it so we can try again in a # different way. We can start by clearing all of the hardware from the current working # block. The working block is a global structure that keeps track of all the # hardware you have built thus far. A "reset" will clear it so we can start fresh. pyrtl.reset_working_block() print("---- Using Probes ----") # In this example, we will be multiplying two numbers using tree_multiplier() # Again, create the two inputs and an output in1, in2 = (pyrtl.Input(8, "in" + str(x)) for x in range(1, 3)) out1, out2 = (pyrtl.Output(8, "out" + str(x)) for x in range(1, 3)) multout = multipliers.tree_multiplier(in1, in2) # The following line will create a probe named 'std_probe" for later use, like an output. pyrtl.probe(multout, 'std_probe') # We could also do the same thing during assignment. The next command will # create a probe (named 'stdout_probe') that refers to multout (returns the wire multout). # This achieves virtually the same thing as 4 lines above, but it is done during assignment, # so we skip a step by probing the wire before the multiplication. # The probe returns multout, the original wire, and out will be assigned multout * 2 out1 <<= pyrtl.probe(multout, 'stdout_probe') * 2 # probe can also be used with other operations like this: pyrtl.probe(multout + 32, 'adder_probe') # or this: pyrtl.probe(multout[2:7], 'select_probe') # or, similarly:
def add_probe_if(wire): if condition_func(wire): pyrtl.probe(wire) return wire, wire
def test_bad_probe_wire(self): with self.assertRaises(pyrtl.PyrtlError): pyrtl.probe(5) with self.assertRaises(pyrtl.PyrtlError): pyrtl.probe('a')
def simple_add(k, x): assert isinstance(k, int) new_wire = x + k return new_wire # --------- Hardware ---------- in1, in2 = (pyrtl.Input(8, "in" + str(x)) for x in range(1, 3)) out1, out2, out3 = (pyrtl.Output(8, "out" + str(x)) for x in range(1, 4)) out1 <<= in1 + in2 out2 <<= simple_add(3, in1) out3 <<= pyrtl.probe(in1 + 3, 'adder1_probe') # idea ? --> nope (maybe) # out3 <<= rdelta((pyrtl.probe(in1, 'in1_probe')), in1) # -------- Simulation --------- # each produces list of 15 random values in the given range vals1 = [int(2**random.uniform(1, 8) - 2) for _ in range(15)] vals2 = [int(random.uniform(0, 36)) for _ in range(15)] sim_trace = pyrtl.SimulationTrace() sim = pyrtl.Simulation(tracer=sim_trace) for cycle in range(len(vals1)): sim.step({ 'in1': vals1[cycle],