def test_bram(): bram_module = bram.mkTop() bram_code = bram_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == bram_code)
def test(): test_module = submodule_read_verilog_nested.mkTop() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test_led(): led_module = led.mkLed() led_code = led_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == led_code)
def test_led(): modules = led.mkThread() code = ''.join([ m.to_verilog() for m in modules.values() ]) from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test_led(): test_module = instance_noname_args.mkTop() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = regchain.mkRegChain(length=120) code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = thread_multibank_ram_rtl_connect.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = types_ram_manager_write_dataflow_when.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert (expected_code == code)
def test(): veriloggen.reset() test_module = seq_delayed_eager_val_lazy_cond.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = from_verilog_module_oldstylecode.mkTop() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = thread_call_from_different_point.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): filename = os.path.dirname(os.path.abspath(__file__)) + '/nested_led.v' conv = hardcheck.convert_from_file('blinkled', filename) code = conv.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert (expected_code == code)
def test(): veriloggen.reset() test_module = thread_intrinsic_method_prefix.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): orig = convert_by_veriloggen_nested_led.mkLed() conv = hardcheck.convert(orig) code = conv.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert (expected_code == code)
def test_sort(): sort_module = sort.mkSimSort() sort_code = sort_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert expected_code == sort_code
def test(): veriloggen.reset() modules = from_verilog_pycoram_ctrl_thread.mkThread() code = ''.join([ m.to_verilog() for m in modules.values() ]) from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = types_axi_read_lite.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = dataflow_two_outputs_mul.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = pipeline_acc_add_valid.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = primitive_mux.mkLed() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() modules = from_verilog_pycoram_object.mkUserlogic() code = ''.join([ m.to_verilog() for m in modules.values() if not m.used ]) from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = thread_read.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(request): veriloggen.reset() simtype = request.config.getoption('--sim') code = thread_stream_ram_external_ports.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = simulation_simulator_iverilog.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code) sim = simulation.Simulator(test_module, sim='iverilog') rslt = sim.run() assert(expected_rslt == rslt)
def test(): veriloggen.reset() test_module = pipeline_multiple_add.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert (expected_code == code) sim = simulation.Simulator(test_module) rslt = sim.run() assert (expected_rslt == rslt)
def FromVerilog(source, func): parser = VerilogParser() ast = parser.parse(source) #ast.show() v = ModuleVisitor() v.visit(ast) if func == DefineCircuit: # only allow a single verilog module assert len(v.nodes) == 1 modules = [] for node in v.nodes: name, args = ParseVerilogModule(node) circuit = func(name, *args) if func == DefineCircuit: # inline source circuit.verilogFile = source EndDefine() modules.append(circuit) return modules
def test(): veriloggen.reset() test_module = simulation_simulator_vcs.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert (expected_code == code) try: from shutil import which except: # from distutils.spawn import find_executable as which print('no which command') return if which('vcs'): sim = simulation.Simulator(test_module, sim='vcs') rslt = sim.run() new_rslt = [] for line in rslt.split('\n'): if line.count('LED:') > 0: new_rslt.append(line) new_rslt.append('') rslt = '\n'.join(new_rslt) assert (expected_rslt == rslt) else: print("'vcs' not found")
def test(): veriloggen.reset() test_module = simulation_simulator_vcs.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code) try: from shutil import which except: # from distutils.spawn import find_executable as which print('no which command') return if which('vcs'): sim = simulation.Simulator(test_module, sim='vcs') rslt = sim.run() new_rslt = [] for line in rslt.split('\n'): if line.count('LED:') > 0: new_rslt.append(line) new_rslt.append('') rslt = '\n'.join(new_rslt) assert(expected_rslt == rslt) else: print("'vcs' not found")
def verilog_to_circuit(verilog, name, seq_types=None): """ Creates a new Circuit from a verilog file. Parameters ---------- path: str verilog code. name: str the module name. seq_types: list of dicts of str:str the sequential element types. Returns ------- Circuit the parsed circuit. """ if seq_types is None: seq_types = default_seq_types c = Circuit(name=name) with tempfile.TemporaryDirectory(prefix="circuitgraph") as d: codeparser = VerilogParser(outputdir=d, debug=False) ast = codeparser.parse(verilog, debug=False) description = ast.children()[0] module_def = [d for d in description.children() if d.name == name] if not module_def: raise ValueError(f"Module {name} not found") module_def = module_def[0] outputs = set() widths = dict() for child in module_def.children(): if type(child) == ast_types.Paramlist: if child.children(): raise ValueError( f"circuitgraph cannot parse parameters (line {child.lineno})" ) # Parse portlist elif type(child) == ast_types.Portlist: for cip in [ i for i in child.children() if type(i) == ast_types.Ioport ]: for ci in cip.children(): parse_io(c, ci, outputs) # Parse declarations elif type(child) == ast_types.Decl: if ast_types.Parameter in [type(i) for i in child.children()]: raise ValueError( f"circuitgraph cannot parse parameters (line {child.lineno})" ) for ci in [ i for i in child.children() if type(i) in [ast_types.Input, ast_types.Output] ]: parse_io(c, ci, outputs) # Parse instances elif type(child) == ast_types.InstanceList: for instance in child.instances: if instance.module in [ "buf", "not", "and", "nand", "or", "nor", "xor", "xnor", ]: gate = instance.module dest = parse_argument(instance.portlist[0].argname, c) sources = [ parse_argument(i.argname, c) for i in instance.portlist[1:] ] c.add(dest, gate, fanin=sources, output=dest in outputs) elif instance.module in [i.name for i in seq_types]: if instance.portlist[0].portname is None: raise ValueError("circuitgraph can only parse " "sequential instances declared " "with port argument notation " f"(line {instance.lineno})") seq_type = [ i for i in seq_types if i.name == instance.module ][0] ports = { p.portname: parse_argument(p.argname, c) for p in instance.portlist } c.add( ports.get(seq_type.io.get("q")), seq_type.seq_type, fanin=ports.get(seq_type.io.get("d")), clk=ports.get(seq_type.io.get("clk")), r=ports.get(seq_type.io.get("r")), s=ports.get(seq_type.io.get("s")), output=ports.get(seq_type.io.get("q")) in outputs, ) else: raise ValueError( "circuitgraph cannot parse instance of " f"type {instance.module} (line " f"{instance.lineno})") # Parse assigns elif type(child) == ast_types.Assign: dest = child.left.var dest = parse_argument(dest, c) if type(child.right.var) == ast_types.IntConst: c.add( dest, f"{child.right.var.value[-1]}", output=dest in outputs, ) elif issubclass(type(child.right.var), ast_types.Operator): parse_operator(child.right.var, c, outputs, dest=dest) elif issubclass(type(child.right.var), ast_types.Concat): raise ValueError( "circuitgraph cannot parse concatenations " f"(line {child.right.var.lineno})") else: raise ValueError( "circuitgraph cannot parse statements of type " f"{type(child)} (line {child.lineno})") return c