def test_apply_operation_back_conditional_measure(self): """Test consistency of apply_operation_back for conditional measure.""" # Measure targeting a clbit which is not a member of the conditional # register. qc.measure(qr[0], cr[0]).c_if(cr2, 0) new_creg = ClassicalRegister(1, 'cr2') self.dag.add_creg(new_creg) meas_gate = Measure() meas_gate.condition = (new_creg, 0) meas_node = self.dag.apply_operation_back(meas_gate, [self.qubit0], [self.clbit0]) self.assertEqual(meas_node.qargs, [self.qubit0]) self.assertEqual(meas_node.cargs, [self.clbit0]) self.assertEqual(meas_node.condition, meas_gate.condition) self.assertEqual( sorted(self.dag._multi_graph.in_edges(meas_node._node_id)), sorted([ (self.dag.input_map[self.qubit0]._node_id, meas_node._node_id, { 'wire': self.qubit0, 'name': 'qr[0]' }), (self.dag.input_map[self.clbit0]._node_id, meas_node._node_id, { 'wire': self.clbit0, 'name': 'cr[0]' }), (self.dag.input_map[new_creg[0]]._node_id, meas_node._node_id, { 'wire': Clbit(new_creg, 0), 'name': 'cr2[0]' }), ])) self.assertEqual( sorted(self.dag._multi_graph.out_edges(meas_node._node_id)), sorted([ (meas_node._node_id, self.dag.output_map[self.qubit0]._node_id, { 'wire': self.qubit0, 'name': 'qr[0]' }), (meas_node._node_id, self.dag.output_map[self.clbit0]._node_id, { 'wire': self.clbit0, 'name': 'cr[0]' }), (meas_node._node_id, self.dag.output_map[new_creg[0]]._node_id, { 'wire': Clbit(new_creg, 0), 'name': 'cr2[0]' }), ])) self.assertTrue(rx.is_directed_acyclic_graph(self.dag._multi_graph))
def test_apply_operation_back_conditional_measure_to_self(self): """Test consistency of apply_operation_back for measure onto conditioning bit.""" # Measure targeting a clbit which _is_ a member of the conditional # register. qc.measure(qr[0], cr[0]).c_if(cr, 3) meas_gate = Measure() meas_gate.condition = self.condition meas_node = self.dag.apply_operation_back(meas_gate, [self.qubit1], [self.clbit1]) self.assertEqual(meas_node.qargs, [self.qubit1]) self.assertEqual(meas_node.cargs, [self.clbit1]) self.assertEqual(meas_node.condition, meas_gate.condition) self.assertEqual( sorted(self.dag._multi_graph.in_edges(meas_node._node_id)), sorted([ (self.dag.input_map[self.qubit1]._node_id, meas_node._node_id, { 'wire': self.qubit1, 'name': 'qr[1]' }), (self.dag.input_map[self.clbit0]._node_id, meas_node._node_id, { 'wire': self.clbit0, 'name': 'cr[0]' }), (self.dag.input_map[self.clbit1]._node_id, meas_node._node_id, { 'wire': self.clbit1, 'name': 'cr[1]' }), ])) self.assertEqual( sorted(self.dag._multi_graph.out_edges(meas_node._node_id)), sorted([ (meas_node._node_id, self.dag.output_map[self.qubit1]._node_id, { 'wire': self.qubit1, 'name': 'qr[1]' }), (meas_node._node_id, self.dag.output_map[self.clbit0]._node_id, { 'wire': self.clbit0, 'name': 'cr[0]' }), (meas_node._node_id, self.dag.output_map[self.clbit1]._node_id, { 'wire': self.clbit1, 'name': 'cr[1]' }), ])) self.assertTrue(rx.is_directed_acyclic_graph(self.dag._multi_graph))