def test_active_reset_circuit(self, write_lat, cond_lat):
"""Test practical example of reset circuit.
Because of the stimulus pulse overlap with the previous XGate on the q register,
measure instruction is always triggered after XGate regardless of write latency.
Thus only conditional latency matters in the scheduling.
(input)
┌─┐ ┌───┐ ┌─┐ ┌───┐ ┌─┐ ┌───┐
q: ┤M├───┤ X ├───┤M├───┤ X ├───┤M├───┤ X ├───
└╥┘ └─╥─┘ └╥┘ └─╥─┘ └╥┘ └─╥─┘
║ ┌────╨────┐ ║ ┌────╨────┐ ║ ┌────╨────┐
c: 1/═╩═╡ c_0=0x1 ╞═╩═╡ c_0=0x1 ╞═╩═╡ c_0=0x1 ╞
0 └─────────┘ 0 └─────────┘ 0 └─────────┘
"""
qc = QuantumCircuit(1, 1)
qc.measure(0, 0)
qc.x(0).c_if(0, 1)
qc.measure(0, 0)
qc.x(0).c_if(0, 1)
qc.measure(0, 0)
qc.x(0).c_if(0, 1)
durations = InstructionDurations([("x", None, 100),
("measure", None, 1000)])
actual_asap = PassManager([
SetIOLatency(clbit_write_latency=write_lat,
conditional_latency=cond_lat),
ASAPScheduleAnalysis(durations),
PadDelay(),
]).run(qc)
actual_alap = PassManager([
SetIOLatency(clbit_write_latency=write_lat,
conditional_latency=cond_lat),
ALAPScheduleAnalysis(durations),
PadDelay(),
]).run(qc)
expected = QuantumCircuit(1, 1)
expected.measure(0, 0)
if cond_lat > 0:
expected.delay(cond_lat, 0)
expected.x(0).c_if(0, 1)
expected.measure(0, 0)
if cond_lat > 0:
expected.delay(cond_lat, 0)
expected.x(0).c_if(0, 1)
expected.measure(0, 0)
if cond_lat > 0:
expected.delay(cond_lat, 0)
expected.x(0).c_if(0, 1)
self.assertEqual(expected, actual_asap)
self.assertEqual(expected, actual_alap)
def test_scheduling_with_calibration(self):
"""Test if calibrated instruction can update node duration."""
qc = QuantumCircuit(2)
qc.x(0)
qc.cx(0, 1)
qc.x(1)
qc.cx(0, 1)
xsched = Schedule(Play(Constant(300, 0.1), DriveChannel(0)))
qc.add_calibration("x", (0, ), xsched)
durations = InstructionDurations([("x", None, 160), ("cx", None, 600)])
pm = PassManager([ASAPScheduleAnalysis(durations), PadDelay()])
scheduled = pm.run(qc)
expected = QuantumCircuit(2)
expected.x(0)
expected.delay(300, 1)
expected.cx(0, 1)
expected.x(1)
expected.delay(160, 0)
expected.cx(0, 1)
expected.add_calibration("x", (0, ), xsched)
self.assertEqual(expected, scheduled)
def test_no_pad_very_end_of_circuit(self):
"""Test padding option that inserts no delay at the very end of circuit.
This circuit will be unchanged after ASAP-schedule/padding.
┌────────────────┐┌─┐
q_0: ┤ Delay(100[dt]) ├┤M├
└─────┬───┬──────┘└╥┘
q_1: ──────┤ X ├────────╫─
└───┘ ║
c: 1/═══════════════════╩═
0
"""
qc = QuantumCircuit(2, 1)
qc.delay(100, 0)
qc.x(1)
qc.measure(0, 0)
durations = InstructionDurations([("x", None, 160),
("measure", None, 1000)])
scheduled = PassManager([
ASAPScheduleAnalysis(durations),
PadDelay(fill_very_end=False),
]).run(qc)
self.assertEqual(scheduled, qc)
def test_padding_not_working_without_scheduling(self):
"""Test padding fails when un-scheduled DAG is input."""
qc = QuantumCircuit(1, 1)
qc.delay(100, 0)
qc.x(0)
qc.measure(0, 0)
with self.assertRaises(TranspilerError):
PassManager(PadDelay()).run(qc)
def test_hanh_echo_experiment_type(self):
"""Test Hahn echo experiment type circuit.
(input)
┌────┐┌────────────────┐┌───┐┌────────────────┐┌────┐┌─┐
q_0: ┤ √X ├┤ Delay(100[dt]) ├┤ X ├┤ Delay(100[dt]) ├┤ √X ├┤M├
└────┘└────────────────┘└───┘└────────────────┘└────┘└╥┘
c: 1/══════════════════════════════════════════════════════╩═
0
(output)
┌────┐┌────────────────┐┌───┐┌────────────────┐┌────┐┌──────────────┐┌─┐
q_0: ┤ √X ├┤ Delay(100[dt]) ├┤ X ├┤ Delay(100[dt]) ├┤ √X ├┤ Delay(8[dt]) ├┤M├
└────┘└────────────────┘└───┘└────────────────┘└────┘└──────────────┘└╥┘
c: 1/══════════════════════════════════════════════════════════════════════╩═
0
This type of experiment doesn't change duration of interest (two in the middle).
However induces slight delay less than alignment * dt before measurement.
This might induce extra amplitude damping error.
"""
circuit = QuantumCircuit(1, 1)
circuit.sx(0)
circuit.delay(100, 0, unit="dt")
circuit.x(0)
circuit.delay(100, 0, unit="dt")
circuit.sx(0)
circuit.measure(0, 0)
pm = PassManager([
# reproduce old behavior of 0.20.0 before #7655
# currently default write latency is 0
ALAPSchedule(
durations=self.instruction_durations,
clbit_write_latency=1600,
conditional_latency=0,
),
PadDelay(),
AlignMeasures(alignment=16),
])
aligned_circuit = pm.run(circuit)
ref_circuit = QuantumCircuit(1, 1)
ref_circuit.sx(0)
ref_circuit.delay(100, 0, unit="dt")
ref_circuit.x(0)
ref_circuit.delay(100, 0, unit="dt")
ref_circuit.sx(0)
ref_circuit.delay(8, 0, unit="dt")
ref_circuit.measure(0, 0)
self.assertEqual(aligned_circuit, ref_circuit)
def test_mid_circuit_measure(self):
"""Test circuit with mid circuit measurement.
(input)
┌───┐┌────────────────┐┌─┐┌───────────────┐┌───┐┌────────────────┐┌─┐
q_0: ┤ X ├┤ Delay(100[dt]) ├┤M├┤ Delay(10[dt]) ├┤ X ├┤ Delay(120[dt]) ├┤M├
└───┘└────────────────┘└╥┘└───────────────┘└───┘└────────────────┘└╥┘
c: 2/════════════════════════╩══════════════════════════════════════════╩═
0 1
(output)
┌───┐┌────────────────┐┌─┐┌───────────────┐┌───┐┌────────────────┐┌─┐
q_0: ┤ X ├┤ Delay(112[dt]) ├┤M├┤ Delay(10[dt]) ├┤ X ├┤ Delay(134[dt]) ├┤M├
└───┘└────────────────┘└╥┘└───────────────┘└───┘└────────────────┘└╥┘
c: 2/════════════════════════╩══════════════════════════════════════════╩═
0 1
Extra delay is always added to the existing delay right before the measurement.
Delay after measurement is unchanged.
"""
circuit = QuantumCircuit(1, 2)
circuit.x(0)
circuit.delay(100, 0, unit="dt")
circuit.measure(0, 0)
circuit.delay(10, 0, unit="dt")
circuit.x(0)
circuit.delay(120, 0, unit="dt")
circuit.measure(0, 1)
pm = PassManager([
# reproduce old behavior of 0.20.0 before #7655
# currently default write latency is 0
ALAPSchedule(
durations=self.instruction_durations,
clbit_write_latency=1600,
conditional_latency=0,
),
PadDelay(),
AlignMeasures(alignment=16),
])
aligned_circuit = pm.run(circuit)
ref_circuit = QuantumCircuit(1, 2)
ref_circuit.x(0)
ref_circuit.delay(112, 0, unit="dt")
ref_circuit.measure(0, 0)
ref_circuit.delay(10, 0, unit="dt")
ref_circuit.x(0)
ref_circuit.delay(134, 0, unit="dt")
ref_circuit.measure(0, 1)
self.assertEqual(aligned_circuit, ref_circuit)
def test_alap_agree_with_reverse_asap_reverse(self):
"""Test if ALAP schedule agrees with doubly-reversed ASAP schedule."""
qc = QuantumCircuit(2)
qc.h(0)
qc.delay(500, 1)
qc.cx(0, 1)
qc.measure_all()
durations = InstructionDurations([("h", 0, 200), ("cx", [0, 1], 700),
("measure", None, 1000)])
pm = PassManager([ALAPScheduleAnalysis(durations), PadDelay()])
alap_qc = pm.run(qc)
pm = PassManager([ASAPScheduleAnalysis(durations), PadDelay()])
new_qc = pm.run(qc.reverse_ops())
new_qc = new_qc.reverse_ops()
new_qc.name = new_qc.name
self.assertEqual(alap_qc, new_qc)
def test_t1_experiment_type(self):
"""Test T1 experiment type circuit.
(input)
┌───┐┌────────────────┐┌─┐
q_0: ┤ X ├┤ Delay(100[dt]) ├┤M├
└───┘└────────────────┘└╥┘
c: 1/════════════════════════╩═
0
(aligned)
┌───┐┌────────────────┐┌─┐
q_0: ┤ X ├┤ Delay(112[dt]) ├┤M├
└───┘└────────────────┘└╥┘
c: 1/════════════════════════╩═
0
This type of experiment slightly changes delay duration of interest.
However the quantization error should be less than alignment * dt.
"""
circuit = QuantumCircuit(1, 1)
circuit.x(0)
circuit.delay(100, 0, unit="dt")
circuit.measure(0, 0)
pm = PassManager([
# reproduce old behavior of 0.20.0 before #7655
# currently default write latency is 0
ALAPSchedule(
durations=self.instruction_durations,
clbit_write_latency=1600,
conditional_latency=0,
),
PadDelay(),
AlignMeasures(alignment=16),
])
aligned_circuit = pm.run(circuit)
ref_circuit = QuantumCircuit(1, 1)
ref_circuit.x(0)
ref_circuit.delay(112, 0, unit="dt")
ref_circuit.measure(0, 0)
self.assertEqual(aligned_circuit, ref_circuit)
def test_c_if_on_different_qubits(self, schedule_pass):
"""Test if ALAP/ASAP schedules circuits with `c_if`s on different qubits.
(input)
┌─┐
q_0: ┤M├──────────────────────
└╥┘ ┌───┐
q_1: ─╫────┤ X ├──────────────
║ └─╥─┘ ┌───┐
q_2: ─╫──────╫────────┤ X ├───
║ ║ └─╥─┘
║ ┌────╨────┐┌────╨────┐
c: 1/═╩═╡ c_0 = T ╞╡ c_0 = T ╞
0 └─────────┘└─────────┘
(scheduled)
┌─┐┌────────────────┐
q_0: ───────────────────┤M├┤ Delay(200[dt]) ├───────────
┌─────────────────┐└╥┘└─────┬───┬──────┘
q_1: ┤ Delay(1000[dt]) ├─╫───────┤ X ├──────────────────
├─────────────────┤ ║ └─╥─┘ ┌───┐
q_2: ┤ Delay(1000[dt]) ├─╫─────────╫────────────┤ X ├───
└─────────────────┘ ║ ║ └─╥─┘
║ ┌────╨────┐ ┌────╨────┐
c: 1/════════════════════╩════╡ c_0=0x1 ╞════╡ c_0=0x1 ╞
0 └─────────┘ └─────────┘
"""
qc = QuantumCircuit(3, 1)
qc.measure(0, 0)
qc.x(1).c_if(0, True)
qc.x(2).c_if(0, True)
durations = InstructionDurations([("x", None, 200),
("measure", None, 1000)])
pm = PassManager([schedule_pass(durations), PadDelay()])
scheduled = pm.run(qc)
expected = QuantumCircuit(3, 1)
expected.measure(0, 0)
expected.delay(1000, 1)
expected.delay(1000, 2)
expected.x(1).c_if(0, True)
expected.x(2).c_if(0, True)
expected.delay(200, 0)
self.assertEqual(expected, scheduled)
def test_measure_after_c_if(self, schedule_pass):
"""Test if ALAP/ASAP schedules circuits with c_if after measure with a common clbit.
(input)
┌─┐
q_0: ┤M├──────────────
└╥┘ ┌───┐
q_1: ─╫────┤ X ├──────
║ └─╥─┘ ┌─┐
q_2: ─╫──────╫─────┤M├
║ ┌────╨────┐└╥┘
c: 1/═╩═╡ c_0 = T ╞═╩═
0 └─────────┘ 0
(scheduled)
┌─┐┌─────────────────┐
q_0: ───────────────────┤M├┤ Delay(1000[dt]) ├──────────────────
┌─────────────────┐└╥┘└──────┬───┬──────┘┌────────────────┐
q_1: ┤ Delay(1000[dt]) ├─╫────────┤ X ├───────┤ Delay(800[dt]) ├
├─────────────────┤ ║ └─╥─┘ └──────┬─┬───────┘
q_2: ┤ Delay(1000[dt]) ├─╫──────────╫────────────────┤M├────────
└─────────────────┘ ║ ┌────╨────┐ └╥┘
c: 1/════════════════════╩═════╡ c_0=0x1 ╞════════════╩═════════
0 └─────────┘ 0
"""
qc = QuantumCircuit(3, 1)
qc.measure(0, 0)
qc.x(1).c_if(0, 1)
qc.measure(2, 0)
durations = InstructionDurations([("x", None, 200),
("measure", None, 1000)])
pm = PassManager([schedule_pass(durations), PadDelay()])
scheduled = pm.run(qc)
expected = QuantumCircuit(3, 1)
expected.delay(1000, 1)
expected.delay(1000, 2)
expected.measure(0, 0)
expected.x(1).c_if(0, 1)
expected.measure(2, 0)
expected.delay(1000, 0)
expected.delay(800, 1)
self.assertEqual(expected, scheduled)
def test_dag_introduces_extra_dependency_between_conditionals(self):
"""Test dependency between conditional operations in the scheduling.
In the below example circuit, the conditional x on q1 could start at time 0,
however it must be scheduled after the conditional x on q0 in ASAP scheduling.
That is because circuit model used in the transpiler passes (DAGCircuit)
interprets instructions acting on common clbits must be run in the order
given by the original circuit (QuantumCircuit).
(input)
┌────────────────┐ ┌───┐
q_0: ┤ Delay(100[dt]) ├───┤ X ├───
└─────┬───┬──────┘ └─╥─┘
q_1: ──────┤ X ├────────────╫─────
└─╥─┘ ║
┌────╨────┐ ┌────╨────┐
c: 1/═══╡ c_0=0x1 ╞════╡ c_0=0x1 ╞
└─────────┘ └─────────┘
(ASAP scheduled)
┌────────────────┐ ┌───┐
q_0: ┤ Delay(100[dt]) ├───┤ X ├──────────────
├────────────────┤ └─╥─┘ ┌───┐
q_1: ┤ Delay(100[dt]) ├─────╫────────┤ X ├───
└────────────────┘ ║ └─╥─┘
┌────╨────┐┌────╨────┐
c: 1/══════════════════╡ c_0=0x1 ╞╡ c_0=0x1 ╞
└─────────┘└─────────┘
"""
qc = QuantumCircuit(2, 1)
qc.delay(100, 0)
qc.x(0).c_if(0, True)
qc.x(1).c_if(0, True)
durations = InstructionDurations([("x", None, 160)])
pm = PassManager([ASAPScheduleAnalysis(durations), PadDelay()])
scheduled = pm.run(qc)
expected = QuantumCircuit(2, 1)
expected.delay(100, 0)
expected.delay(100, 1) # due to extra dependency on clbits
expected.x(0).c_if(0, True)
expected.x(1).c_if(0, True)
self.assertEqual(expected, scheduled)
def test_measure_after_measure(self, schedule_pass):
"""Test if ALAP/ASAP schedules circuits with measure after measure with a common clbit.
See: https://github.com/Qiskit/qiskit-terra/issues/7654
(input)
┌───┐┌─┐
q_0: ┤ X ├┤M├───
└───┘└╥┘┌─┐
q_1: ──────╫─┤M├
║ └╥┘
c: 1/══════╩══╩═
0 0
(scheduled)
┌───┐ ┌─┐┌─────────────────┐
q_0: ───────┤ X ├───────┤M├┤ Delay(1000[dt]) ├
┌──────┴───┴──────┐└╥┘└───────┬─┬───────┘
q_1: ┤ Delay(1200[dt]) ├─╫─────────┤M├────────
└─────────────────┘ ║ └╥┘
c: 1/════════════════════╩══════════╩═════════
0 0
"""
qc = QuantumCircuit(2, 1)
qc.x(0)
qc.measure(0, 0)
qc.measure(1, 0)
durations = InstructionDurations([("x", None, 200),
("measure", None, 1000)])
pm = PassManager([schedule_pass(durations), PadDelay()])
scheduled = pm.run(qc)
expected = QuantumCircuit(2, 1)
expected.x(0)
expected.measure(0, 0)
expected.delay(1200, 1)
expected.measure(1, 0)
expected.delay(1000, 0)
self.assertEqual(expected, scheduled)
def test_classically_controlled_gate_after_measure(self, schedule_pass):
"""Test if ALAP/ASAP schedules circuits with c_if after measure with a common clbit.
See: https://github.com/Qiskit/qiskit-terra/issues/7654
(input)
┌─┐
q_0: ┤M├───────────
└╥┘ ┌───┐
q_1: ─╫────┤ X ├───
║ └─╥─┘
║ ┌────╨────┐
c: 1/═╩═╡ c_0 = T ╞
0 └─────────┘
(scheduled)
┌─┐┌────────────────┐
q_0: ───────────────────┤M├┤ Delay(200[dt]) ├
┌─────────────────┐└╥┘└─────┬───┬──────┘
q_1: ┤ Delay(1000[dt]) ├─╫───────┤ X ├───────
└─────────────────┘ ║ └─╥─┘
║ ┌────╨────┐
c: 1/════════════════════╩════╡ c_0=0x1 ╞════
0 └─────────┘
"""
qc = QuantumCircuit(2, 1)
qc.measure(0, 0)
qc.x(1).c_if(0, True)
durations = InstructionDurations([("x", None, 200),
("measure", None, 1000)])
pm = PassManager([schedule_pass(durations), PadDelay()])
scheduled = pm.run(qc)
expected = QuantumCircuit(2, 1)
expected.measure(0, 0)
expected.delay(1000, 1) # x.c_if starts after measure
expected.x(1).c_if(0, True)
expected.delay(200, 0)
self.assertEqual(expected, scheduled)
def test_shorter_measure_after_measure(self, schedule_pass):
"""Test if ALAP/ASAP schedules circuits with shorter measure after measure with a common clbit.
(input)
┌─┐
q_0: ┤M├───
└╥┘┌─┐
q_1: ─╫─┤M├
║ └╥┘
c: 1/═╩══╩═
0 0
(scheduled)
┌─┐┌────────────────┐
q_0: ───────────────────┤M├┤ Delay(700[dt]) ├
┌─────────────────┐└╥┘└──────┬─┬───────┘
q_1: ┤ Delay(1000[dt]) ├─╫────────┤M├────────
└─────────────────┘ ║ └╥┘
c: 1/════════════════════╩═════════╩═════════
0 0
"""
qc = QuantumCircuit(2, 1)
qc.measure(0, 0)
qc.measure(1, 0)
durations = InstructionDurations([("measure", [0], 1000),
("measure", [1], 700)])
pm = PassManager([schedule_pass(durations), PadDelay()])
scheduled = pm.run(qc)
expected = QuantumCircuit(2, 1)
expected.measure(0, 0)
expected.delay(1000, 1)
expected.measure(1, 0)
expected.delay(700, 0)
self.assertEqual(expected, scheduled)
def test_both_pulse_and_acquire_alignment(self):
"""Test when both acquire and pulse alignment are specified.
(input)
┌────────────────┐┌───┐┌───────────────┐┌─┐
q: ┤ Delay(100[dt]) ├┤ X ├┤ Delay(10[dt]) ├┤M├
└────────────────┘└───┘└───────────────┘└╥┘
c: 1/═════════════════════════════════════════╩═
0
(aligned)
┌────────────────┐┌───┐┌───────────────┐┌─┐
q: ┤ Delay(112[dt]) ├┤ X ├┤ Delay(16[dt]) ├┤M├
└────────────────┘└───┘└───────────────┘└╥┘
c: 1/═════════════════════════════════════════╩═
0
"""
pm = PassManager([
ALAPScheduleAnalysis(durations=self.instruction_durations),
ConstrainedReschedule(pulse_alignment=16, acquire_alignment=16),
PadDelay(fill_very_end=False),
])
circuit = QuantumCircuit(1, 1)
circuit.delay(100, 0, unit="dt")
circuit.x(0)
circuit.delay(10, 0, unit="dt")
circuit.measure(0, 0)
ref_circ = QuantumCircuit(1, 1)
ref_circ.delay(112, 0, unit="dt")
ref_circ.x(0)
ref_circ.delay(16, 0, unit="dt")
ref_circ.measure(0, 0)
self.assertEqual(pm.run(circuit), ref_circ)
def level_0_pass_manager(
pass_manager_config: PassManagerConfig) -> PassManager:
"""Level 0 pass manager: no explicit optimization other than mapping to backend.
This pass manager applies the user-given initial layout. If none is given, a trivial
layout consisting of mapping the i-th virtual qubit to the i-th physical qubit is used.
Any unused physical qubit is allocated as ancilla space.
The pass manager then unrolls the circuit to the desired basis, and transforms the
circuit to match the coupling map.
Note:
In simulators where ``coupling_map=None``, only the unrolling and
optimization stages are done.
Args:
pass_manager_config: configuration of the pass manager.
Returns:
a level 0 pass manager.
Raises:
TranspilerError: if the passmanager config is invalid.
"""
basis_gates = pass_manager_config.basis_gates
inst_map = pass_manager_config.inst_map
coupling_map = pass_manager_config.coupling_map
initial_layout = pass_manager_config.initial_layout
layout_method = pass_manager_config.layout_method or "trivial"
routing_method = pass_manager_config.routing_method or "stochastic"
translation_method = pass_manager_config.translation_method or "translator"
scheduling_method = pass_manager_config.scheduling_method
instruction_durations = pass_manager_config.instruction_durations
seed_transpiler = pass_manager_config.seed_transpiler
backend_properties = pass_manager_config.backend_properties
approximation_degree = pass_manager_config.approximation_degree
timing_constraints = pass_manager_config.timing_constraints or TimingConstraints(
)
unitary_synthesis_method = pass_manager_config.unitary_synthesis_method
unitary_synthesis_plugin_config = pass_manager_config.unitary_synthesis_plugin_config
target = pass_manager_config.target
# 1. Decompose so only 1-qubit and 2-qubit gates remain
_unroll3q = [
# Use unitary synthesis for basis aware decomposition of UnitaryGates
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
method=unitary_synthesis_method,
min_qubits=3,
plugin_config=unitary_synthesis_plugin_config,
target=target,
),
Unroll3qOrMore(),
]
# 2. Choose an initial layout if not set by user (default: trivial layout)
_given_layout = SetLayout(initial_layout)
def _choose_layout_condition(property_set):
return not property_set["layout"]
if layout_method == "trivial":
_choose_layout = TrivialLayout(coupling_map)
elif layout_method == "dense":
_choose_layout = DenseLayout(coupling_map,
backend_properties,
target=target)
elif layout_method == "noise_adaptive":
_choose_layout = NoiseAdaptiveLayout(backend_properties)
elif layout_method == "sabre":
_choose_layout = SabreLayout(coupling_map,
max_iterations=1,
seed=seed_transpiler)
else:
raise TranspilerError("Invalid layout method %s." % layout_method)
# 3. Extend dag/layout with ancillas using the full coupling map
_embed = [
FullAncillaAllocation(coupling_map),
EnlargeWithAncilla(),
ApplyLayout()
]
# 4. Swap to fit the coupling map
_swap_check = CheckMap(coupling_map)
def _swap_condition(property_set):
return not property_set["is_swap_mapped"]
_swap = [BarrierBeforeFinalMeasurements()]
if routing_method == "basic":
_swap += [BasicSwap(coupling_map)]
elif routing_method == "stochastic":
_swap += [
StochasticSwap(coupling_map, trials=20, seed=seed_transpiler)
]
elif routing_method == "lookahead":
_swap += [LookaheadSwap(coupling_map, search_depth=2, search_width=2)]
elif routing_method == "sabre":
_swap += [
SabreSwap(coupling_map, heuristic="basic", seed=seed_transpiler)
]
elif routing_method == "none":
_swap += [
Error(
msg=
("No routing method selected, but circuit is not routed to device. "
"CheckMap Error: {check_map_msg}"),
action="raise",
)
]
else:
raise TranspilerError("Invalid routing method %s." % routing_method)
# 5. Unroll to the basis
if translation_method == "unroller":
_unroll = [Unroller(basis_gates)]
elif translation_method == "translator":
from qiskit.circuit.equivalence_library import SessionEquivalenceLibrary as sel
_unroll = [
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
backend_props=backend_properties,
method=unitary_synthesis_method,
plugin_config=unitary_synthesis_plugin_config,
target=target,
),
UnrollCustomDefinitions(sel, basis_gates),
BasisTranslator(sel, basis_gates, target),
]
elif translation_method == "synthesis":
_unroll = [
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
backend_props=backend_properties,
method=unitary_synthesis_method,
min_qubits=3,
plugin_config=unitary_synthesis_plugin_config,
target=target,
),
Unroll3qOrMore(),
Collect2qBlocks(),
Collect1qRuns(),
ConsolidateBlocks(basis_gates=basis_gates, target=target),
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
backend_props=backend_properties,
method=unitary_synthesis_method,
plugin_config=unitary_synthesis_plugin_config,
target=target,
),
]
else:
raise TranspilerError("Invalid translation method %s." %
translation_method)
# 6. Fix any bad CX directions
_direction_check = [CheckGateDirection(coupling_map, target)]
def _direction_condition(property_set):
return not property_set["is_direction_mapped"]
_direction = [GateDirection(coupling_map, target)]
# Build pass manager
pm0 = PassManager()
if coupling_map or initial_layout:
pm0.append(_given_layout)
pm0.append(_unroll3q)
pm0.append(_choose_layout, condition=_choose_layout_condition)
pm0.append(_embed)
pm0.append(_swap_check)
pm0.append(_swap, condition=_swap_condition)
pm0.append(_unroll)
if (coupling_map and not coupling_map.is_symmetric) or (
target is not None
and target.get_non_global_operation_names(strict_direction=True)):
pm0.append(_direction_check)
pm0.append(_direction, condition=_direction_condition)
pm0.append(_unroll)
if inst_map and inst_map.has_custom_gate():
pm0.append(PulseGates(inst_map=inst_map))
# 7. Unify all durations (either SI, or convert to dt if known)
# Schedule the circuit only when scheduling_method is supplied
# Apply alignment analysis regardless of scheduling for delay validation.
if scheduling_method:
# Do scheduling after unit conversion.
scheduler = {
"alap": ALAPScheduleAnalysis,
"as_late_as_possible": ALAPScheduleAnalysis,
"asap": ASAPScheduleAnalysis,
"as_soon_as_possible": ASAPScheduleAnalysis,
}
pm0.append(TimeUnitConversion(instruction_durations))
try:
pm0.append(scheduler[scheduling_method](instruction_durations))
except KeyError as ex:
raise TranspilerError("Invalid scheduling method %s." %
scheduling_method) from ex
elif instruction_durations:
# No scheduling. But do unit conversion for delays.
def _contains_delay(property_set):
return property_set["contains_delay"]
pm0.append(ContainsInstruction("delay"))
pm0.append(TimeUnitConversion(instruction_durations),
condition=_contains_delay)
if (timing_constraints.granularity != 1
or timing_constraints.min_length != 1
or timing_constraints.acquire_alignment != 1
or timing_constraints.pulse_alignment != 1):
# Run alignment analysis regardless of scheduling.
def _require_alignment(property_set):
return property_set["reschedule_required"]
pm0.append(
InstructionDurationCheck(
acquire_alignment=timing_constraints.acquire_alignment,
pulse_alignment=timing_constraints.pulse_alignment,
))
pm0.append(
ConstrainedReschedule(
acquire_alignment=timing_constraints.acquire_alignment,
pulse_alignment=timing_constraints.pulse_alignment,
),
condition=_require_alignment,
)
pm0.append(
ValidatePulseGates(
granularity=timing_constraints.granularity,
min_length=timing_constraints.min_length,
))
if scheduling_method:
# Call padding pass if circuit is scheduled
pm0.append(PadDelay())
return pm0
def test_parallel_gate_different_length(self):
"""Test circuit having two parallel instruction with different length.
(input)
┌───┐┌─┐
q_0: ┤ X ├┤M├───
├───┤└╥┘┌─┐
q_1: ┤ X ├─╫─┤M├
└───┘ ║ └╥┘
c: 2/══════╩══╩═
0 1
(expected, ALAP)
┌────────────────┐┌───┐┌─┐
q_0: ┤ Delay(200[dt]) ├┤ X ├┤M├
└─────┬───┬──────┘└┬─┬┘└╥┘
q_1: ──────┤ X ├────────┤M├──╫─
└───┘ └╥┘ ║
c: 2/════════════════════╩═══╩═
1 0
(expected, ASAP)
┌───┐┌─┐┌────────────────┐
q_0: ┤ X ├┤M├┤ Delay(200[dt]) ├
├───┤└╥┘└──────┬─┬───────┘
q_1: ┤ X ├─╫────────┤M├────────
└───┘ ║ └╥┘
c: 2/══════╩═════════╩═════════
0 1
"""
qc = QuantumCircuit(2, 2)
qc.x(0)
qc.x(1)
qc.measure(0, 0)
qc.measure(1, 1)
durations = InstructionDurations([("x", [0], 200), ("x", [1], 400),
("measure", None, 1000)])
pm = PassManager([ALAPSchedule(durations), PadDelay()])
qc_alap = pm.run(qc)
alap_expected = QuantumCircuit(2, 2)
alap_expected.delay(200, 0)
alap_expected.x(0)
alap_expected.x(1)
alap_expected.measure(0, 0)
alap_expected.measure(1, 1)
self.assertEqual(qc_alap, alap_expected)
pm = PassManager([ASAPSchedule(durations), PadDelay()])
qc_asap = pm.run(qc)
asap_expected = QuantumCircuit(2, 2)
asap_expected.x(0)
asap_expected.x(1)
asap_expected.measure(0, 0) # immediately start after X gate
asap_expected.measure(1, 1)
asap_expected.delay(200, 0)
self.assertEqual(qc_asap, asap_expected)
def generate_scheduling(instruction_durations, scheduling_method,
timing_constraints, inst_map):
"""Generate a post optimization scheduling :class:`~qiskit.transpiler.PassManager`
Args:
instruction_durations (dict): The dictionary of instruction durations
scheduling_method (str): The scheduling method to use, can either be
``'asap'``/``'as_soon_as_possible'`` or
``'alap'``/``'as_late_as_possible'``
timing_constraints (TimingConstraints): Hardware time alignment restrictions.
inst_map (InstructionScheduleMap): Mapping object that maps gate to schedule.
Returns:
PassManager: The scheduling pass manager
Raises:
TranspilerError: If the ``scheduling_method`` kwarg is not a valid value
"""
scheduling = PassManager()
if inst_map and inst_map.has_custom_gate():
scheduling.append(PulseGates(inst_map=inst_map))
if scheduling_method:
# Do scheduling after unit conversion.
scheduler = {
"alap": ALAPScheduleAnalysis,
"as_late_as_possible": ALAPScheduleAnalysis,
"asap": ASAPScheduleAnalysis,
"as_soon_as_possible": ASAPScheduleAnalysis,
}
scheduling.append(TimeUnitConversion(instruction_durations))
try:
scheduling.append(
scheduler[scheduling_method](instruction_durations))
except KeyError as ex:
raise TranspilerError("Invalid scheduling method %s." %
scheduling_method) from ex
elif instruction_durations:
# No scheduling. But do unit conversion for delays.
def _contains_delay(property_set):
return property_set["contains_delay"]
scheduling.append(ContainsInstruction("delay"))
scheduling.append(TimeUnitConversion(instruction_durations),
condition=_contains_delay)
if (timing_constraints.granularity != 1
or timing_constraints.min_length != 1
or timing_constraints.acquire_alignment != 1
or timing_constraints.pulse_alignment != 1):
# Run alignment analysis regardless of scheduling.
def _require_alignment(property_set):
return property_set["reschedule_required"]
scheduling.append(
InstructionDurationCheck(
acquire_alignment=timing_constraints.acquire_alignment,
pulse_alignment=timing_constraints.pulse_alignment,
))
scheduling.append(
ConstrainedReschedule(
acquire_alignment=timing_constraints.acquire_alignment,
pulse_alignment=timing_constraints.pulse_alignment,
),
condition=_require_alignment,
)
scheduling.append(
ValidatePulseGates(
granularity=timing_constraints.granularity,
min_length=timing_constraints.min_length,
))
if scheduling_method:
# Call padding pass if circuit is scheduled
scheduling.append(PadDelay())
return scheduling
def test_mid_circuit_multiq_gates(self):
"""Test circuit with mid circuit measurement and multi qubit gates.
(input)
┌───┐┌────────────────┐┌─┐ ┌─┐
q_0: ┤ X ├┤ Delay(100[dt]) ├┤M├──■───────■──┤M├
└───┘└────────────────┘└╥┘┌─┴─┐┌─┐┌─┴─┐└╥┘
q_1: ────────────────────────╫─┤ X ├┤M├┤ X ├─╫─
║ └───┘└╥┘└───┘ ║
c: 2/════════════════════════╩═══════╩═══════╩═
0 1 0
(output)
┌───┐ ┌────────────────┐┌─┐ ┌─────────────────┐ ┌─┐»
q_0: ───────┤ X ├───────┤ Delay(112[dt]) ├┤M├──■──┤ Delay(1600[dt]) ├──■──┤M├»
┌──────┴───┴──────┐└────────────────┘└╥┘┌─┴─┐└───────┬─┬───────┘┌─┴─┐└╥┘»
q_1: ┤ Delay(1872[dt]) ├───────────────────╫─┤ X ├────────┤M├────────┤ X ├─╫─»
└─────────────────┘ ║ └───┘ └╥┘ └───┘ ║ »
c: 2/══════════════════════════════════════╩═══════════════╩═══════════════╩═»
0 1 0 »
«
«q_0: ───────────────────
« ┌─────────────────┐
«q_1: ┤ Delay(1600[dt]) ├
« └─────────────────┘
«c: 2/═══════════════════
«
Delay for the other channel paired by multi-qubit instruction is also scheduled.
Delay (1872dt) = X (160dt) + Delay (100dt + extra 12dt) + Measure (1600dt).
"""
circuit = QuantumCircuit(2, 2)
circuit.x(0)
circuit.delay(100, 0, unit="dt")
circuit.measure(0, 0)
circuit.cx(0, 1)
circuit.measure(1, 1)
circuit.cx(0, 1)
circuit.measure(0, 0)
pm = PassManager([
# reproduce old behavior of 0.20.0 before #7655
# currently default write latency is 0
SetIOLatency(clbit_write_latency=1600, conditional_latency=0),
ALAPScheduleAnalysis(durations=self.instruction_durations),
ConstrainedReschedule(acquire_alignment=16),
PadDelay(),
])
aligned_circuit = pm.run(circuit)
ref_circuit = QuantumCircuit(2, 2)
ref_circuit.x(0)
ref_circuit.delay(112, 0, unit="dt")
ref_circuit.measure(0, 0)
ref_circuit.delay(160 + 112 + 1600, 1, unit="dt")
ref_circuit.cx(0, 1)
ref_circuit.delay(1600, 0, unit="dt")
ref_circuit.measure(1, 1)
ref_circuit.cx(0, 1)
ref_circuit.delay(1600, 1, unit="dt")
ref_circuit.measure(0, 0)
self.assertEqual(aligned_circuit, ref_circuit)
def test_random_complicated_circuit(self):
"""Test scheduling complicated circuit with control flow.
(input)
┌────────────────┐ ┌───┐ ░ ┌───┐ »
q_0: ┤ Delay(100[dt]) ├───┤ X ├────░──────────────────┤ X ├───»
└────────────────┘ └─╥─┘ ░ ┌───┐ └─╥─┘ »
q_1: ───────────────────────╫──────░───────┤ X ├────────╫─────»
║ ░ ┌─┐ └─╥─┘ ║ »
q_2: ───────────────────────╫──────░─┤M├─────╫──────────╫─────»
┌────╨────┐ ░ └╥┘┌────╨────┐┌────╨────┐»
c: 1/══════════════════╡ c_0=0x1 ╞════╩═╡ c_0=0x0 ╞╡ c_0=0x0 ╞»
└─────────┘ 0 └─────────┘└─────────┘»
« ┌────────────────┐┌───┐
«q_0: ┤ Delay(300[dt]) ├┤ X ├─────■─────
« └────────────────┘└───┘ ┌─┴─┐
«q_1: ────────■─────────────────┤ X ├───
« ┌─┴─┐ ┌─┐ └─╥─┘
«q_2: ──────┤ X ├────────┤M├──────╫─────
« └───┘ └╥┘ ┌────╨────┐
«c: 1/════════════════════╩══╡ c_0=0x0 ╞
« 0 └─────────┘
(ASAP scheduled) duration = 2800 dt
┌────────────────┐ ┌───┐ ░ ┌─────────────────┐ »
q_0: ┤ Delay(200[dt]) ├───┤ X ├────░─┤ Delay(1400[dt]) ├───────────»
├────────────────┤ └─╥─┘ ░ ├─────────────────┤ ┌───┐ »
q_1: ┤ Delay(300[dt]) ├─────╫──────░─┤ Delay(1200[dt]) ├───┤ X ├───»
├────────────────┤ ║ ░ └───────┬─┬───────┘ └─╥─┘ »
q_2: ┤ Delay(300[dt]) ├─────╫──────░─────────┤M├─────────────╫─────»
└────────────────┘┌────╨────┐ ░ └╥┘ ┌────╨────┐»
c: 1/══════════════════╡ c_0=0x1 ╞════════════╩═════════╡ c_0=0x0 ╞»
└─────────┘ 0 └─────────┘»
« ┌───┐ ┌────────────────┐ ┌───┐ »
«q_0: ─────────────────────┤ X ├───┤ Delay(300[dt]) ├──────┤ X ├───────»
« └─╥─┘ └────────────────┘┌─────┴───┴──────┐»
«q_1: ───────────────────────╫─────────────■─────────┤ Delay(400[dt]) ├»
« ┌────────────────┐ ║ ┌─┴─┐ ├────────────────┤»
«q_2: ┤ Delay(300[dt]) ├─────╫───────────┤ X ├───────┤ Delay(300[dt]) ├»
« └────────────────┘┌────╨────┐ └───┘ └────────────────┘»
«c: 1/══════════════════╡ c_0=0x0 ╞════════════════════════════════════»
« └─────────┘ »
« ┌────────────────┐
«q_0: ─────■─────┤ Delay(700[dt]) ├
« ┌─┴─┐ ├────────────────┤
«q_1: ───┤ X ├───┤ Delay(700[dt]) ├
« └─╥─┘ └──────┬─┬───────┘
«q_2: ─────╫────────────┤M├────────
« ┌────╨────┐ └╥┘
«c: 1/╡ c_0=0x0 ╞════════╩═════════
« └─────────┘ 0
(ALAP scheduled) duration = 3100
┌────────────────┐ ┌───┐ ░ ┌─────────────────┐ »
q_0: ┤ Delay(200[dt]) ├───┤ X ├────░─┤ Delay(1400[dt]) ├───────────»
├────────────────┤ └─╥─┘ ░ ├─────────────────┤ ┌───┐ »
q_1: ┤ Delay(300[dt]) ├─────╫──────░─┤ Delay(1200[dt]) ├───┤ X ├───»
├────────────────┤ ║ ░ └───────┬─┬───────┘ └─╥─┘ »
q_2: ┤ Delay(300[dt]) ├─────╫──────░─────────┤M├─────────────╫─────»
└────────────────┘┌────╨────┐ ░ └╥┘ ┌────╨────┐»
c: 1/══════════════════╡ c_0=0x1 ╞════════════╩═════════╡ c_0=0x0 ╞»
└─────────┘ 0 └─────────┘»
« ┌───┐ ┌────────────────┐ ┌───┐ »
«q_0: ─────────────────────┤ X ├───┤ Delay(300[dt]) ├──────┤ X ├───────»
« ┌────────────────┐ └─╥─┘ └────────────────┘┌─────┴───┴──────┐»
«q_1: ┤ Delay(300[dt]) ├─────╫─────────────■─────────┤ Delay(100[dt]) ├»
« ├────────────────┤ ║ ┌─┴─┐ └──────┬─┬───────┘»
«q_2: ┤ Delay(600[dt]) ├─────╫───────────┤ X ├──────────────┤M├────────»
« └────────────────┘┌────╨────┐ └───┘ └╥┘ »
«c: 1/══════════════════╡ c_0=0x0 ╞══════════════════════════╩═════════»
« └─────────┘ 0 »
« ┌────────────────┐
«q_0: ─────■─────┤ Delay(700[dt]) ├
« ┌─┴─┐ ├────────────────┤
«q_1: ───┤ X ├───┤ Delay(700[dt]) ├
« └─╥─┘ └────────────────┘
«q_2: ─────╫───────────────────────
« ┌────╨────┐
«c: 1/╡ c_0=0x0 ╞══════════════════
« └─────────┘
"""
qc = QuantumCircuit(3, 1)
qc.delay(100, 0)
qc.x(0).c_if(0, 1)
qc.barrier()
qc.measure(2, 0)
qc.x(1).c_if(0, 0)
qc.x(0).c_if(0, 0)
qc.delay(300, 0)
qc.cx(1, 2)
qc.x(0)
qc.cx(0, 1).c_if(0, 0)
qc.measure(2, 0)
durations = InstructionDurations([("x", None, 100),
("measure", None, 1000),
("cx", None, 200)])
actual_asap = PassManager([
SetIOLatency(clbit_write_latency=100, conditional_latency=200),
ASAPScheduleAnalysis(durations),
PadDelay(),
]).run(qc)
actual_alap = PassManager([
SetIOLatency(clbit_write_latency=100, conditional_latency=200),
ALAPScheduleAnalysis(durations),
PadDelay(),
]).run(qc)
expected_asap = QuantumCircuit(3, 1)
expected_asap.delay(200, 0) # due to conditional latency of 200dt
expected_asap.delay(300, 1)
expected_asap.delay(300, 2)
expected_asap.x(0).c_if(0, 1)
expected_asap.barrier()
expected_asap.delay(1400, 0)
expected_asap.delay(1200, 1)
expected_asap.measure(2, 0)
expected_asap.x(1).c_if(0, 0)
expected_asap.x(0).c_if(0, 0)
expected_asap.delay(300, 0)
expected_asap.x(0)
expected_asap.delay(300, 2)
expected_asap.cx(1, 2)
expected_asap.delay(400, 1)
expected_asap.cx(0, 1).c_if(0, 0)
expected_asap.delay(700,
0) # creg is released at t0 of cx(0,1).c_if(0,0)
expected_asap.delay(
700, 1
) # no creg write until 100dt. thus measure can move left by 300dt.
expected_asap.delay(300, 2)
expected_asap.measure(2, 0)
self.assertEqual(expected_asap, actual_asap)
self.assertEqual(actual_asap.duration, 3100)
expected_alap = QuantumCircuit(3, 1)
expected_alap.delay(200, 0) # due to conditional latency of 200dt
expected_alap.delay(300, 1)
expected_alap.delay(300, 2)
expected_alap.x(0).c_if(0, 1)
expected_alap.barrier()
expected_alap.delay(1400, 0)
expected_alap.delay(1200, 1)
expected_alap.measure(2, 0)
expected_alap.x(1).c_if(0, 0)
expected_alap.x(0).c_if(0, 0)
expected_alap.delay(300, 0)
expected_alap.x(0)
expected_alap.delay(300, 1)
expected_alap.delay(600, 2)
expected_alap.cx(1, 2)
expected_alap.delay(100, 1)
expected_alap.cx(0, 1).c_if(0, 0)
expected_alap.measure(2, 0)
expected_alap.delay(700, 0)
expected_alap.delay(700, 1)
self.assertEqual(expected_alap, actual_alap)
self.assertEqual(actual_alap.duration, 3100)
def test_circuit_using_clbit(self):
"""Test a circuit with instructions using a common clbit.
(input)
┌───┐┌────────────────┐┌─┐
q_0: ┤ X ├┤ Delay(100[dt]) ├┤M├──────────────
└───┘└────────────────┘└╥┘ ┌───┐
q_1: ────────────────────────╫────┤ X ├──────
║ └─╥─┘ ┌─┐
q_2: ────────────────────────╫──────╫─────┤M├
║ ┌────╨────┐└╥┘
c: 1/════════════════════════╩═╡ c_0 = T ╞═╩═
0 └─────────┘ 0
(aligned)
┌───┐ ┌────────────────┐┌─┐┌────────────────┐
q_0: ───────┤ X ├───────┤ Delay(112[dt]) ├┤M├┤ Delay(160[dt]) ├───
┌──────┴───┴──────┐└────────────────┘└╥┘└─────┬───┬──────┘
q_1: ┤ Delay(1872[dt]) ├───────────────────╫───────┤ X ├──────────
└┬────────────────┤ ║ └─╥─┘ ┌─┐
q_2: ─┤ Delay(432[dt]) ├───────────────────╫─────────╫─────────┤M├
└────────────────┘ ║ ┌────╨────┐ └╥┘
c: 1/══════════════════════════════════════╩════╡ c_0 = T ╞═════╩═
0 └─────────┘ 0
Looking at the q_0, the total schedule length T becomes
160 (x) + 112 (aligned delay) + 1600 (measure) + 160 (delay) = 2032.
The last delay comes from ALAP scheduling called before the AlignMeasure pass,
which aligns stop times as late as possible, so the start time of x(1).c_if(0)
and the stop time of measure(0, 0) become T - 160.
"""
circuit = QuantumCircuit(3, 1)
circuit.x(0)
circuit.delay(100, 0, unit="dt")
circuit.measure(0, 0)
circuit.x(1).c_if(0, 1)
circuit.measure(2, 0)
pm = PassManager([
# reproduce old behavior of 0.20.0 before #7655
# currently default write latency is 0
SetIOLatency(clbit_write_latency=1600, conditional_latency=0),
ALAPScheduleAnalysis(durations=self.instruction_durations),
ConstrainedReschedule(acquire_alignment=16),
PadDelay(fill_very_end=False),
])
aligned_circuit = pm.run(circuit)
self.assertEqual(aligned_circuit.duration, 2032)
ref_circuit = QuantumCircuit(3, 1)
ref_circuit.x(0)
ref_circuit.delay(112, 0, unit="dt")
ref_circuit.delay(1872, 1, unit="dt") # 2032 - 160
ref_circuit.delay(432, 2, unit="dt") # 2032 - 1600
ref_circuit.measure(0, 0)
ref_circuit.x(1).c_if(0, 1)
ref_circuit.measure(2, 0)
self.assertEqual(aligned_circuit, ref_circuit)
def test_measure_after_c_if_on_edge_locking(self):
"""Test if ALAP/ASAP schedules circuits with c_if after measure with a common clbit.
The scheduler is configured to reproduce behavior of the 0.20.0,
in which clbit lock is applied to the end-edge of measure instruction.
See https://github.com/Qiskit/qiskit-terra/pull/7655
(input)
┌─┐
q_0: ┤M├──────────────
└╥┘ ┌───┐
q_1: ─╫────┤ X ├──────
║ └─╥─┘ ┌─┐
q_2: ─╫──────╫─────┤M├
║ ┌────╨────┐└╥┘
c: 1/═╩═╡ c_0 = T ╞═╩═
0 └─────────┘ 0
(ASAP scheduled)
┌─┐┌────────────────┐
q_0: ───────────────────┤M├┤ Delay(200[dt]) ├─────────────────────
┌─────────────────┐└╥┘└─────┬───┬──────┘
q_1: ┤ Delay(1000[dt]) ├─╫───────┤ X ├────────────────────────────
└─────────────────┘ ║ └─╥─┘ ┌─┐┌────────────────┐
q_2: ────────────────────╫─────────╫─────────┤M├┤ Delay(200[dt]) ├
║ ┌────╨────┐ └╥┘└────────────────┘
c: 1/════════════════════╩════╡ c_0=0x1 ╞═════╩═══════════════════
0 └─────────┘ 0
(ALAP scheduled)
┌─┐┌────────────────┐
q_0: ───────────────────┤M├┤ Delay(200[dt]) ├───
┌─────────────────┐└╥┘└─────┬───┬──────┘
q_1: ┤ Delay(1000[dt]) ├─╫───────┤ X ├──────────
└┬────────────────┤ ║ └─╥─┘ ┌─┐
q_2: ─┤ Delay(200[dt]) ├─╫─────────╫─────────┤M├
└────────────────┘ ║ ┌────╨────┐ └╥┘
c: 1/════════════════════╩════╡ c_0=0x1 ╞═════╩═
0 └─────────┘ 0
"""
qc = QuantumCircuit(3, 1)
qc.measure(0, 0)
qc.x(1).c_if(0, 1)
qc.measure(2, 0)
durations = InstructionDurations([("x", None, 200),
("measure", None, 1000)])
# lock at the end edge
actual_asap = PassManager([
SetIOLatency(clbit_write_latency=1000),
ASAPScheduleAnalysis(durations),
PadDelay(),
]).run(qc)
actual_alap = PassManager([
SetIOLatency(clbit_write_latency=1000),
ALAPScheduleAnalysis(durations),
PadDelay(),
]).run(qc)
# start times of 2nd measure depends on ASAP/ALAP
expected_asap = QuantumCircuit(3, 1)
expected_asap.measure(0, 0)
expected_asap.delay(1000, 1)
expected_asap.x(1).c_if(0, 1)
expected_asap.measure(2, 0)
expected_asap.delay(200, 0)
expected_asap.delay(200, 2)
self.assertEqual(expected_asap, actual_asap)
expected_alap = QuantumCircuit(3, 1)
expected_alap.measure(0, 0)
expected_alap.delay(1000, 1)
expected_alap.x(1).c_if(0, 1)
expected_alap.delay(200, 2)
expected_alap.measure(2, 0)
expected_alap.delay(200, 0)
self.assertEqual(expected_alap, actual_alap)
def test_parallel_gate_different_length_with_barrier(self):
"""Test circuit having two parallel instruction with different length with barrier.
(input)
┌───┐┌─┐
q_0: ┤ X ├┤M├───
├───┤└╥┘┌─┐
q_1: ┤ X ├─╫─┤M├
└───┘ ║ └╥┘
c: 2/══════╩══╩═
0 1
(expected, ALAP)
┌────────────────┐┌───┐ ░ ┌─┐
q_0: ┤ Delay(200[dt]) ├┤ X ├─░─┤M├───
└─────┬───┬──────┘└───┘ ░ └╥┘┌─┐
q_1: ──────┤ X ├─────────────░──╫─┤M├
└───┘ ░ ║ └╥┘
c: 2/═══════════════════════════╩══╩═
0 1
(expected, ASAP)
┌───┐┌────────────────┐ ░ ┌─┐
q_0: ┤ X ├┤ Delay(200[dt]) ├─░─┤M├───
├───┤└────────────────┘ ░ └╥┘┌─┐
q_1: ┤ X ├───────────────────░──╫─┤M├
└───┘ ░ ║ └╥┘
c: 2/═══════════════════════════╩══╩═
0 1
"""
qc = QuantumCircuit(2, 2)
qc.x(0)
qc.x(1)
qc.barrier()
qc.measure(0, 0)
qc.measure(1, 1)
durations = InstructionDurations([("x", [0], 200), ("x", [1], 400),
("measure", None, 1000)])
pm = PassManager([ALAPScheduleAnalysis(durations), PadDelay()])
qc_alap = pm.run(qc)
alap_expected = QuantumCircuit(2, 2)
alap_expected.delay(200, 0)
alap_expected.x(0)
alap_expected.x(1)
alap_expected.barrier()
alap_expected.measure(0, 0)
alap_expected.measure(1, 1)
self.assertEqual(qc_alap, alap_expected)
pm = PassManager([ASAPScheduleAnalysis(durations), PadDelay()])
qc_asap = pm.run(qc)
asap_expected = QuantumCircuit(2, 2)
asap_expected.x(0)
asap_expected.delay(200, 0)
asap_expected.x(1)
asap_expected.barrier()
asap_expected.measure(0, 0)
asap_expected.measure(1, 1)
self.assertEqual(qc_asap, asap_expected)
def test_programmed_delay_preserved(self):
"""Intentionally programmed delay will be kept after reschedule.
No delay
++++++++
(input)
┌────────────────┐┌───┐ ░ ┌───┐
q_0: ┤ Delay(100[dt]) ├┤ X ├─░─┤ X ├
├────────────────┤└───┘ ░ └───┘
q_1: ┤ Delay(272[dt]) ├──────░──────
└────────────────┘ ░
(aligned)
┌────────────────┐┌───┐ ░ ┌───┐
q_0: ┤ Delay(112[dt]) ├┤ X ├─░─┤ X ├
├────────────────┤└───┘ ░ └───┘
q_1: ┤ Delay(272[dt]) ├──────░──────
└────────────────┘ ░
With delay (intentional post buffer)
++++++++++++++++++++++++++++++++++++
(input) ... this is identical to no delay pattern without reschedule
┌────────────────┐┌───┐┌───────────────┐ ░ ┌───┐
q_0: ┤ Delay(100[dt]) ├┤ X ├┤ Delay(10[dt]) ├─░─┤ X ├
├────────────────┤└───┘└───────────────┘ ░ └───┘
q_1: ┤ Delay(272[dt]) ├───────────────────────░──────
└────────────────┘ ░
(aligned)
┌────────────────┐┌───┐┌───────────────┐ ░ ┌──────────────┐┌───┐
q_0: ┤ Delay(112[dt]) ├┤ X ├┤ Delay(10[dt]) ├─░─┤ Delay(6[dt]) ├┤ X ├
├────────────────┤└───┘└───────────────┘ ░ └──────────────┘└───┘
q_1: ┤ Delay(282[dt]) ├───────────────────────░──────────────────────
└────────────────┘ ░
"""
pm = PassManager([
ASAPScheduleAnalysis(durations=self.instruction_durations),
ConstrainedReschedule(pulse_alignment=16),
PadDelay(fill_very_end=False),
])
pm_only_schedule = PassManager([
ASAPScheduleAnalysis(durations=self.instruction_durations),
PadDelay(fill_very_end=False),
])
circuit_no_delay = QuantumCircuit(2)
circuit_no_delay.delay(100, 0, unit="dt")
circuit_no_delay.x(0) # q0 ends here at t = 260, t = 260 - 272 is free
circuit_no_delay.delay(160 + 112, 1, unit="dt")
circuit_no_delay.barrier() # q0 and q1 is aligned here at t = 272 dt
circuit_no_delay.x(0)
ref_no_delay = QuantumCircuit(2)
ref_no_delay.delay(112, 0, unit="dt")
ref_no_delay.x(0)
ref_no_delay.delay(160 + 100 + 12, 1,
unit="dt") # this t0 doesn't change
ref_no_delay.barrier()
ref_no_delay.x(0) # no buffer
self.assertEqual(pm.run(circuit_no_delay), ref_no_delay)
circuit_with_delay = QuantumCircuit(2)
circuit_with_delay.delay(100, 0, unit="dt")
circuit_with_delay.x(0) # q0 ends here at t = 260
circuit_with_delay.delay(
10, 0, unit="dt") # intentional post buffer of 10 dt to next X(0)
circuit_with_delay.delay(
160 + 112, 1, unit="dt") # q0 and q1 is aligned here at t = 272 dt
circuit_with_delay.barrier()
circuit_with_delay.x(0)
ref_with_delay = QuantumCircuit(2)
ref_with_delay.delay(112, 0, unit="dt")
ref_with_delay.x(0)
ref_with_delay.delay(10, 0, unit="dt") # this delay survive
ref_with_delay.delay(160 + 100 + 12 + 10, 1, unit="dt")
ref_with_delay.barrier()
ref_with_delay.delay(6, 0, unit="dt") # extra delay for next X0
ref_with_delay.x(0) # at least 10dt buffer is preserved
self.assertEqual(pm.run(circuit_with_delay), ref_with_delay)
# check if circuit is identical without reschedule
self.assertEqual(
pm_only_schedule.run(circuit_no_delay),
pm_only_schedule.run(circuit_with_delay),
)
def level_1_pass_manager(
pass_manager_config: PassManagerConfig) -> PassManager:
"""Level 1 pass manager: light optimization by simple adjacent gate collapsing.
This pass manager applies the user-given initial layout. If none is given,
and a trivial layout (i-th virtual -> i-th physical) makes the circuit fit
the coupling map, that is used.
Otherwise, the circuit is mapped to the most densely connected coupling subgraph,
and swaps are inserted to map. Any unused physical qubit is allocated as ancilla space.
The pass manager then unrolls the circuit to the desired basis, and transforms the
circuit to match the coupling map. Finally, optimizations in the form of adjacent
gate collapse and redundant reset removal are performed.
Note:
In simulators where ``coupling_map=None``, only the unrolling and
optimization stages are done.
Args:
pass_manager_config: configuration of the pass manager.
Returns:
a level 1 pass manager.
Raises:
TranspilerError: if the passmanager config is invalid.
"""
basis_gates = pass_manager_config.basis_gates
inst_map = pass_manager_config.inst_map
coupling_map = pass_manager_config.coupling_map
initial_layout = pass_manager_config.initial_layout
layout_method = pass_manager_config.layout_method or "dense"
routing_method = pass_manager_config.routing_method or "stochastic"
translation_method = pass_manager_config.translation_method or "translator"
scheduling_method = pass_manager_config.scheduling_method
instruction_durations = pass_manager_config.instruction_durations
seed_transpiler = pass_manager_config.seed_transpiler
backend_properties = pass_manager_config.backend_properties
approximation_degree = pass_manager_config.approximation_degree
unitary_synthesis_method = pass_manager_config.unitary_synthesis_method
unitary_synthesis_plugin_config = pass_manager_config.unitary_synthesis_plugin_config
timing_constraints = pass_manager_config.timing_constraints or TimingConstraints(
)
target = pass_manager_config.target
# 1. Use trivial layout if no layout given if that isn't perfect use vf2 layout
_given_layout = SetLayout(initial_layout)
def _choose_layout_condition(property_set):
return not property_set["layout"]
def _trivial_not_perfect(property_set):
# Verify that a trivial layout is perfect. If trivial_layout_score > 0
# the layout is not perfect. The layout is unconditionally set by trivial
# layout so we need to clear it before contuing.
if (property_set["trivial_layout_score"] is not None
and property_set["trivial_layout_score"] != 0):
return True
return False
def _vf2_match_not_found(property_set):
# If a layout hasn't been set by the time we run vf2 layout we need to
# run layout
if property_set["layout"] is None:
return True
# if VF2 layout stopped for any reason other than solution found we need
# to run layout since VF2 didn't converge.
if (property_set["VF2Layout_stop_reason"] is not None
and property_set["VF2Layout_stop_reason"]
is not VF2LayoutStopReason.SOLUTION_FOUND):
return True
return False
_choose_layout_0 = ([] if pass_manager_config.layout_method else [
TrivialLayout(coupling_map),
Layout2qDistance(coupling_map, property_name="trivial_layout_score"),
])
_choose_layout_1 = ([] if pass_manager_config.layout_method else VF2Layout(
coupling_map,
seed=seed_transpiler,
call_limit=int(5e4), # Set call limit to ~100ms with retworkx 0.10.2
time_limit=0.1,
properties=backend_properties,
target=target,
))
# 2. Decompose so only 1-qubit and 2-qubit gates remain
_unroll3q = [
# Use unitary synthesis for basis aware decomposition of UnitaryGates
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
method=unitary_synthesis_method,
min_qubits=3,
plugin_config=unitary_synthesis_plugin_config,
target=target,
),
Unroll3qOrMore(),
]
# 3. Use a better layout on densely connected qubits, if circuit needs swaps
if layout_method == "trivial":
_improve_layout = TrivialLayout(coupling_map)
elif layout_method == "dense":
_improve_layout = DenseLayout(coupling_map,
backend_properties,
target=target)
elif layout_method == "noise_adaptive":
_improve_layout = NoiseAdaptiveLayout(backend_properties)
elif layout_method == "sabre":
_improve_layout = SabreLayout(coupling_map,
max_iterations=2,
seed=seed_transpiler)
else:
raise TranspilerError("Invalid layout method %s." % layout_method)
# 4. Extend dag/layout with ancillas using the full coupling map
_embed = [
FullAncillaAllocation(coupling_map),
EnlargeWithAncilla(),
ApplyLayout()
]
# 5. Swap to fit the coupling map
_swap_check = CheckMap(coupling_map)
def _swap_condition(property_set):
return not property_set["is_swap_mapped"]
_swap = [BarrierBeforeFinalMeasurements()]
if routing_method == "basic":
_swap += [BasicSwap(coupling_map)]
elif routing_method == "stochastic":
_swap += [
StochasticSwap(coupling_map, trials=20, seed=seed_transpiler)
]
elif routing_method == "lookahead":
_swap += [LookaheadSwap(coupling_map, search_depth=4, search_width=4)]
elif routing_method == "sabre":
_swap += [
SabreSwap(coupling_map,
heuristic="lookahead",
seed=seed_transpiler)
]
elif routing_method == "none":
_swap += [
Error(
msg=
("No routing method selected, but circuit is not routed to device. "
"CheckMap Error: {check_map_msg}"),
action="raise",
)
]
else:
raise TranspilerError("Invalid routing method %s." % routing_method)
# 6. Unroll to the basis
if translation_method == "unroller":
_unroll = [Unroller(basis_gates)]
elif translation_method == "translator":
from qiskit.circuit.equivalence_library import SessionEquivalenceLibrary as sel
_unroll = [
# Use unitary synthesis for basis aware decomposition of UnitaryGates before
# custom unrolling
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
method=unitary_synthesis_method,
backend_props=backend_properties,
plugin_config=unitary_synthesis_plugin_config,
target=target,
),
UnrollCustomDefinitions(sel, basis_gates),
BasisTranslator(sel, basis_gates, target),
]
elif translation_method == "synthesis":
_unroll = [
# Use unitary synthesis for basis aware decomposition of UnitaryGates before
# collection
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
method=unitary_synthesis_method,
backend_props=backend_properties,
min_qubits=3,
target=target,
),
Unroll3qOrMore(),
Collect2qBlocks(),
ConsolidateBlocks(basis_gates=basis_gates, target=target),
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
method=unitary_synthesis_method,
backend_props=backend_properties,
plugin_config=unitary_synthesis_plugin_config,
target=target,
),
]
else:
raise TranspilerError("Invalid translation method %s." %
translation_method)
# 7. Fix any bad CX directions
_direction_check = [CheckGateDirection(coupling_map, target)]
def _direction_condition(property_set):
return not property_set["is_direction_mapped"]
_direction = [GateDirection(coupling_map, target)]
# 8. Remove zero-state reset
_reset = RemoveResetInZeroState()
# 9. Merge 1q rotations and cancel CNOT gates iteratively until no more change in depth
# or size of circuit
_depth_check = [Depth(), FixedPoint("depth")]
_size_check = [Size(), FixedPoint("size")]
def _opt_control(property_set):
return (not property_set["depth_fixed_point"]) or (
not property_set["size_fixed_point"])
_opt = [Optimize1qGatesDecomposition(basis_gates), CXCancellation()]
# Build pass manager
pm1 = PassManager()
if coupling_map or initial_layout:
pm1.append(_given_layout)
pm1.append(_unroll3q)
pm1.append(_choose_layout_0, condition=_choose_layout_condition)
pm1.append(_choose_layout_1, condition=_trivial_not_perfect)
pm1.append(_improve_layout, condition=_vf2_match_not_found)
pm1.append(_embed)
pm1.append(_swap_check)
pm1.append(_swap, condition=_swap_condition)
pm1.append(_unroll)
if (coupling_map and not coupling_map.is_symmetric) or (
target is not None
and target.get_non_global_operation_names(strict_direction=True)):
pm1.append(_direction_check)
pm1.append(_direction, condition=_direction_condition)
pm1.append(_reset)
pm1.append(_depth_check + _size_check)
pm1.append(_opt + _unroll + _depth_check + _size_check,
do_while=_opt_control)
if inst_map and inst_map.has_custom_gate():
pm1.append(PulseGates(inst_map=inst_map))
# 10. Unify all durations (either SI, or convert to dt if known)
# Schedule the circuit only when scheduling_method is supplied
# Apply alignment analysis regardless of scheduling for delay validation.
if scheduling_method:
# Do scheduling after unit conversion.
scheduler = {
"alap": ALAPScheduleAnalysis,
"as_late_as_possible": ALAPScheduleAnalysis,
"asap": ASAPScheduleAnalysis,
"as_soon_as_possible": ASAPScheduleAnalysis,
}
pm1.append(TimeUnitConversion(instruction_durations))
try:
pm1.append(scheduler[scheduling_method](instruction_durations))
except KeyError as ex:
raise TranspilerError("Invalid scheduling method %s." %
scheduling_method) from ex
elif instruction_durations:
# No scheduling. But do unit conversion for delays.
def _contains_delay(property_set):
return property_set["contains_delay"]
pm1.append(ContainsInstruction("delay"))
pm1.append(TimeUnitConversion(instruction_durations),
condition=_contains_delay)
if (timing_constraints.granularity != 1
or timing_constraints.min_length != 1
or timing_constraints.acquire_alignment != 1
or timing_constraints.pulse_alignment != 1):
# Run alignment analysis regardless of scheduling.
def _require_alignment(property_set):
return property_set["reschedule_required"]
pm1.append(
InstructionDurationCheck(
acquire_alignment=timing_constraints.acquire_alignment,
pulse_alignment=timing_constraints.pulse_alignment,
))
pm1.append(
ConstrainedReschedule(
acquire_alignment=timing_constraints.acquire_alignment,
pulse_alignment=timing_constraints.pulse_alignment,
),
condition=_require_alignment,
)
pm1.append(
ValidatePulseGates(
granularity=timing_constraints.granularity,
min_length=timing_constraints.min_length,
))
if scheduling_method:
# Call padding pass if circuit is scheduled
pm1.append(PadDelay())
return pm1
def level_2_pass_manager(
pass_manager_config: PassManagerConfig) -> PassManager:
"""Level 2 pass manager: medium optimization by initial layout selection and
gate cancellation using commutativity rules.
This pass manager applies the user-given initial layout. If none is given, a search
for a perfect layout (i.e. one that satisfies all 2-qubit interactions) is conducted.
If no such layout is found, qubits are laid out on the most densely connected subset
which also exhibits the best gate fidelities.
The pass manager then transforms the circuit to match the coupling constraints.
It is then unrolled to the basis, and any flipped cx directions are fixed.
Finally, optimizations in the form of commutative gate cancellation and redundant
reset removal are performed.
Note:
In simulators where ``coupling_map=None``, only the unrolling and
optimization stages are done.
Args:
pass_manager_config: configuration of the pass manager.
Returns:
a level 2 pass manager.
Raises:
TranspilerError: if the passmanager config is invalid.
"""
basis_gates = pass_manager_config.basis_gates
inst_map = pass_manager_config.inst_map
coupling_map = pass_manager_config.coupling_map
initial_layout = pass_manager_config.initial_layout
layout_method = pass_manager_config.layout_method or "dense"
routing_method = pass_manager_config.routing_method or "stochastic"
translation_method = pass_manager_config.translation_method or "translator"
scheduling_method = pass_manager_config.scheduling_method
instruction_durations = pass_manager_config.instruction_durations
seed_transpiler = pass_manager_config.seed_transpiler
backend_properties = pass_manager_config.backend_properties
approximation_degree = pass_manager_config.approximation_degree
unitary_synthesis_method = pass_manager_config.unitary_synthesis_method
timing_constraints = pass_manager_config.timing_constraints or TimingConstraints(
)
unitary_synthesis_plugin_config = pass_manager_config.unitary_synthesis_plugin_config
target = pass_manager_config.target
# 1. Unroll to 1q or 2q gates
_unroll3q = [
# Use unitary synthesis for basis aware decomposition of UnitaryGates
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
method=unitary_synthesis_method,
min_qubits=3,
plugin_config=unitary_synthesis_plugin_config,
),
Unroll3qOrMore(),
]
# 2. Search for a perfect layout, or choose a dense layout, if no layout given
_given_layout = SetLayout(initial_layout)
def _choose_layout_condition(property_set):
# layout hasn't been set yet
return not property_set["layout"]
def _vf2_match_not_found(property_set):
# If a layout hasn't been set by the time we run vf2 layout we need to
# run layout
if property_set["layout"] is None:
return True
# if VF2 layout stopped for any reason other than solution found we need
# to run layout since VF2 didn't converge.
if (property_set["VF2Layout_stop_reason"] is not None
and property_set["VF2Layout_stop_reason"]
is not VF2LayoutStopReason.SOLUTION_FOUND):
return True
return False
# 2a. Try using VF2 layout to find a perfect layout
_choose_layout_0 = ([] if pass_manager_config.layout_method else VF2Layout(
coupling_map,
seed=seed_transpiler,
call_limit=int(5e6), # Set call limit to ~10 sec with retworkx 0.10.2
time_limit=10.0,
properties=backend_properties,
))
# 2b. if VF2 layout doesn't converge on a solution use layout_method (dense) to get a layout
if layout_method == "trivial":
_choose_layout_1 = TrivialLayout(coupling_map)
elif layout_method == "dense":
_choose_layout_1 = DenseLayout(coupling_map, backend_properties)
elif layout_method == "noise_adaptive":
_choose_layout_1 = NoiseAdaptiveLayout(backend_properties)
elif layout_method == "sabre":
_choose_layout_1 = SabreLayout(coupling_map,
max_iterations=2,
seed=seed_transpiler)
else:
raise TranspilerError("Invalid layout method %s." % layout_method)
# 3. Extend dag/layout with ancillas using the full coupling map
_embed = [
FullAncillaAllocation(coupling_map),
EnlargeWithAncilla(),
ApplyLayout()
]
# 4. Swap to fit the coupling map
_swap_check = CheckMap(coupling_map)
def _swap_condition(property_set):
return not property_set["is_swap_mapped"]
_swap = [BarrierBeforeFinalMeasurements()]
if routing_method == "basic":
_swap += [BasicSwap(coupling_map)]
elif routing_method == "stochastic":
_swap += [
StochasticSwap(coupling_map, trials=20, seed=seed_transpiler)
]
elif routing_method == "lookahead":
_swap += [LookaheadSwap(coupling_map, search_depth=5, search_width=5)]
elif routing_method == "sabre":
_swap += [
SabreSwap(coupling_map, heuristic="decay", seed=seed_transpiler)
]
elif routing_method == "none":
_swap += [
Error(
msg=
("No routing method selected, but circuit is not routed to device. "
"CheckMap Error: {check_map_msg}"),
action="raise",
)
]
else:
raise TranspilerError("Invalid routing method %s." % routing_method)
# 5. Unroll to the basis
if translation_method == "unroller":
_unroll = [Unroller(basis_gates)]
elif translation_method == "translator":
from qiskit.circuit.equivalence_library import SessionEquivalenceLibrary as sel
_unroll = [
# Use unitary synthesis for basis aware decomposition of UnitaryGates before
# custom unrolling
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
backend_props=backend_properties,
method=unitary_synthesis_method,
plugin_config=unitary_synthesis_plugin_config,
),
UnrollCustomDefinitions(sel, basis_gates),
BasisTranslator(sel, basis_gates, target),
]
elif translation_method == "synthesis":
_unroll = [
# Use unitary synthesis for basis aware decomposition of UnitaryGates before
# collection
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
backend_props=backend_properties,
method=unitary_synthesis_method,
plugin_config=unitary_synthesis_plugin_config,
min_qubits=3,
),
Unroll3qOrMore(),
Collect2qBlocks(),
ConsolidateBlocks(basis_gates=basis_gates, target=target),
UnitarySynthesis(
basis_gates,
approximation_degree=approximation_degree,
coupling_map=coupling_map,
backend_props=backend_properties,
method=unitary_synthesis_method,
plugin_config=unitary_synthesis_plugin_config,
),
]
else:
raise TranspilerError("Invalid translation method %s." %
translation_method)
# 6. Fix any bad CX directions
_direction_check = [CheckGateDirection(coupling_map, target)]
def _direction_condition(property_set):
return not property_set["is_direction_mapped"]
_direction = [GateDirection(coupling_map, target)]
# 7. Remove zero-state reset
_reset = RemoveResetInZeroState()
# 8. 1q rotation merge and commutative cancellation iteratively until no more change in depth
_depth_check = [Depth(), FixedPoint("depth")]
def _opt_control(property_set):
return not property_set["depth_fixed_point"]
_opt = [
Optimize1qGatesDecomposition(basis_gates),
CommutativeCancellation(basis_gates=basis_gates),
]
# 9. Unify all durations (either SI, or convert to dt if known)
# Schedule the circuit only when scheduling_method is supplied
_time_unit_setup = [ContainsInstruction("delay")]
_time_unit_conversion = [TimeUnitConversion(instruction_durations)]
def _contains_delay(property_set):
return property_set["contains_delay"]
_scheduling = []
if scheduling_method:
_scheduling += _time_unit_conversion
if scheduling_method in {"alap", "as_late_as_possible"}:
_scheduling += [ALAPSchedule(instruction_durations), PadDelay()]
elif scheduling_method in {"asap", "as_soon_as_possible"}:
_scheduling += [ASAPSchedule(instruction_durations), PadDelay()]
else:
raise TranspilerError("Invalid scheduling method %s." %
scheduling_method)
# 10. Call measure alignment. Should come after scheduling.
if (timing_constraints.granularity != 1
or timing_constraints.min_length != 1
or timing_constraints.acquire_alignment != 1):
_alignments = [
ValidatePulseGates(granularity=timing_constraints.granularity,
min_length=timing_constraints.min_length),
AlignMeasures(alignment=timing_constraints.acquire_alignment),
]
else:
_alignments = []
# Build pass manager
pm2 = PassManager()
if coupling_map or initial_layout:
pm2.append(_given_layout)
pm2.append(_unroll3q)
pm2.append(_choose_layout_0, condition=_choose_layout_condition)
pm2.append(_choose_layout_1, condition=_vf2_match_not_found)
pm2.append(_embed)
pm2.append(_swap_check)
pm2.append(_swap, condition=_swap_condition)
pm2.append(_unroll)
if (coupling_map and not coupling_map.is_symmetric) or (
target is not None
and target.get_non_global_operation_names(strict_direction=True)):
pm2.append(_direction_check)
pm2.append(_direction, condition=_direction_condition)
pm2.append(_reset)
pm2.append(_depth_check + _opt + _unroll, do_while=_opt_control)
if inst_map and inst_map.has_custom_gate():
pm2.append(PulseGates(inst_map=inst_map))
if scheduling_method:
pm2.append(_scheduling)
elif instruction_durations:
pm2.append(_time_unit_setup)
pm2.append(_time_unit_conversion, condition=_contains_delay)
pm2.append(_alignments)
return pm2
