def __init__(self, mode="pack"):
"""
Simple example that instances two stub DMA modules and is paramtrizable
over distributed versus packed register file
"""
if mode not in ["pack", "distribute"]:
raise ValueError(f"Unexpected mode {mode}")
fields = ["csr", "src_addr", "dst_addr", "txfr_len"]
data_width = 32
addr_width = math.ceil(math.log2(len(fields) * 2))
self.name = "Top_" + mode
self.io = io = m.IO(apb=APBSlave(addr_width, data_width, 0))
dmas = [DMA(name=f"dma{i}") for i in range(2)]
regs = tuple(Register(name + str(i)) for i in range(2) for name in
fields)
reg_file = RegisterFileGenerator(regs, data_width=32)(name="reg_file")
for i in range(2):
for name in fields:
m.wire(getattr(reg_file, name + str(i) + "_q"),
getattr(dmas[i], name))
m.wire(io.apb, reg_file.apb)
for i in range(2):
for name in fields:
m.wire(getattr(reg_file, name + str(i) + "_q"),
getattr(reg_file, name + str(i) + "_d"))
def definition(io):
dmas = [DMA(name=f"dma{i}") for i in range(2)]
if mode == "pack":
regs = [
Register(name + str(i)) for i in range(2)
for name in fields
]
reg_file = DefineRegFile(regs, data_width=32)(name="reg_file")
for i in range(2):
for name in fields:
m.wire(getattr(reg_file, name + str(i) + "_q"),
getattr(dmas[i], name))
m.wire(io.apb, reg_file.apb)
for i in range(2):
for name in fields:
m.wire(getattr(reg_file, name + str(i) + "_q"),
getattr(reg_file, name + str(i) + "_d"))
else:
apb_outputs = {}
for key, type_ in APBBase(addr_width, data_width).items():
if type_.isinput():
apb_outputs[key] = []
for i in range(2):
regs = [Register(name) for name in fields]
reg_file = DefineRegFile(
regs, data_width=32,
apb_slave_id=i)(name=f"reg_file{i}")
for name in fields:
m.wire(getattr(reg_file, name + "_q"),
getattr(dmas[i], name))
for key, type_ in APBBase(addr_width, data_width).items():
if type_.isoutput():
m.wire(getattr(io.apb, key),
getattr(reg_file.apb, key))
else:
apb_outputs[key].append(getattr(reg_file.apb, key))
m.wire(getattr(io.apb, f"PSEL{i}"),
getattr(reg_file.apb, f"PSEL{i}"))
for name in fields:
m.wire(getattr(reg_file, name + "_q"),
getattr(reg_file, name + "_d"))
for key, values in apb_outputs.items():
m.wire(getattr(io.apb, key),
mantle.mux(values, io.apb.PSEL1))
def test_simple_write():
data_width = 32
regs = [Register(f"reg_{i}", init=i, has_ce=True) for i in range(4)]
RegFile = DefineRegFile(regs, data_width)
tester = fault.Tester(RegFile, clock=RegFile.apb.PCLK)
tester.circuit.apb.PRESETn = 1
addr_width = m.bitutils.clog2(len(regs))
data_width = 32
addr = 1
data = 45
bus = APBBus(addr_width, data_width)
io, request = make_request(addr, data, addr_width, data_width)
write(bus, io, request, tester, addr, data)
getattr(tester.circuit, f"reg_{addr}_q").expect(data)
tester.compile_and_run(target="verilator", magma_output="coreir-verilog",
magma_opts={"verilator_debug": True},
flags=["--trace"])
def test_simple_write_read():
data_width = 32
regs = tuple(Register(f"reg_{i}", init=i, has_ce=True) for i in range(4))
RegFile = RegisterFileGenerator(regs, data_width)
tester = fault.Tester(RegFile, clock=RegFile.apb.PCLK)
tester.circuit.apb.PRESETn = 1
addr_width = m.bitutils.clog2(len(regs))
data_width = 32
bus = APBBus(addr_width, data_width)
addr = 1
data = 45
io, request = make_request(addr, data, addr_width, data_width)
write(bus, io, request, tester, addr, data)
read(bus, io, request, tester, addr, data)
tester.compile_and_run(target="verilator",
magma_output="coreir-verilog",
magma_opts={"verilator_debug": True},
flags=["--trace"])
def test_write_then_reads():
data_width = 32
regs = tuple(Register(f"reg_{i}", init=i, has_ce=True) for i in range(4))
RegFile = RegisterFileGenerator(regs, data_width)
tester = fault.Tester(RegFile, clock=RegFile.apb.PCLK)
tester.circuit.apb.PRESETn = 1
addr_width = m.bitutils.clog2(len(regs))
data_width = 32
bus = APBBus(addr_width, data_width)
values = [0xDE, 0xAD, 0xBE, 0xEF]
for addr, data in enumerate(values):
io, request = make_request(addr, data, addr_width, data_width)
write(bus, io, request, tester, addr, data)
getattr(tester.circuit, f"reg_{addr}_q").expect(data)
for addr, data in enumerate(values):
io, request = make_request(addr, data, addr_width, data_width)
read(bus, io, request, tester, addr, data)
tester.compile_and_run(target="verilator",
magma_output="coreir-verilog",
magma_opts={"verilator_debug": True},
flags=["--trace"])
def __init__(self, mode="pack"):
"""
Simple example that instances two stub DMA modules and is paramtrizable
over distributed versus packed register file
"""
if mode not in ["pack", "distribute"]:
raise ValueError(f"Unexpected mode {mode}")
fields = ["csr", "src_addr", "dst_addr", "txfr_len"]
data_width = 32
if mode == "pack":
addr_width = math.ceil(math.log2(len(fields) * 2))
else:
addr_width = math.ceil(math.log2(len(fields)))
self.name = "Top_" + mode
if mode == "pack":
self.io = io = m.IO(apb=APBSlave(addr_width, data_width, 0))
else:
self.io = io = m.IO(apb=APBSlave(addr_width, data_width, [0, 1]))
dmas = [DMA(name=f"dma{i}") for i in range(2)]
if mode == "pack":
regs = tuple(
Register(name + str(i)) for i in range(2) for name in fields)
reg_file = RegisterFileGenerator(regs,
data_width=32)(name="reg_file")
for i in range(2):
for name in fields:
m.wire(getattr(reg_file, name + str(i) + "_q"),
getattr(dmas[i], name))
m.wire(io.apb, reg_file.apb)
for i in range(2):
for name in fields:
m.wire(getattr(reg_file, name + str(i) + "_q"),
getattr(reg_file, name + str(i) + "_d"))
else:
apb_outputs = {}
for key, type_ in APBBase(addr_width, data_width).items():
if type_.is_input():
apb_outputs[key] = []
for i in range(2):
regs = tuple(Register(name) for name in fields)
reg_file = RegisterFileGenerator(
regs, data_width=32, apb_slave_id=i)(name=f"reg_file{i}")
for name in fields:
m.wire(getattr(reg_file, name + "_q"),
getattr(dmas[i], name))
for key, type_ in APBBase(addr_width, data_width).items():
if type_.is_output():
m.wire(getattr(io.apb, key),
getattr(reg_file.apb, key))
else:
apb_outputs[key].append(getattr(reg_file.apb, key))
m.wire(getattr(io.apb, f"PSEL{i}"),
getattr(reg_file.apb, f"PSEL{i}"))
for name in fields:
m.wire(getattr(reg_file, name + "_q"),
getattr(reg_file, name + "_d"))
for key, values in apb_outputs.items():
m.wire(getattr(io.apb, key), mantle.mux(values, io.apb.PSEL1))