def build(args): # @todo: use parallella board, use an ISE support board for now ... brd = get_board('parallella') # @todo: temporary for existing board # brd.add_reset('reset', active=1, async=True, pins=('N20',)) brd.add_port_name('serial_tx_p', 'gpio_p', slice(4, 8)) brd.add_port_name('serial_tx_n', 'gpio_n', slice(4, 8)) brd.add_port_name('serial_rx_p', 'gpio_p', slice(8, 12)) brd.add_port_name('serial_rx_n', 'gpio_n', slice(8, 12)) flow = brd.get_flow(parallella_serdes) flow.run() info = flow.get_utilization() pprint(info)
def build(args): # @todo: use parallella board, use an ISE support board for now ... brd = get_board('parallella') # @todo: temporary for existing board # brd.add_reset('reset', active=1, isasync=True, pins=('N20',)) brd.add_port_name('serial_tx_p', 'gpio_p', slice(4, 8)) brd.add_port_name('serial_tx_n', 'gpio_n', slice(4, 8)) brd.add_port_name('serial_rx_p', 'gpio_p', slice(8, 12)) brd.add_port_name('serial_rx_n', 'gpio_n', slice(8, 12)) flow = brd.get_flow(parallella_serdes) flow.run() info = flow.get_utilization() pprint(info)
def build(): brd = get_board('zybo') flow = brd.get_flow(zybo_vga) flow.run()