def icestick_blinky_host(clock, led, pmod, uart_tx, uart_rx, uart_dtr, uart_rts):
"""
This example is similar to the other examples in this directory but
the LEDs are controlled externally via command packets sent from a
host via the UART on the icestick.
Ports:
clock:
led:
pmod:
uart_tx:
uart_rx:
"""
glbl = Global(clock, None)
ledreg = Signal(intbv(0)[8:])
# create the timer tick instance
tick_inst = glbl_timer_ticks(glbl, include_seconds=True)
# create the interfaces to the UART
fbustx = FIFOBus(width=8, size=4)
fbusrx = FIFOBus(width=8, size=4)
# create the memmap (CSR) interface
memmap = Barebone(glbl, data_width=32, address_width=32)
# create the UART instance.
uart_inst = uartlite(glbl, fbustx, fbusrx, uart_rx, uart_tx)
# create the packet command instance
cmd_inst = memmap_command_bridge(glbl, fbusrx, fbustx, memmap)
@always_seq(clock.posedge, reset=None)
def beh_led_control():
memmap.done.next = not (memmap.write or memmap.read)
if memmap.write and memmap.mem_addr == 0x20:
ledreg.next = memmap.write_data
@always_comb
def beh_led_read():
if memmap.read and memmap.mem_addr == 0x20:
memmap.read_data.next = ledreg
else:
memmap.read_data.next = 0
# blink one of the LEDs
tone = Signal(intbv(0)[8:])
@always_seq(clock.posedge, reset=None)
def beh_assign():
if glbl.tick_sec:
tone.next = (~tone) & 0x1
led.next = ledreg | tone[5:]
pmod.next = 0
# @todo: PMOD OLED memmap control
return (tick_inst, uart_inst, cmd_inst, beh_led_control, beh_led_read, beh_assign)
def catboard_blinky_host(clock, led, uart_tx, uart_rx):
"""
The LEDs are controlled from the RPi over the UART
to the FPGA.
"""
glbl = Global(clock, None)
ledreg = Signal(intbv(0)[8:])
# create the timer tick instance
tick_inst = glbl_timer_ticks(glbl, include_seconds=True)
# create the interfaces to the UART
fbustx = FIFOBus(width=8, size=4)
fbusrx = FIFOBus(width=8, size=4)
# create the memmap (CSR) interface
memmap = Barebone(glbl, data_width=32, address_width=32)
# create the UART instance.
uart_inst = uartlite(glbl,
fbustx,
fbusrx,
serial_in=uart_rx,
serial_out=uart_tx)
# create the packet command instance
cmd_inst = memmap_command_bridge(glbl, fbusrx, fbustx, memmap)
@always_seq(clock.posedge, reset=None)
def beh_led_control():
memmap.done.next = not (memmap.write or memmap.read)
if memmap.write and memmap.mem_addr == 0x20:
ledreg.next = memmap.write_data
@always_comb
def beh_led_read():
if memmap.read and memmap.mem_addr == 0x20:
memmap.read_data.next = ledreg
else:
memmap.read_data.next = 0
# blink one of the LEDs
tone = Signal(intbv(0)[8:])
@always_seq(clock.posedge, reset=None)
def beh_assign():
if glbl.tick_sec:
tone.next = (~tone) & 0x1
led.next = ledreg | tone[5:]
return (tick_inst, uart_inst, cmd_inst, beh_led_control, beh_led_read,
beh_assign)
def _bench_command_bridge():
tbclk = clock.gen()
tbdut = memmap_command_bridge(glbl, fbtx, fbrx, memmap)
tbfii = fifo_fast(clock, reset, fbtx)
tbfio = fifo_fast(clock, reset, fbrx)
# @todo: add other bus types
tbmem = memmap_peripheral_bb(clock, reset, memmap)
# save the data read ...
read_value = []
@instance
def tbstim():
yield reset.pulse(32)
try:
# test a single address
pkt = CommandPacket(True, 0x0000)
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [0])
pkt = CommandPacket(False, 0x0000, [0x5555AAAA])
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [0x5555AAAA])
# test a bunch of random addresses
for ii in range(nloops):
randaddr = randint(0, (2**20)-1)
randdata = randint(0, (2**32)-1)
pkt = CommandPacket(False, randaddr, [randdata])
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [randdata])
except Exception as err:
print("Error: {}".format(str(err)))
traceback.print_exc()
yield delay(2000)
raise StopSimulation
return tbclk, tbdut, tbfii, tbfio, tbmem, tbstim
def _bench_command_bridge():
tbclk = clock.gen()
tbdut = memmap_command_bridge(glbl, fbtx, fbrx, memmap)
tbfii = fifo_fast(clock, reset, fbtx)
tbfio = fifo_fast(clock, reset, fbrx)
# @todo: add other bus types
tbmem = memmap_peripheral_bb(clock, reset, memmap)
# save the data read ...
read_value = []
@instance
def tbstim():
yield reset.pulse(32)
try:
# test a single address
pkt = CommandPacket(True, 0x0000)
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [0])
pkt = CommandPacket(False, 0x0000, [0x5555AAAA])
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [0x5555AAAA])
# test a bunch of random addresses
for ii in range(nloops):
randaddr = randint(0, (2**20) - 1)
randdata = randint(0, (2**32) - 1)
pkt = CommandPacket(False, randaddr, [randdata])
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [randdata])
except Exception as err:
print("Error: {}".format(str(err)))
traceback.print_exc()
yield delay(2000)
raise StopSimulation
return tbclk, tbdut, tbfii, tbfio, tbmem, tbstim
def atlys_blinky_host(clock, reset, led, sw, pmod, uart_tx, uart_rx):
"""
This example is similar to the other examples in this directory but
the LEDs are controlled externally via command packets sent from a
host via the UART on the icestick.
"""
glbl = Global(clock, reset)
ledreg = Signal(intbv(0)[8:])
# create the timer tick instance
tick_inst = glbl_timer_ticks(glbl, include_seconds=True)
# create the interfaces to the UART
fbustx = FIFOBus(width=8, size=32)
fbusrx = FIFOBus(width=8, size=32)
# create the memmap (CSR) interface
memmap = Barebone(glbl, data_width=32, address_width=32)
# create the UART instance.
cmd_tx = Signal(bool(0))
uart_inst = uartlite(glbl, fbustx, fbusrx, uart_rx, cmd_tx)
# create the packet command instance
cmd_inst = memmap_command_bridge(glbl, fbusrx, fbustx, memmap)
@always_seq(clock.posedge, reset=reset)
def beh_led_control():
memmap.done.next = not (memmap.write or memmap.read)
if memmap.write: # and memmap.mem_addr == 0x20:
ledreg.next = memmap.write_data
@always_comb
def beh_led_read():
if memmap.read and memmap.mem_addr == 0x20:
memmap.read_data.next = ledreg
else:
memmap.read_data.next = 0
# blink one of the LEDs
status = [Signal(bool(0)) for _ in range(8)]
statusbv = ConcatSignal(*reversed(status))
@always_seq(clock.posedge, reset=reset)
def beh_assign():
# status / debug signals
if glbl.tick_sec:
status[0].next = not status[0]
status[1].next = memmap.mem_addr == 0x20
status[2].next = uart_rx
status[3].next = uart_tx
led.next = ledreg | statusbv | sw
pmod.next = 0
if sw[0]:
uart_tx.next = uart_rx
else:
uart_tx.next = cmd_tx
# @todo: PMOD OLED memmap control
return (tick_inst, uart_inst, cmd_inst, beh_led_control, beh_led_read,
beh_assign)
def atlys_blinky_host(clock, reset, led, sw, pmod, uart_tx, uart_rx):
"""
This example is similar to the other examples in this directory but
the LEDs are controlled externally via command packets sent from a
host via the UART on the icestick.
"""
glbl = Global(clock, reset)
ledreg = Signal(intbv(0)[8:])
# create the timer tick instance
tick_inst = glbl_timer_ticks(glbl, include_seconds=True)
# create the interfaces to the UART
fbustx = FIFOBus(width=8, size=32)
fbusrx = FIFOBus(width=8, size=32)
# create the memmap (CSR) interface
memmap = Barebone(glbl, data_width=32, address_width=32)
# create the UART instance.
cmd_tx = Signal(bool(0))
uart_inst = uartlite(glbl, fbustx, fbusrx, uart_rx, cmd_tx)
# create the packet command instance
cmd_inst = memmap_command_bridge(glbl, fbusrx, fbustx, memmap)
@always_seq(clock.posedge, reset=reset)
def beh_led_control():
memmap.done.next = not (memmap.write or memmap.read)
if memmap.write: # and memmap.mem_addr == 0x20:
ledreg.next = memmap.write_data
@always_comb
def beh_led_read():
if memmap.read and memmap.mem_addr == 0x20:
memmap.read_data.next = ledreg
else:
memmap.read_data.next = 0
# blink one of the LEDs
status = [Signal(bool(0)) for _ in range(8)]
statusbv = ConcatSignal(*reversed(status))
@always_seq(clock.posedge, reset=reset)
def beh_assign():
# status / debug signals
if glbl.tick_sec:
status[0].next = not status[0]
status[1].next = memmap.mem_addr == 0x20
status[2].next = uart_rx
status[3].next = uart_tx
led.next = ledreg | statusbv | sw
pmod.next = 0
if sw[0]:
uart_tx.next = uart_rx
else:
uart_tx.next = cmd_tx
# @todo: PMOD OLED memmap control
return (tick_inst, uart_inst, cmd_inst, beh_led_control, beh_led_read,
beh_assign)
def icestick_blinky_host(clock, led, pmod, uart_tx, uart_rx, uart_dtr,
uart_rts):
"""
This example is similar to the other examples in this directory but
the LEDs are controlled externally via command packets sent from a
host via the UART on the icestick.
Ports:
clock:
led:
pmod:
uart_tx:
uart_rx:
"""
glbl = Global(clock, None)
ledreg = Signal(intbv(0)[8:])
# create the timer tick instance
tick_inst = glbl_timer_ticks(glbl, include_seconds=True)
# create the interfaces to the UART
fbustx = FIFOBus(width=8, size=4)
fbusrx = FIFOBus(width=8, size=4)
# create the memmap (CSR) interface
memmap = Barebone(glbl, data_width=32, address_width=32)
# create the UART instance.
uart_inst = uartlite(glbl, fbustx, fbusrx, uart_rx, uart_tx)
# create the packet command instance
cmd_inst = memmap_command_bridge(glbl, fbusrx, fbustx, memmap)
@always_seq(clock.posedge, reset=None)
def beh_led_control():
memmap.done.next = not (memmap.write or memmap.read)
if memmap.write and memmap.mem_addr == 0x20:
ledreg.next = memmap.write_data
@always_comb
def beh_led_read():
if memmap.read and memmap.mem_addr == 0x20:
memmap.read_data.next = ledreg
else:
memmap.read_data.next = 0
# blink one of the LEDs
tone = Signal(intbv(0)[8:])
@always_seq(clock.posedge, reset=None)
def beh_assign():
if glbl.tick_sec:
tone.next = (~tone) & 0x1
led.next = ledreg | tone[5:]
pmod.next = 0
# @todo: PMOD OLED memmap control
return (tick_inst, uart_inst, cmd_inst, beh_led_control, beh_led_read,
beh_assign)