def mm_lt24lcdsys(clock, reset, lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn,
lcd_rdn, lcd_data):
"""
"""
# interfaces
glbl = Global(clock, reset)
lcd = LT24Interface()
resolution = lcd.resolution
color_depth = lcd.color_depth
refresh_rate = 60
vmem = VideoMemory(resolution=resolution, color_depth=color_depth)
# assign the ports to the interface
lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn, lcd_rdn, lcd_data)
# simulation mode, reduce the dead time between real-world ticks
# modules
tck_inst = glbl_timer_ticks(glbl, user_timer=16, tick_div=100)
bar_inst = color_bars(glbl,
vmem,
resolution=resolution,
color_depth=color_depth)
lcd_inst = lt24lcd(glbl, vmem, lcd)
return myhdl.instances()
def test_lt24lcd(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=True)
glbl = Global(clock, reset)
lcd_on = Signal(bool(0))
lcd_resetn = Signal(bool(0))
lcd_csn = Signal(bool(0))
lcd_rs = Signal(bool(0))
lcd_wrn = Signal(bool(0))
lcd_rdn = Signal(bool(0))
lcd_data = Signal(intbv(0)[16:])
lcd = LT24Interface()
resolution = lcd.resolution
color_depth = lcd.color_depth
# assign the ports to the interface
lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn,
lcd_rdn, lcd_data)
mvd = LT24LCDDisplay()
@myhdl.block
def bench_lt24lcdsys():
tbdut = mm_lt24lcdsys(
clock, reset, lcd_on, lcd_resetn,
lcd_csn, lcd_rs, lcd_wrn, lcd_rdn, lcd_data
)
tbvd = mvd.process(glbl, lcd) # LCD display model
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(33)
yield clock.posedge
timeout = 33000
while mvd.update_cnt < 3 and timeout > 0:
yield delay(1000)
timeout -= 1
yield delay(100)
print("{:<10d}: simulation real time {}".format(now(), mvd.get_time()))
raise StopSimulation
return tbdut, tbvd, tbclk, tbstim
run_testbench(bench_lt24lcdsys)
def de0nano_lt24lcd(clock, reset, led,
# LT24 LCD display signals
lcd_on, lcd_resetn, lcd_csn, lcd_rs,
lcd_wrn, lcd_rdn, lcd_data
):
"""
The port names are the same as those in the board definition
(names in the user manual) for automatic mapping by the
rhea.build automation.
"""
# signals and interfaces
glbl = Global(clock, reset)
# ----------------------------------------------------------------
# global ticks
gtick = glbl_timer_ticks(glbl, include_seconds=True,
user_timer=16)
heartbeat = Signal(bool(0))
@always_seq(clock.posedge, reset=reset)
def rtl_leds():
if glbl.tick_sec:
heartbeat.next = not heartbeat
led.next = concat(intbv(0)[7:], heartbeat)
# ----------------------------------------------------------------
# LCD dislay
lcd = LT24Interface()
resolution, color_depth = lcd.resolution, lcd.color_depth
lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn,
lcd_rdn, lcd_data)
# color bars and the interface between video source-n-sink
vmem = VideoMemory(resolution=resolution, color_depth=color_depth)
gbar = color_bars(glbl, vmem, resolution=resolution,
color_depth=color_depth)
# LCD video driver
glcd = lt24lcd(glbl, vmem, lcd)
gens = gtick, rtl_leds, gbar, glcd
return gens
def tb_lt24lcd_driver(args=None):
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
lcd = LT24Interface()
display = LT24LCDDisplay()
cmd = Signal(intbv(0)[8:])
datalen = Signal(intbv(0, min=0, max=lcd.number_of_pixels+1))
data = Signal(intbv(0)[16:])
datasent = Signal(bool(0))
datalast = Signal(bool(0))
cmd_in_progress = Signal(bool(0))
def _bench_lt24lcd_driver():
tbdut = lt24lcd_driver(glbl, lcd, cmd, datalen, data,
datasent, datalast, cmd_in_progress,
maxlen=lcd.number_of_pixels)
gtck = glbl_timer_ticks(glbl, tick_div=100)
tbmdl = display.process(glbl, lcd)
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(111)
yield clock.posedge
# --------------------------------------------
# send a column write command
print("column write command")
cmd.next = 0x2A
bytes = [0, 0, 0, 239]
data.next = bytes[0]
datalen.next = 4
for ii in range(4):
yield datasent.posedge
data.next = bytes[ii+1] if ii < 3 else 0
cmd.next = 0
yield cmd_in_progress.negedge
yield clock.posedge
# --------------------------------------------
# send a page address write command
print("page address write command")
cmd.next = 0x2B
bytes = [0, 0, 1, 0x3F]
data.next = bytes[0]
datalen.next = 4
for ii in range(4):
yield datasent.posedge
data.next = bytes[ii+1] if ii < 3 else 0
cmd.next = 0
yield cmd_in_progress.negedge
yield clock.posedge
# --------------------------------------------
# write display memory, full update
print("display update")
cmd.next = 0x2C
data.next = randint(0, data.max-1)
datalen.next = lcd.number_of_pixels
for ii in range(lcd.number_of_pixels):
yield datasent.posedge
data.next = randint(0, data.max-1)
if (ii % 5000) == 0:
print("{} pixels xfer'd".format(ii))
cmd.next = 0
yield cmd_in_progress.negedge
yield clock.posedge
print("display update complete")
# --------------------------------------------
# @todo: verify the display received an image
yield delay(100)
raise StopSimulation
return tbdut, tbmdl, tbclk, tbstim, gtck
run_testbench(_bench_lt24lcd_driver)
def de0nano_converters(
clock,
reset,
led,
# ADC signals
adc_cs_n,
adc_saddr,
adc_sdat,
adc_sclk,
# Accelerometer and I2C signals
i2c_sclk,
i2c_sdat,
g_sensor_cs_n,
g_sensor_int,
# LT24 LCD display signals
lcd_on,
lcd_resetn,
lcd_csn,
lcd_rs,
lcd_wrn,
lcd_rdn,
lcd_data):
"""
The port names are the same as those in the board definition
(names in the user manual) for automatic mapping by the
rhea.build automation.
"""
# signals and interfaces
glbl = Global(clock, reset)
adcbus = SPIBus()
adcbus.mosi, adcbus.miso, adcbus.csn, adcbus.sck = (adc_saddr, adc_sdat,
adc_cs_n, adc_sclk)
fifobus = FIFOBus(width=16, size=16)
channel = Signal(intbv(0, min=0, max=8))
# ----------------------------------------------------------------
# global ticks
gtick = glbl_timer_ticks(glbl, include_seconds=True, user_timer=16)
# ----------------------------------------------------------------
# instantiate the ADC controller (retieves samples)
gconv = adc128s022(glbl, fifobus, adcbus, channel)
# read the samples out of the FIFO interface
fiford = Signal(bool(0))
@always(clock.posedge)
def rtl_read():
fiford = not fifobus.empty
@always_comb
def rtl_read_gate():
fifobus.rd.next = fiford and not fifobus.empty
# for now assign the samples to the LEDs for viewing
heartbeat = Signal(bool(0))
@always_seq(clock.posedge, reset=reset)
def rtl_leds():
if glbl.tick_sec:
heartbeat.next = not heartbeat
led.next = concat(fifobus.rdata[12:5], heartbeat)
# ----------------------------------------------------------------
# LCD dislay
lcd = LT24Interface()
resolution, color_depth = lcd.resolution, lcd.color_depth
lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn, lcd_rdn, lcd_data)
# color bars and the interface between video source-n-sink
vmem = VideoMemory(resolution=resolution, color_depth=color_depth)
gbar = color_bars(glbl,
vmem,
resolution=resolution,
color_depth=color_depth)
# LCD video driver
glcd = lt24lcd(glbl, vmem, lcd)
gens = gtick, gconv, rtl_read, rtl_leds, gbar, glcd
return gens