# verify bytes received and not timeout
print("RX FIFO count {}".format(regbus.get_read_data()))
assert regbus.get_read_data() == 5
print("read the returned bytes")
for ii in range(5):
yield regbus.readtrans(rf.sprx.addr)
print("spi readback {0}".format(regbus.get_read_data()))
except Exception as err:
print("@W: exception {0}".format(err))
yield delay(100)
traceback.print_exc()
raise err
yield delay(100)
raise StopSimulation
return tbstim, tbdut, tbeep, tbclk, tbmap
run_testbench(_bench_spi, args=args)
@pytest.mark.xfail
def test_convert():
convert()
if __name__ == '__main__':
testbench_spi(tb_args())
# test a single address
pkt = CommandPacket(True, 0x0000)
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [0])
pkt = CommandPacket(False, 0x0000, [0x5555AAAA])
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [0x5555AAAA])
# test a bunch of random addresses
for ii in range(nloops):
randaddr = randint(0, (2**20)-1)
randdata = randint(0, (2**32)-1)
pkt = CommandPacket(False, randaddr, [randdata])
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [randdata])
except Exception as err:
print("Error: {}".format(str(err)))
traceback.print_exc()
yield delay(2000)
raise StopSimulation
return tbclk, tbdut, tbfii, tbfio, tbmem, tbstim
run_testbench(_bench_command_bridge, args=args)
if __name__ == '__main__':
test_memmap_command_bridge(tb_args())
@always_comb
def tblpk():
rxp.next = txp
rxn.next = txn
@instance
def tbstim():
yield reset.pulse(32)
yield clock.posedge
for ii in range(100):
for jj in range(1000):
yield clock.posedge
yield delay(1000)
raise StopSimulation
return tbdut, tbclk, tblpk, tbstim
run_testbench(bench_serdes, timescale='1ps', args=args)
inst = parallella_serdes(
clock, txp, txn, rxp, rxn, leds
)
inst.convert(hdl='Verilog', directory='output', testbench=False)
if __name__ == '__main__':
args = tb_args()
test_parallella_serdes(args=args)
lcd_csn, lcd_rs, lcd_wrn, lcd_rdn,
lcd_data)
tbvd = mvd.process(glbl, lcd) # LCD display model
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(33)
yield clock.posedge
timeout = 33000
while mvd.update_cnt < 3 and timeout > 0:
yield delay(1000)
timeout -= 1
yield delay(100)
print("{:<10d}: simulation real time {}".format(now(), mvd.get_time()))
raise StopSimulation
return tbdut, tbvd, tbclk, tbstim
run_testbench(_bench_lt24lcdsys)
def test_conversion():
convert()
if __name__ == '__main__':
tb_lt24lcd(tb_args())
test_conversion()
# test a single address
pkt = CommandPacket(True, 0x0000)
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [0])
pkt = CommandPacket(False, 0x0000, [0x5555AAAA])
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [0x5555AAAA])
# test a bunch of random addresses
for ii in range(nloops):
randaddr = randint(0, (2**20) - 1)
randdata = randint(0, (2**32) - 1)
pkt = CommandPacket(False, randaddr, [randdata])
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [randdata])
except Exception as err:
print("Error: {}".format(str(err)))
traceback.print_exc()
yield delay(2000)
raise StopSimulation
return tbclk, tbdut, tbfii, tbfio, tbmem, tbstim
run_testbench(_bench_command_bridge, args=args)
if __name__ == '__main__':
test_memmap_command_bridge(tb_args())
for ii in range(numbytes):
wb = randint(0, 255)
print("send {:02X}".format(wb))
uartmdl.write(wb)
timeout = ((clock.frequency / uartmdl.baudrate) * 40)
rb = uartmdl.read()
while rb is None and timeout > 0:
yield clock.posedge
rb = uartmdl.read()
timeout -= 1
if rb is None:
raise TimeoutError
print("received {:02X}".format(rb))
assert rb == wb, "{:02X} != {:02X}".format(rb, wb)
yield delay(100)
raise StopSimulation
return tbdut, tbmdl, tbclk, tblpbk, tbstim
run_testbench(bench_uart, args=args)
if __name__ == '__main__':
args = tb_args(tests=['model', 'uart'])
if args.test == 'model' or args.test == 'all':
test_uart_model(args)
if args.test == 'uart' or args.test == 'all':
test_uart(args)
def testbench_memmap(args=None):
""" """
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
csbus = Barebone(glbl, data_width=8, address_width=16)
def bench_memmap():
tbdut = peripheral(csbus)
tbclk = clock.gen()
print(csbus.regfiles)
@instance
def tbstim():
yield reset.pulse(111)
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_memmap)
if __name__ == '__main__':
testbench_memmap(args=tb_args())
for ii in range(numbytes):
wb = randint(0, 255)
print("send {:02X}".format(wb))
uartmdl.write(wb)
timeout = ((clock.frequency/uartmdl.baudrate) * 40)
rb = uartmdl.read()
while rb is None and timeout > 0:
yield clock.posedge
rb = uartmdl.read()
timeout -= 1
if rb is None:
raise TimeoutError
print("received {:02X}".format(rb))
assert rb == wb, "{:02X} != {:02X}".format(rb, wb)
yield delay(100)
raise StopSimulation
return tbdut, tbmdl, tbclk, tblpbk, tbstim
run_testbench(_bench_uart, args=args)
if __name__ == '__main__':
args = tb_args(tests=['model', 'uart'])
if args.test == 'model' or args.test == 'all':
testbench_uart_model(args)
if args.test == 'uart' or args.test == 'all':
testbench_uart(args)
uartmdl.write(bb)
waitticks = int((1 / 115200.) / 1e-9) * 10 * 28
yield delay(waitticks)
timeout = 100
yield delay(waitticks)
# get the response packet
for ii in range(PACKET_LENGTH):
rb = uartmdl.read()
while rb is None and timeout > 0:
yield clock.posedge
rb = uartmdl.read()
timeout -= 1
if rb is None:
raise TimeoutError
# the last byte should be the byte written
assert rb == 0xFF
yield delay(1000)
raise StopSimulation
return tbclk, tbmdl, tbdut, tbstim
run_testbench(bench_ibh, args=args)
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog(catboard_blinky_host, clock, led, uart_tx, uart_rx)
if __name__ == '__main__':
test_ibh(tb_args())
lcd_csn, lcd_rs, lcd_wrn, lcd_rdn, lcd_data
)
tbvd = mvd.process(glbl, lcd) # LCD display model
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(33)
yield clock.posedge
timeout = 33000
while mvd.update_cnt < 3 and timeout > 0:
yield delay(1000)
timeout -= 1
yield delay(100)
print("{:<10d}: simulation real time {}".format(now(), mvd.get_time()))
raise StopSimulation
return tbdut, tbvd, tbclk, tbstim
run_testbench(bench_lt24lcdsys)
def test_conversion():
convert()
if __name__ == '__main__':
test_lt24lcd(tb_args())
test_conversion()
int(rr),
))
rr = int(cnt)
print("{}, {}, {}".format(Nramps, rr, timeout))
except AssertionError as err:
asserr.next = True
for _ in range(10):
yield clock.posedge
raise err
raise StopSimulation
# monitor the values from the fifo bus, it should
# be a simple "ramp" increasing values
_mask = 0xFF
_cval = Signal(modbv(0, min=0, max=256))
@always(clock.posedge)
def tbmon():
if fifobus.write:
assert _cval == fifobus.write_data
_cval.next = _cval + 1
return tbclk, tbdut, tbstim, tbmon, tbrbor
run_testbench(bench_fifo_ramp, args=args)
if __name__ == '__main__':
test_fifo_ramp(tb_args())
# verify bytes received and not timeout
print("RX FIFO count {}".format(regbus.get_read_data()))
assert regbus.get_read_data() == 5
print("read the returned bytes")
for ii in range(5):
yield regbus.readtrans(rf.sprx.addr)
print("spi readback {0}".format(regbus.get_read_data()))
except Exception as err:
print("@W: exception {0}".format(err))
yield delay(100)
traceback.print_exc()
raise err
yield delay(100)
raise StopSimulation
return tbstim, tbdut, tbeep, tbclk, tbmap
run_testbench(_bench_spi, args=args)
@pytest.mark.xfail
def test_convert():
convert()
if __name__ == '__main__':
testbench_spi(tb_args())
def testbench_memmap(args=None):
""" """
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
csrbus = Barebone(glbl, data_width=8, address_width=16)
def _bench_memmap():
tbdut = memmap_peripheral_regfile(csrbus)
tbclk = clock.gen()
print(csrbus.regfiles)
@instance
def tbstim():
yield reset.pulse(111)
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(_bench_memmap)
if __name__ == '__main__':
testbench_memmap(args=tb_args())
if cnt != rr or (timeout % 1000) == 0:
print(" ramp {} {}".format(int(cnt), int(rr),))
rr = int(cnt)
print("{}, {}, {}".format(Nramps, rr, timeout))
except AssertionError as err:
asserr.next = True
for _ in range(10):
yield clock.posedge
raise err
raise StopSimulation
# monitor the values from the fifo bus, it should
# be a simple "ramp" increasing values
_mask = 0xFF
_cval = Signal(modbv(0, min=0, max=256))
@always(clock.posedge)
def tbmon():
if fifobus.write:
assert _cval == fifobus.write_data
_cval.next = _cval+1
return tbclk, tbdut, tbstim, tbmon, tbrbor
run_testbench(bench_fifo_ramp, args=args)
if __name__ == '__main__':
test_fifo_ramp(tb_args())
lcd_rs, lcd_wrn, lcd_rdn, lcd_data)
tbvd = mvd.process(glbl, lcd) # LCD display model
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(33)
yield clock.posedge
timeout = 33000
while mvd.update_cnt < 3 and timeout > 0:
yield delay(1000)
timeout -= 1
yield delay(100)
print("{:<10d}: simulation real time {}".format(
now(), mvd.get_time()))
raise StopSimulation
return tbdut, tbvd, tbclk, tbstim
run_testbench(_bench_lt24lcdsys)
def test_conversion():
convert()
if __name__ == '__main__':
tb_lt24lcd(tb_args())
test_conversion()
lcd_rs, lcd_wrn, lcd_rdn, lcd_data)
tbvd = mvd.process(glbl, lcd) # LCD display model
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(33)
yield clock.posedge
timeout = 33000
while mvd.update_cnt < 3 and timeout > 0:
yield delay(1000)
timeout -= 1
yield delay(100)
print("{:<10d}: simulation real time {}".format(
now(), mvd.get_time()))
raise StopSimulation
return tbdut, tbvd, tbclk, tbstim
run_testbench(bench_lt24lcdsys)
def test_conversion():
convert()
if __name__ == '__main__':
test_lt24lcd(tb_args())
test_conversion()
return tbdut, tbitx, tbclk, tbstim
if run:
run_testbench(bench_to_generic, args=args)
def test_barebone():
testbench_to_generic(argparse.Namespace(bustype='barebone'))
pytest.skip(msg="simulator crashes, duplicate error, causes next to fail")
def test_wishbone():
testbench_to_generic(argparse.Namespace(bustype='wishbone'))
def tb_parser():
parser = argparse.ArgumentParser()
parser.add_argument('--bustype',
type=str,
choices=busmap.keys(),
default='barebone',
help="The memory-mapped bus type to test")
return parser
if __name__ == '__main__':
args = tb_args(parser=tb_parser())
testbench_to_generic(args)
yield delay(waitticks)
timeout = 100
yield delay(waitticks)
# get the response packet
for ii in range(PACKET_LENGTH):
rb = uartmdl.read()
while rb is None and timeout > 0:
yield clock.posedge
rb = uartmdl.read()
timeout -= 1
if rb is None:
raise Exception("TimeoutError")
# the last byte should be the byte written
assert rb == 0xFF
yield delay(1000)
raise StopSimulation
return tbclk, tbmdl, tbdut, tbstim
run_testbench(_bench_ibh, args=args)
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog(atlys_blinky_host, clock, reset,
led, sw, pmod,
uart_tx, uart_rx)
if __name__ == '__main__':
test_ibh(tb_args())
def test_spi_slave(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
spibus = SPIBus()
fifobus = FIFOBus()
def bench_spi_slave():
tbdut = spi_slave_fifo(glbl, spibus, fifobus)
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(40)
yield clock.posedge
yield spibus.writeread(0x55)
yield spibus.writeread(0xAA)
assert spibus.get_read_data() == 0x55
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_spi_slave, args=args)
if __name__ == '__main__':
args = tb_args()
test_spi_slave(args)
int(rr),
))
rr = int(cnt)
print("{}, {}, {}".format(Nramps, rr, timeout))
except AssertionError as err:
asserr.next = True
for _ in range(10):
yield clock.posedge
raise err
raise StopSimulation
# monitor the values from the fifo bus, it should
# be a simple "ramp" increasing values
_mask = 0xFF
_cval = Signal(modbv(0, min=0, max=256))
@always(clock.posedge)
def tbmon():
if fifobus.write:
assert _cval == fifobus.write_data
_cval.next = _cval + 1
return tbclk, tbdut, tbstim, tbmon, tbrbor
run_testbench(_bench_fifo_ramp, args=args)
if __name__ == '__main__':
tb_fifo_ramp(tb_args())
yield clock.posedge
yield delay(100)
raise StopSimulation
return tbdut, tbitx, tbclk, tbstim
if run:
run_testbench(bench_to_generic, args=args)
def test_barebone():
testbench_to_generic(argparse.Namespace(bustype='barebone'))
def test_wishbone():
testbench_to_generic(argparse.Namespace(bustype='wishbone'))
def tb_parser():
parser = argparse.ArgumentParser()
parser.add_argument('--bustype', type=str, choices=busmap.keys(),
default='barebone',
help="The memory-mapped bus type to test")
return parser
if __name__ == '__main__':
args = tb_args(parser=tb_parser())
testbench_to_generic(args)
if cnt != rr or (timeout % 1000) == 0:
print(" ramp {} {}".format(int(cnt), int(rr),))
rr = int(cnt)
print("{}, {}, {}".format(Nramps, rr, timeout))
except AssertionError as err:
asserr.next = True
for _ in range(10):
yield clock.posedge
raise err
raise StopSimulation
# monitor the values from the fifo bus, it should
# be a simple "ramp" increasing values
_mask = 0xFF
_cval = Signal(modbv(0, min=0, max=256))
@always(clock.posedge)
def tbmon():
if fifobus.write:
assert _cval == fifobus.write_data
_cval.next = _cval+1
return tbclk, tbdut, tbstim, tbmon, tbrbor
run_testbench(_bench_fifo_ramp, args=args)
if __name__ == '__main__':
tb_fifo_ramp(tb_args())