def generate_arbitrators(self, debug=False): #tags have already been set for this class if (not saparbitrator.is_arbitrator_required(self.project_tags, False)): return 0 arb_size_list = [] arbitrator_buffer = "" #we have some arbitrators, add the tag to the project # (this is needed for gen_top) # arb_tags = saparbitrator.generate_arbitrator_tags(self.project_tags, False) # self.project_tags["ARBITRATORS"] = arb_tags #for each of the items in the arbitrator list create a file tags #item that can be proecessed by sapfile.process file arb_tags = self.project_tags["ARBITRATORS"] for i in range (0, len(arb_tags.keys())): key = arb_tags.keys()[i] arb_size = len(arb_tags[key]) + 1 if (arb_size in arb_size_list): continue #we don't already have this size, so add it into the list arb_size_list.append(arb_size) fn = "arbitrator_" + str(arb_size) + "_masters.v" d = self.project_tags["BASE_DIR"] + "/rtl/bus/arbitrators" self.filegen.buf = saparbitrator.generate_arbitrator_buffer(arb_size) if debug: print "arbitrator buffer: " + self.filegen.buf self.filegen.write_file(d, fn) return len(arb_size_list)
def generate_arbitrators(self, debug=False):
"""Generates all the arbitrators modules from the configuration file
Searches for any required arbitrators in the configuration file.
Then generates the required arbitrators (2 to 1, 3 to 1, etc...)
Args:
Nothing
Return:
The largest size arbitrator generated (used for testing purposes)
Raises:
TypeError
IOError
"""
#tags have already been set for this class
if (not saparbitrator.is_arbitrator_required(self.project_tags,
False)):
return 0
arb_size_list = []
arbitrator_buffer = ""
#we have some arbitrators, add the tag to the project
# (this is needed for gen_top)
# arb_tags = saparbitrator.generate_arbitrator_tags(self.project_tags, False)
# self.project_tags["ARBITRATORS"] = arb_tags
#for each of the items in the arbitrator list create a file tags
#item that can be proecessed by sapfile.process file
arb_tags = self.project_tags["ARBITRATORS"]
for i in range(0, len(arb_tags.keys())):
key = arb_tags.keys()[i]
arb_size = len(arb_tags[key]) + 1
if (arb_size in arb_size_list):
continue
#we don't already have this size, so add it into the list
arb_size_list.append(arb_size)
fn = "arbitrator_" + str(arb_size) + "_masters.v"
d = self.project_tags["BASE_DIR"] + "/rtl/bus/arbitrators"
self.filegen.buf = saparbitrator.generate_arbitrator_buffer(
arb_size)
if debug:
print "arbitrator buffer: " + self.filegen.buf
self.filegen.write_file(d, fn)
return len(arb_size_list)
def generate_arbitrators(self, debug=False):
"""Generates all the arbitrators modules from the configuration file
Searches for any required arbitrators in the configuration file.
Then generates the required arbitrators (2 to 1, 3 to 1, etc...)
Args:
Nothing
Return:
The largest size arbitrator generated (used for testing purposes)
Raises:
TypeError
IOError
"""
#tags have already been set for this class
if (not saparbitrator.is_arbitrator_required(self.project_tags, False)):
return 0
arb_size_list = []
arbitrator_buffer = ""
#we have some arbitrators, add the tag to the project
# (this is needed for gen_top)
# arb_tags = saparbitrator.generate_arbitrator_tags(self.project_tags, False)
# self.project_tags["ARBITRATORS"] = arb_tags
#for each of the items in the arbitrator list create a file tags
#item that can be proecessed by sapfile.process file
arb_tags = self.project_tags["ARBITRATORS"]
for i in range (0, len(arb_tags.keys())):
key = arb_tags.keys()[i]
arb_size = len(arb_tags[key]) + 1
if (arb_size in arb_size_list):
continue
#we don't already have this size, so add it into the list
arb_size_list.append(arb_size)
fn = "arbitrator_" + str(arb_size) + "_masters.v"
d = self.project_tags["BASE_DIR"] + "/rtl/bus/arbitrators"
self.filegen.buf = saparbitrator.generate_arbitrator_buffer(arb_size)
if debug:
print "arbitrator buffer: " + self.filegen.buf
self.filegen.write_file(d, fn)
return len(arb_size_list)
def test_is_arbitrator_not_requried(self):
"""test if the project_tags have been modified to show arbitrator"""
result = False
tags = {}
#get the example project data
try:
filename = os.getenv("SAPLIB_BASE") + "/example_project/gpio_example.json"
filein = open(filename)
filestr = filein.read()
tags = json.loads(filestr)
except IOError as err:
print "File Error: " + str(err)
self.assertEqual(False, True)
result = saparbitrator.is_arbitrator_required(tags, debug = self.dbg)
self.assertEqual(result, False)
def test_is_arbitrator_requried(self):
"""test if the project_tags have been modified to show arbitrator"""
result = False
tags = {}
#get the example project data
try:
filename = os.getenv(
"SAPLIB_BASE") + "/example_project/arb_example.json"
filein = open(filename)
filestr = filein.read()
tags = json.loads(filestr)
except IOError as err:
print "File Error: " + str(err)
self.assertEqual(False, True)
result = saparbitrator.is_arbitrator_required(tags, debug=self.dbg)
self.assertEqual(result, True)
def generate_arbitrator_buffer(self, debug=False):
result = ""
board_dict = saputils.get_board_config(self.tags["board"])
invert_reset = board_dict["invert_reset"]
#self.wires
arbitrator_count = 0
if (not saparbitrator.is_arbitrator_required(self.tags)):
return ""
if debug:
print "arbitration is required"
result += "//Project Arbitrators\n\n"
arb_tags = saparbitrator.generate_arbitrator_tags(self.tags)
for i in range(0, len(arb_tags.keys())):
arb_slave = arb_tags.keys()[i]
master_count = 1
arb_name = ""
if debug:
print "found arbitrated slave: " + arb_slave
result += "//" + arb_slave + " arbitrator\n\n"
master_count += len(arb_tags[arb_slave].keys())
arb_name = "arb" + str(i)
arb_module = "arbitrator_" + str(master_count) + "_masters"
if debug:
print "number of masters for this arbitrator: " + str(
master_count)
print "using: " + arb_module
print "arbitrator name: " + arb_name
#generate the wires
for mi in range(0, master_count):
wbm_name = ""
if (mi == 0):
#these wires are taken care of by the interconnect
continue
else:
master_name = arb_tags[arb_slave].keys()[mi - 1]
bus_name = arb_tags[arb_slave][master_name]
wbm_name = master_name + "_" + bus_name
#strobe
wire = wbm_name + "_stb_o"
if (not (wire in self.wires)):
result += "\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#cycle
wire = wbm_name + "_cyc_o"
if (not (wire in self.wires)):
result += "\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#write enable
wire = wbm_name + "_we_o"
if (not (wire in self.wires)):
result += "\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#select
wire = wbm_name + "_sel_o"
if (not (wire in self.wires)):
result += "\twire\t[3:0]\t" + wire + ";\n"
self.wires.append(wire)
#in data
wire = wbm_name + "_dat_o"
if (not (wire in self.wires)):
result += "\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#out data
wire = wbm_name + "_dat_i"
if (not (wire in self.wires)):
result += "\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#address
wire = wbm_name + "_adr_o"
if (not (wire in self.wires)):
result += "\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#acknowledge
wire = wbm_name + "_ack_i"
if (not (wire in self.wires)):
result += "\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#interrupt
wire = wbm_name + "_int_i"
if (not (wire in self.wires)):
result += "\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#generate arbitrator signals
#strobe
wire = arb_name + "_wbs_stb_i"
if (not (wire in self.wires)):
result += "\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#cycle
wire = arb_name + "_wbs_cyc_i"
if (not (wire in self.wires)):
result += "\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#write enable
wire = arb_name + "_wbs_we_i"
if (not (wire in self.wires)):
result += "\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#select
wire = arb_name + "_wbs_sel_i"
if (not (wire in self.wires)):
result += "\twire\t[3:0]\t" + wire + ";\n"
self.wires.append(wire)
#in data
wire = arb_name + "_wbs_dat_i"
if (not (wire in self.wires)):
result += "\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#out data
wire = arb_name + "_wbs_dat_o"
if (not (wire in self.wires)):
result += "\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#address
wire = arb_name + "_wbs_adr_i"
if (not (wire in self.wires)):
result += "\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#acknowledge
wire = arb_name + "_wbs_ack_o"
if (not (wire in self.wires)):
result += "\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#interrupt
wire = arb_name + "_wbs_int_o"
if (not (wire in self.wires)):
result += "\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
result += "\n\n"
#finished generating the wires
result += "\t" + arb_module + " " + arb_name + "(\n"
result += "\t\t.clk(clk),\n"
if invert_reset:
result += "\t\t.rst(rst_n),\n"
else:
result += "\t\t.rst(rst),\n"
result += "\n"
result += "\t\t//masters\n"
for mi in range(0, master_count):
wbm_name = ""
#last master is always from the interconnect
#XXX: This should really be a parameter, but this will alow slaves to take over a peripheral
if (mi == master_count - 1):
if debug:
print "mi: " + str(mi)
on_periph_bus = False
#in this case I need to use the wishbone interconnect
#search for the index of the slave
for i in range(0, len(self.tags["SLAVES"].keys())):
name = self.tags["SLAVES"].keys()[i]
if name == arb_slave:
interconnect_index = i + 1 # +1 to account for DRT
on_periph_bus = True
wbm_name = "s" + str(interconnect_index)
if debug:
print "arb slave on peripheral bus"
print "slave index: " + str(
interconnect_index - 1)
print "accounting for drt, actual bus index == " + str(
interconnect_index)
break
#check mem bus
if (not on_periph_bus):
if ("MEMORY" in self.tags.keys()):
#There is a memory bus, look in here
for i in range(0, len(self.tags["MEMORY"].keys())):
name = self.tags["MEMORY"].keys()[i]
if name == arb_slave:
mem_inc_index = i
wbm_name = "sm" + str(i)
if debug:
print "arb slave on mem bus"
print "slave index: " + str(
mem_inc_index)
break
result += "\t\t.m" + str(
mi) + "_stb_i(" + wbm_name + "_wbs_stb_i),\n"
result += "\t\t.m" + str(
mi) + "_cyc_i(" + wbm_name + "_wbs_cyc_i),\n"
result += "\t\t.m" + str(
mi) + "_we_i(" + wbm_name + "_wbs_we_i),\n"
result += "\t\t.m" + str(
mi) + "_sel_i(" + wbm_name + "_wbs_sel_i),\n"
result += "\t\t.m" + str(
mi) + "_dat_i(" + wbm_name + "_wbs_dat_i),\n"
result += "\t\t.m" + str(
mi) + "_adr_i(" + wbm_name + "_wbs_adr_i),\n"
result += "\t\t.m" + str(
mi) + "_dat_o(" + wbm_name + "_wbs_dat_o),\n"
result += "\t\t.m" + str(
mi) + "_ack_o(" + wbm_name + "_wbs_ack_o),\n"
result += "\t\t.m" + str(
mi) + "_int_o(" + wbm_name + "_wbs_int_o),\n"
result += "\n\n"
#not the last index
else:
if debug:
print "mi: " + str(mi)
master_name = arb_tags[arb_slave].keys()[mi]
bus_name = arb_tags[arb_slave][master_name]
wbm_name = master_name + "_" + bus_name
result += "\t\t.m" + str(
mi) + "_stb_i(" + wbm_name + "_stb_o),\n"
result += "\t\t.m" + str(
mi) + "_cyc_i(" + wbm_name + "_cyc_o),\n"
result += "\t\t.m" + str(
mi) + "_we_i(" + wbm_name + "_we_o),\n"
result += "\t\t.m" + str(
mi) + "_sel_i(" + wbm_name + "_sel_o),\n"
result += "\t\t.m" + str(
mi) + "_dat_i(" + wbm_name + "_dat_o),\n"
result += "\t\t.m" + str(
mi) + "_adr_i(" + wbm_name + "_adr_o),\n"
result += "\t\t.m" + str(
mi) + "_dat_o(" + wbm_name + "_dat_i),\n"
result += "\t\t.m" + str(
mi) + "_ack_o(" + wbm_name + "_ack_i),\n"
result += "\t\t.m" + str(
mi) + "_int_o(" + wbm_name + "_int_i),\n"
result += "\n\n"
result += "\t\t//slave\n"
result += "\t\t.s_stb_o(" + arb_name + "_wbs_stb_i),\n"
result += "\t\t.s_cyc_o(" + arb_name + "_wbs_cyc_i),\n"
result += "\t\t.s_we_o(" + arb_name + "_wbs_we_i),\n"
result += "\t\t.s_sel_o(" + arb_name + "_wbs_sel_i),\n"
result += "\t\t.s_dat_o(" + arb_name + "_wbs_dat_i),\n"
result += "\t\t.s_adr_o(" + arb_name + "_wbs_adr_i),\n"
result += "\t\t.s_dat_i(" + arb_name + "_wbs_dat_o),\n"
result += "\t\t.s_ack_i(" + arb_name + "_wbs_ack_o),\n"
result += "\t\t.s_int_i(" + arb_name + "_wbs_int_o)\n"
result += ");\n"
return result
def generate_arbitrator_buffer(self, debug = False):
result = ""
board_dict = saputils.get_board_config(self.tags["board"])
invert_reset = board_dict["invert_reset"]
#self.wires
arbitrator_count = 0
if (not saparbitrator.is_arbitrator_required(self.tags)):
return ""
if debug:
print "arbitration is required"
result += "//Project Arbitrators\n\n"
arb_tags = saparbitrator.generate_arbitrator_tags(self.tags)
for i in range (0, len(arb_tags.keys())):
arb_slave = arb_tags.keys()[i]
master_count = 1
arb_name = ""
if debug:
print "found arbitrated slave: " + arb_slave
result += "//" + arb_slave + " arbitrator\n\n"
master_count += len(arb_tags[arb_slave].keys())
arb_name = "arb" + str(i)
arb_module = "arbitrator_" + str(master_count) + "_masters"
if debug:
print "number of masters for this arbitrator: " + str(master_count)
print "using: " + arb_module
print "arbitrator name: " + arb_name
#generate the wires
for mi in range (0, master_count):
wbm_name = ""
if (mi == 0):
#these wires are taken care of by the interconnect
continue
else:
master_name = arb_tags[arb_slave].keys()[mi - 1]
bus_name = arb_tags[arb_slave][master_name]
wbm_name = master_name + "_" + bus_name
#strobe
wire = wbm_name + "_stb_o"
if (not (wire in self.wires)):
result +="\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#cycle
wire = wbm_name + "_cyc_o"
if (not (wire in self.wires)):
result +="\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#write enable
wire = wbm_name + "_we_o"
if (not (wire in self.wires)):
result +="\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#select
wire = wbm_name + "_sel_o"
if (not (wire in self.wires)):
result +="\twire\t[3:0]\t" + wire + ";\n"
self.wires.append(wire)
#in data
wire = wbm_name + "_dat_o"
if (not (wire in self.wires)):
result +="\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#out data
wire = wbm_name + "_dat_i"
if (not (wire in self.wires)):
result +="\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#address
wire = wbm_name + "_adr_o"
if (not (wire in self.wires)):
result +="\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#acknowledge
wire = wbm_name + "_ack_i"
if (not (wire in self.wires)):
result +="\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#interrupt
wire = wbm_name + "_int_i"
if (not (wire in self.wires)):
result +="\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#generate arbitrator signals
#strobe
wire = arb_name + "_wbs_stb_i"
if (not (wire in self.wires)):
result +="\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#cycle
wire = arb_name + "_wbs_cyc_i"
if (not (wire in self.wires)):
result +="\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#write enable
wire = arb_name + "_wbs_we_i"
if (not (wire in self.wires)):
result +="\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#select
wire = arb_name + "_wbs_sel_i"
if (not (wire in self.wires)):
result +="\twire\t[3:0]\t" + wire + ";\n"
self.wires.append(wire)
#in data
wire = arb_name + "_wbs_dat_i"
if (not (wire in self.wires)):
result +="\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#out data
wire = arb_name + "_wbs_dat_o"
if (not (wire in self.wires)):
result +="\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#address
wire = arb_name + "_wbs_adr_i"
if (not (wire in self.wires)):
result +="\twire\t[31:0]\t" + wire + ";\n"
self.wires.append(wire)
#acknowledge
wire = arb_name + "_wbs_ack_o"
if (not (wire in self.wires)):
result +="\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
#interrupt
wire = arb_name + "_wbs_int_o"
if (not (wire in self.wires)):
result +="\twire\t\t\t" + wire + ";\n"
self.wires.append(wire)
result +="\n\n"
#finished generating the wires
result += "\t" + arb_module + " " + arb_name + "(\n"
result += "\t\t.clk(clk),\n"
if invert_reset:
result += "\t\t.rst(rst_n),\n"
else:
result += "\t\t.rst(rst),\n"
result += "\n"
result += "\t\t//masters\n"
for mi in range (0, master_count):
wbm_name = ""
#last master is always from the interconnect
#XXX: This should really be a parameter, but this will alow slaves to take over a peripheral
if (mi == master_count - 1):
if debug:
print "mi: " + str(mi)
on_periph_bus = False
#in this case I need to use the wishbone interconnect
#search for the index of the slave
for i in range (0, len(self.tags["SLAVES"].keys())):
name = self.tags["SLAVES"].keys()[i]
if name == arb_slave:
interconnect_index = i + 1 # +1 to account for DRT
on_periph_bus = True
wbm_name = "s" + str(interconnect_index)
if debug:
print "arb slave on peripheral bus"
print "slave index: " + str(interconnect_index - 1)
print "accounting for drt, actual bus index == " + str(interconnect_index)
break
#check mem bus
if (not on_periph_bus):
if ("MEMORY" in self.tags.keys()):
#There is a memory bus, look in here
for i in range (0, len(self.tags["MEMORY"].keys())):
name = self.tags["MEMORY"].keys()[i]
if name == arb_slave:
mem_inc_index = i
wbm_name = "sm" + str(i)
if debug:
print "arb slave on mem bus"
print "slave index: " + str(mem_inc_index)
break
result +="\t\t.m" + str(mi) + "_stb_i(" + wbm_name + "_wbs_stb_i),\n"
result +="\t\t.m" + str(mi) + "_cyc_i(" + wbm_name + "_wbs_cyc_i),\n"
result +="\t\t.m" + str(mi) + "_we_i(" + wbm_name + "_wbs_we_i),\n"
result +="\t\t.m" + str(mi) + "_sel_i(" + wbm_name + "_wbs_sel_i),\n"
result +="\t\t.m" + str(mi) + "_dat_i(" + wbm_name + "_wbs_dat_i),\n"
result +="\t\t.m" + str(mi) + "_adr_i(" + wbm_name + "_wbs_adr_i),\n"
result +="\t\t.m" + str(mi) + "_dat_o(" + wbm_name + "_wbs_dat_o),\n"
result +="\t\t.m" + str(mi) + "_ack_o(" + wbm_name + "_wbs_ack_o),\n"
result +="\t\t.m" + str(mi) + "_int_o(" + wbm_name + "_wbs_int_o),\n"
result +="\n\n"
#not the last index
else:
if debug:
print "mi: " + str(mi)
master_name = arb_tags[arb_slave].keys()[mi]
bus_name = arb_tags[arb_slave][master_name]
wbm_name = master_name + "_" + bus_name
result +="\t\t.m" + str(mi) + "_stb_i(" + wbm_name + "_stb_o),\n"
result +="\t\t.m" + str(mi) + "_cyc_i(" + wbm_name + "_cyc_o),\n"
result +="\t\t.m" + str(mi) + "_we_i(" + wbm_name + "_we_o),\n"
result +="\t\t.m" + str(mi) + "_sel_i(" + wbm_name + "_sel_o),\n"
result +="\t\t.m" + str(mi) + "_dat_i(" + wbm_name + "_dat_o),\n"
result +="\t\t.m" + str(mi) + "_adr_i(" + wbm_name + "_adr_o),\n"
result +="\t\t.m" + str(mi) + "_dat_o(" + wbm_name + "_dat_i),\n"
result +="\t\t.m" + str(mi) + "_ack_o(" + wbm_name + "_ack_i),\n"
result +="\t\t.m" + str(mi) + "_int_o(" + wbm_name + "_int_i),\n"
result +="\n\n"
result += "\t\t//slave\n"
result += "\t\t.s_stb_o(" + arb_name + "_wbs_stb_i),\n"
result += "\t\t.s_cyc_o(" + arb_name + "_wbs_cyc_i),\n"
result += "\t\t.s_we_o(" + arb_name + "_wbs_we_i),\n"
result += "\t\t.s_sel_o(" + arb_name + "_wbs_sel_i),\n"
result += "\t\t.s_dat_o(" + arb_name + "_wbs_dat_i),\n"
result += "\t\t.s_adr_o(" + arb_name + "_wbs_adr_i),\n"
result += "\t\t.s_dat_i(" + arb_name + "_wbs_dat_o),\n"
result += "\t\t.s_ack_i(" + arb_name + "_wbs_ack_o),\n"
result += "\t\t.s_int_i(" + arb_name + "_wbs_int_o)\n"
result += ");\n"
return result
