def __init__(self, hardware, mem, mode): self.hardware = hardware self.mem = mem if mode == 'r': mode = 'r' access = smmap.ACCESS_READ else: mode = 'r+' access = smmap.ACCESS_WRITE if mem == 'emce1': length = 4096 * 2 else: length = 49152 * 2 f = open('/dev/' + mem, mode) self.data = smmap.mmap(f.fileno(), length, 'h', access) f.close() self.pos = 0 if mem == 'emce0': self.write = self.writereal else: self.write = self.writecomplex
def __init__(self, hardware, mem, mode): self.hardware = hardware self.mem = mem if mode == 'r': mode = 'r' access = smmap.ACCESS_READ else: mode = 'r+' access = smmap.ACCESS_WRITE if mem == 'emce1': length = 4096*2 else: length = 49152*2 f = open('/dev/'+mem, mode) self.data = smmap.mmap(f.fileno(), length, 'h', access) f.close() self.pos = 0 if mem == 'emce0': self.write = self.writereal else: self.write = self.writecomplex
#!/usr/bin/python import sys import csv import smmap if len(sys.argv) == 3: length = int(sys.argv[2]) else: with open('/sys/devices/plb.0/84000000.proc2fpga/depth','r') as f: length = int(f.read()) if sys.argv[1][-1] != '0': length *= 2 f = open(sys.argv[1], 'r+') data = smmap.mmap(f.fileno(), length, 'h') f.close() if sys.argv[1][-1] != '0': for i in xrange(length): print "%s,%s" % data[i*2:i*2+2] else: for i in xrange(length): print "%s" % (data[i]) data.close()
import smmap f = open('data' ,'r+') x = smmap.mmap(f.fileno(), 10, 'h') print x[0] print x[0:3] x[1]=5 x[2]=-5 x[5:7] = (2,3) x[5:7] = (2,3,4)