def nRF51822_fixup(d):
d.soc_name = 'nRF51822'
d.cpu_info.deviceNumInterrupts = 32
# memory and misc peripherals
d.insert(soc.make_peripheral('ram', 0x20000000, 16 << 10, None, 'Data RAM'))
# This device has FICR.CLENR0 = 0xffffffff indicating that the code 0 region does not exist
d.insert(soc.make_peripheral('flash', 0, 256 << 10, None, 'Code FLASH'))
def nRF51822_fixup(d):
d.soc_name = 'nRF51822'
d.cpu_info.deviceNumInterrupts = 32
# memory and misc peripherals
d.insert(soc.make_peripheral('ram', 0x20000000, 16 << 10, None,
'Data RAM'))
# This device has FICR.CLENR0 = 0xffffffff indicating that the code 0 region does not exist
d.insert(soc.make_peripheral('flash', 0, 256 << 10, None, 'Code FLASH'))
def nRF52832_fixup(d):
d.soc_name = 'nRF52832'
d.cpu_info.nvicPrioBits = 3
d.cpu_info.deviceNumInterrupts = 39 # Note: reference manual has 37, svd file has 39
# remove some core peripherals - we'll replace them in the cpu fixup
d.remove(d.FPU)
# memory and misc peripherals
d.insert(soc.make_peripheral('ram', 0x20000000, 64 << 10, None, 'Data RAM'))
d.insert(soc.make_peripheral('flash', 0, 512 << 10, None, 'Code FLASH'))
def ATSAML21J18B_fixup(d):
d.soc_name = 'ATSAML21J18B'
d.cpu_info.deviceNumInterrupts = 32
# memory and misc periperhals
d.insert(soc.make_peripheral('flash', 0x00000000, 256 << 10, None, 'Flash'))
d.insert(soc.make_peripheral('rww', 0x00400000, 8 << 10, None, 'RWW Section'))
d.insert(soc.make_peripheral('sram', 0x20000000, 32 << 10, None, 'SRAM'))
d.insert(soc.make_peripheral('lp_sram', 0x30000000, 8 << 10, None, 'Low Power SRAM'))
d.insert(soc.make_peripheral('NVMUR', 0x00804000, 8, _nvm_user_row_regset, 'NVM User Row'))
def EFM32LG990F256_fixup(d):
d.soc_name = 'EFM32LG990F256'
d.cpu_info.nvicPrioBits = 3
d.cpu_info.deviceNumInterrupts = 40
# memory and misc periperhals
d.insert(soc.make_peripheral('flash', 0x00000000, 256 << 10, None, 'flash'))
d.insert(soc.make_peripheral('sram', 0x20000000, 32 << 10, None, 'sram'))
d.insert(soc.make_peripheral('DI', 0x0FE08000, 0x200, _device_info_regset, 'Device Information'))
# ram buffer for flash writing
d.rambuf = mem.region('rambuf', 0x20000000 + 512, 24 << 10)
def EFM32LG990F256_fixup(d):
d.soc_name = "EFM32LG990F256"
d.cpu_info.nvicPrioBits = 3
d.cpu_info.deviceNumInterrupts = 40
# memory and misc periperhals
d.insert(soc.make_peripheral("flash", 0x00000000, 256 << 10, None, "flash"))
d.insert(soc.make_peripheral("sram", 0x20000000, 32 << 10, None, "sram"))
d.insert(soc.make_peripheral("DI", 0x0FE08000, 0x200, _device_info_regset, "Device Information"))
# ram buffer for flash writing
d.rambuf = mem.region("rambuf", 0x20000000 + 512, 24 << 10)
def nRF52832_fixup(d):
d.soc_name = 'nRF52832'
d.cpu_info.nvicPrioBits = 3
d.cpu_info.deviceNumInterrupts = 39 # Note: reference manual has 37, svd file has 39
# remove some core peripherals - we'll replace them in the cpu fixup
d.remove(d.FPU)
# memory and misc peripherals
d.insert(soc.make_peripheral('ram', 0x20000000, 64 << 10, None,
'Data RAM'))
d.insert(soc.make_peripheral('flash', 0, 512 << 10, None, 'Code FLASH'))
def STM32F429xI_fixup(d):
d.soc_name = 'STM32F429xI'
d.cpu_info.nvicPrioBits = 4
d.cpu_info.deviceNumInterrupts = 90
# remove some core peripherals - we'll replace them in the cpu fixup
d.remove(d.NVIC)
# more decode for the DBG registers
f = d.DBG.DBGMCU_IDCODE.REV_ID
f.enumvals = soc.make_enumvals(f, _rev_id_enumset)
f = d.DBG.DBGMCU_IDCODE.DEV_ID
f.enumvals = soc.make_enumvals(f, _dev_id_enumset)
# fix up the OSPEEDR labels ST messed up
for x in ('A','B','C','D','E','F','G','H','I','J','K'):
d.peripherals['GPIO%c' % x].rename_register('GPIOB_OSPEEDR', 'OSPEEDR')
# more decode for the GPIO registers
gpio_decodes(d, ('A','B','C','D','E','F','G','H','I','J','K'), _STM32F429xI_altfunc)
# memory and misc periperhals
d.insert(soc.make_peripheral('sram', 0x20000000, 256 << 10, None, 'sram'))
d.insert(soc.make_peripheral('ccm_sram', 0x10000000, 64 << 10, None, 'core coupled memory sram'))
d.insert(soc.make_peripheral('flash_system', 0x1fff0000, 30 << 10, None, 'flash system memory'))
d.insert(soc.make_peripheral('flash_main', 0x08000000, 2 << 20, None, 'flash main memory'))
d.insert(soc.make_peripheral('flash_opt_bank1', 0x1fffc000, 16, None, 'flash option memory'))
d.insert(soc.make_peripheral('flash_opt_bank2', 0x1ffec000, 16, None, 'flash option memory'))
d.insert(soc.make_peripheral('flash_otp', 0x1fff7800, 528, None, 'flash otp memory'))
d.insert(soc.make_peripheral('UID', 0x1fff7a10, 12, _uuid_regset, 'Unique Device ID'))
d.insert(soc.make_peripheral('FLASH_SIZE', 0x1fff7a22, 2, _flash_size_regset, 'Flash Size'))
# the size of this peripheral seems wrong
d.OTG_HS_PWRCLK.size = 1 << 10
# ram buffer for flash writing
d.rambuf = mem.region('rambuf', 0x20000000 + 512, 32 << 10)
def MIMXRT1021_fixup(d):
d.soc_name = 'MIMXRT1021'
d.cpu_info.nvicPrioBits = 4
d.cpu_info.deviceNumInterrupts = 176
# fix up some peripherals
rt1020_iomuxc_fixup(d)
# more decodes for peripheral registers
flexspi_decodes(d)
# memory
d.insert(
soc.make_peripheral('itcm', 0x00000000, 256 << 10, None,
'Instruction Tightly Coupled Memory'))
d.insert(
soc.make_peripheral('romcp', 0x00200000, 96 << 10, None, 'Boot ROM'))
d.insert(
soc.make_peripheral('dtcm', 0x20000000, 256 << 10, None,
'Data Tightly Coupled Memory'))
d.insert(
soc.make_peripheral('ocram', 0x20200000, 256 << 10, None,
'On Chip RAM'))
d.insert(
soc.make_peripheral('flexspi_memory', 0x60000000, 504 << 20, None,
'FlexSPI Memory'))
d.insert(
soc.make_peripheral('flexspi_rxfifo', 0x7fc00000, 4 << 20, None,
'FlexSPI Rx FIFO'))
d.insert(
soc.make_peripheral('flexspi_txfifo', 0x7f800000, 4 << 20, None,
'FlexSPI Tx FIFO'))
d.insert(
soc.make_peripheral('semc_memory', 0x80000000, 1536 << 20, None,
'SEMC Memory'))
def cmd_info(self, ui,args):
"""display firmware information"""
# nor
ui.put('NOR Configuration Block\n')
nor = soc.make_peripheral('ncb', 0x60000000, 0x200, _FlexSPI_NOR_Configuration_Block, 'NOR Configuration Block')
nor.bind_cpu(self.cpu)
ui.put('%s\n\n' % nor.display(fields=True))
# ivt
ui.put('Image Vector Table\n')
ivt = soc.make_peripheral('ivt', 0x60001000, 32 << 2, _IVT_regset, 'Image Vector Table')
ivt.bind_cpu(self.cpu)
ui.put('%s\n\n' % ivt.display(fields=True))
# boot_data
boot_data = ivt.boot_data.rd()
if boot_data != 0:
ui.put('Boot Data\n')
bd = soc.make_peripheral('boot_data', boot_data, 3 << 2, _boot_data_regset, 'Boot Data')
bd.bind_cpu(self.cpu)
ui.put('%s\n\n' % bd.display(fields=True))
def STM32F427xx_fixup(d):
d.cpu_info.nvicPrioBits = 4
d.cpu_info.deviceNumInterrupts = 106
# remove some core peripherals - we'll replace them in the cpu fixup
d.remove(d.NVIC)
# more decode for the DBG registers
f = d.DBG.DBGMCU_IDCODE.REV_ID
f.enumvals = soc.make_enumvals(f, _rev_id_enumset)
f = d.DBG.DBGMCU_IDCODE.DEV_ID
f.enumvals = soc.make_enumvals(f, _dev_id_enumset)
# more decode for the GPIO registers
gpio_decodes(d, ('A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I'),
_STM32F427xx_altfunc)
# sram
d.insert(soc.make_peripheral('sram', 0x20000000, 256 << 10, None, 'sram'))
d.insert(
soc.make_peripheral('ccm_sram', 0x10000000, 64 << 10, None,
'core coupled memory sram'))
d.insert(
soc.make_peripheral('BKPSRAM', 0x40024000, 4 << 10, None,
'backup sram'))
# flash (rm0090 3.4 table 6))
d.insert(
soc.make_peripheral('flash_otp', 0x1fff7800, 528, None,
'flash otp memory'))
d.insert(
soc.make_peripheral('flash_system', 0x1fff0000, 30 << 10, None,
'flash system memory'))
d.insert(
soc.make_peripheral('flash_opt_bank1', 0x1fffc000, 16, None,
'flash option memory'))
d.insert(
soc.make_peripheral('flash_opt_bank2', 0x1ffec000, 16, None,
'flash option memory'))
# misc periperhals
d.insert(
soc.make_peripheral('UID', 0x1fff7a10, 12, _uuid_regset,
'Unique Device ID'))
d.insert(
soc.make_peripheral('FLASH_SIZE', 0x1fff7a22, 2, _flash_size_regset,
'Flash Size'))
# the size of this peripheral seems wrong
d.OTG_HS_PWRCLK.size = 1 << 10
# ram buffer for flash writing
d.rambuf = mem.region('rambuf', 0x20000000 + 512, 32 << 10)
def STM32F091xC_fixup(d):
d.soc_name = 'STM32F091xC'
d.cpu_info.deviceNumInterrupts = 32
# remove some core peripherals - we'll replace them in the cpu fixup
d.remove(d.NVIC)
# More decode for the DBGMCU registers
f = d.DBGMCU.IDCODE.REV_ID
f.enumvals = soc.make_enumvals(f, _rev_id_enumset)
f = d.DBGMCU.IDCODE.DEV_ID
f.enumvals = soc.make_enumvals(f, _dev_id_enumset)
# more decode for the GPIO registers
gpio_decodes(d, ('A', 'B', 'C', 'D', 'E', 'F'), _STM32F091xC_altfunc)
# TODO: RCC.AHBENR.IOPEEN is missing from the svd
# memory and misc periperhals
d.insert(soc.make_peripheral('sram', 0x20000000, 32 << 10, None, 'sram'))
d.insert(
soc.make_peripheral('flash_system', 0x1fffd800, 8 << 10, None,
'flash system memory'))
d.insert(
soc.make_peripheral('flash_main', 0x08000000, 256 << 10, None,
'flash main memory'))
d.insert(
soc.make_peripheral('flash_option', 0x1ffff800, 16, None,
'flash option memory'))
d.insert(
soc.make_peripheral('UID', 0x1ffff7ac, 12, _uuid_regset,
'Unique Device ID'))
d.insert(
soc.make_peripheral('FLASH_SIZE', 0x1ffff7cc, 2, _flash_size_regset,
'Flash Size'))
# ram buffer for flash writing
d.rambuf = mem.region('rambuf', 0x20000000 + 512, 24 << 10)
def STM32L432KC_fixup(d):
d.soc_name = 'STM32L432KC'
d.cpu_info.nvicPrioBits = 4
d.cpu_info.deviceNumInterrupts = 84
# remove some core peripherals - we'll replace them in the cpu fixup
d.remove(d.NVIC)
# ST didn't put DBGMCU in the SVD, so we will add it.
d.insert(
soc.make_peripheral('DBGMCU', 0xe0042000, 1 << 10, _DBGMCU_regset,
'Debug support'))
# more decode for the GPIO registers
gpio_decodes(d, ('A', 'B', 'C', 'D', 'E', 'H'), _STM32L432KC_altfunc)
# memory and misc periperhals
d.insert(soc.make_peripheral('sram1', 0x20000000, 48 << 10, None, 'sram1'))
# sram2 is found in 2 regions of the memory map
d.insert(soc.make_peripheral('sram2a', 0x2000c000, 16 << 10, None,
'sram2'))
d.insert(soc.make_peripheral('sram2b', 0x10000000, 16 << 10, None,
'sram2'))
d.insert(
soc.make_peripheral('flash_system', 0x1fff0000, 28 << 10, None,
'flash system memory'))
d.insert(
soc.make_peripheral('flash_main', 0x08000000, 256 << 10, None,
'flash main memory'))
d.insert(
soc.make_peripheral('flash_otp', 0x1fff7000, 1 << 10, None,
'flash otp memory'))
d.insert(
soc.make_peripheral('flash_option', 0x1fff7800, 16, None,
'flash option memory'))
d.insert(
soc.make_peripheral('UID', 0x1fff7590, 12, _uuid_regset,
'Unique Device ID'))
d.insert(
soc.make_peripheral('FLASH_SIZE', 0x1fff75e0, 2, _flash_size_regset,
'Flash Size'))
# ram buffer for flash writing
d.rambuf = mem.region('rambuf', 0x20000000 + 512, 32 << 10)
def STM32L432KC_fixup(d):
d.soc_name = 'STM32L432KC'
d.cpu_info.nvicPrioBits = 4
d.cpu_info.deviceNumInterrupts = 84
# remove some core peripherals - we'll replace them in the cpu fixup
d.remove(d.NVIC)
# ST didn't put DBGMCU in the SVD, so we will add it.
d.insert(soc.make_peripheral('DBGMCU', 0xe0042000, 1 << 10, _DBGMCU_regset, 'Debug support'))
# more decode for the GPIO registers
gpio_decodes(d, ('A','B','C','D','E','H'), _STM32L432KC_altfunc)
# memory and misc periperhals
d.insert(soc.make_peripheral('sram1', 0x20000000, 48 << 10, None, 'sram1'))
# sram2 is found in 2 regions of the memory map
d.insert(soc.make_peripheral('sram2a', 0x2000c000, 16 << 10, None, 'sram2'))
d.insert(soc.make_peripheral('sram2b', 0x10000000, 16 << 10, None, 'sram2'))
d.insert(soc.make_peripheral('flash_system', 0x1fff0000, 28 << 10, None, 'flash system memory'))
d.insert(soc.make_peripheral('flash_main', 0x08000000, 256 << 10, None, 'flash main memory'))
d.insert(soc.make_peripheral('flash_otp', 0x1fff7000, 1 << 10, None, 'flash otp memory'))
d.insert(soc.make_peripheral('flash_option', 0x1fff7800, 16, None, 'flash option memory'))
d.insert(soc.make_peripheral('UID', 0x1fff7590, 12, _uuid_regset, 'Unique Device ID'))
d.insert(soc.make_peripheral('FLASH_SIZE', 0x1fff75e0, 2, _flash_size_regset, 'Flash Size'))
# ram buffer for flash writing
d.rambuf = mem.region('rambuf', 0x20000000 + 512, 32 << 10)
def STM32F407xx_fixup(d):
d.soc_name = 'STM32F407xx'
d.cpu_info.nvicPrioBits = 4
d.cpu_info.deviceNumInterrupts = 82
# remove some core peripherals - we'll replace them in the cpu fixup
d.remove(d.NVIC)
# more decode for the DBG registers
f = d.DBG.DBGMCU_IDCODE.REV_ID
f.enumvals = soc.make_enumvals(f, _rev_id_enumset)
f = d.DBG.DBGMCU_IDCODE.DEV_ID
f.enumvals = soc.make_enumvals(f, _dev_id_enumset)
# more decode for the GPIO registers
gpio_decodes(d, ('A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I'),
_STM32F407xx_altfunc)
# additional interrupts
d.insert(
soc.make_interrupt('HASH_RNG_IRQ', 80,
'Hash and RNG global interrupt'))
d.insert(soc.make_interrupt('FPU_IRQ', 81, 'FPU global interrupt'))
# memory and misc periperhals
d.insert(soc.make_peripheral('sram', 0x20000000, 128 << 10, None, 'sram'))
d.insert(
soc.make_peripheral('ccm_sram', 0x10000000, 8 << 10, None,
'core coupled memory sram'))
d.insert(
soc.make_peripheral('flash_system', 0x1fff0000, 30 << 10, None,
'flash system memory'))
d.insert(
soc.make_peripheral('flash_main', 0x08000000, 1 << 20, None,
'flash main memory'))
d.insert(
soc.make_peripheral('flash_option', 0x1fffc000, 16, None,
'flash option memory'))
d.insert(
soc.make_peripheral('flash_otp', 0x1fff7800, 528, None,
'flash otp memory'))
d.insert(
soc.make_peripheral('UID', 0x1fff7a10, 12, _uuid_regset,
'Unique Device ID'))
d.insert(
soc.make_peripheral('FLASH_SIZE', 0x1fff7a22, 2, _flash_size_regset,
'Flash Size'))
# the size of these peripherals seems wrong
d.OTG_HS_GLOBAL.size = 1 << 10
d.OTG_HS_PWRCLK.size = 1 << 10
# ram buffer for flash writing
d.rambuf = mem.region('rambuf', 0x20000000 + 512, 32 << 10)
def __init__(self, ui, dbgio):
self.ui = ui
self.dbgio = dbgio
self.device = vendor.get_device(self.ui, soc_name)
# add the 8MiB SDRAM
self.device.insert(
soc.make_peripheral('sdram', 0xc0000000, 8 << 20, None,
'external sdram'))
self.dbgio.connect(self.device.cpu_info.name, 'swd')
self.cpu = cortexm.cortexm(self, ui, self.dbgio, self.device)
self.device.bind_cpu(self.cpu)
self.mem = mem.mem(self.cpu)
self.flash = flash.flash(flash_driver.sdrv(self.device), self.device,
self.mem)
gpio_drv = (gpio_driver.drv(self.device, gpio_cfg))
self.gpio = gpio.gpio(gpio_drv)
self.i2c1 = i2c.i2c(i2c_driver.bitbang(gpio_drv, 'PB8', 'PB9'))
self.i2c3 = i2c.i2c(i2c_driver.bitbang(gpio_drv, 'PH7', 'PH8'))
# setup the rtt client
ram = self.device.sram
self.rtt = rtt.rtt(self.cpu, mem.region('ram', ram.address, ram.size))
self.menu_root = (
('cpu', self.cpu.menu, 'cpu functions'),
('da', self.cpu.cmd_disassemble, cortexm.help_disassemble),
('debugger', self.dbgio.menu, 'debugger functions'),
('exit', self.cmd_exit),
('flash', self.flash.menu, 'flash functions'),
('go', self.cpu.cmd_go),
('gpio', self.gpio.menu, 'gpio functions'),
('halt', self.cpu.cmd_halt),
('help', self.ui.cmd_help),
('history', self.ui.cmd_history, cli.history_help),
('i2c1', self.i2c1.menu, 'i2c1 functions'),
('i2c3', self.i2c3.menu, 'i2c3 functions'),
('map', self.device.cmd_map),
('mem', self.mem.menu, 'memory functions'),
('program', self.flash.cmd_program, flash.help_program),
('regs', self.cmd_regs, soc.help_regs),
('rtt', self.rtt.menu, 'rtt client functions'),
('vtable', self.cpu.cmd_vtable),
)
self.ui.cli.set_root(self.menu_root)
self.set_prompt()
self.dbgio.cmd_info(self.ui, None)
def STM32F303xC_fixup(d):
d.soc_name = 'STM32F303xC'
d.cpu_info.nvicPrioBits = 4
d.cpu_info.deviceNumInterrupts = 84
# remove some core peripherals - we'll replace them in the cpu fixup
d.remove(d.NVIC)
d.remove(d.FPU)
# fix up the name of the FLASH peripheral
d.rename_peripheral('Flash', 'FLASH')
# More decode for the DBGMCU registers
f = d.DBGMCU.IDCODE.REV_ID
f.enumvals = soc.make_enumvals(f, _rev_id_enumset)
f = d.DBGMCU.IDCODE.DEV_ID
f.enumvals = soc.make_enumvals(f, _dev_id_enumset)
# more decode for the GPIO registers
gpio_decodes(d, ('A', 'B', 'C', 'D', 'E', 'F'), _STM32F303xC_altfunc)
# memory and misc periperhals
d.insert(soc.make_peripheral('sram', 0x20000000, 40 << 10, None, 'sram'))
d.insert(
soc.make_peripheral('ccm_sram', 0x10000000, 8 << 10, None,
'core coupled memory sram'))
d.insert(
soc.make_peripheral('flash_system', 0x1fffd800, 8 << 10, None,
'flash system memory'))
d.insert(
soc.make_peripheral('flash_main', 0x08000000, 256 << 10, None,
'flash main memory'))
d.insert(
soc.make_peripheral('flash_option', 0x1ffff800, 16, None,
'flash option memory'))
d.insert(
soc.make_peripheral('UID', 0x1ffff7ac, 12, _uuid_regset,
'Unique Device ID'))
d.insert(
soc.make_peripheral('FLASH_SIZE', 0x1ffff7cc, 2, _flash_size_regset,
'Flash Size'))
# ram buffer for flash writing
d.rambuf = mem.region('rambuf', 0x20000000 + 512, 32 << 10)
def STM32F303xC_fixup(d):
d.soc_name = 'STM32F303xC'
d.cpu_info.nvicPrioBits = 4
d.cpu_info.deviceNumInterrupts = 84
# remove some core peripherals - we'll replace them in the cpu fixup
d.remove(d.NVIC)
d.remove(d.FPU)
# More decode for the DBGMCU registers
f = d.DBGMCU.IDCODE.REV_ID
f.enumvals = soc.make_enumvals(f, _rev_id_enumset)
f = d.DBGMCU.IDCODE.DEV_ID
f.enumvals = soc.make_enumvals(f, _dev_id_enumset)
# more decode for the GPIO registers
gpio_decodes(d, ('A','B','C','D','E','F'), _STM32F303xC_altfunc)
# memory and misc periperhals
d.insert(soc.make_peripheral('sram', 0x20000000, 40 << 10, None, 'sram'))
d.insert(soc.make_peripheral('ccm_sram', 0x10000000, 8 << 10, None, 'core coupled memory sram'))
d.insert(soc.make_peripheral('flash_system', 0x1fffd800, 8 << 10, None, 'flash system memory'))
d.insert(soc.make_peripheral('flash_main', 0x08000000, 256 << 10, None, 'flash main memory'))
d.insert(soc.make_peripheral('flash_option', 0x1ffff800, 16, None, 'flash option memory'))
d.insert(soc.make_peripheral('UID', 0x1ffff7ac, 12, _uuid_regset, 'Unique Device ID'))
d.insert(soc.make_peripheral('FLASH_SIZE', 0x1ffff7cc, 2, _flash_size_regset, 'Flash Size'))
# ram buffer for flash writing
d.rambuf = mem.region('rambuf', 0x20000000 + 512, 32 << 10)
def STM32F103x8_fixup(d):
d.soc_name = 'STM32F103x8'
d.cpu_info.nvicPrioBits = 4
d.cpu_info.deviceNumInterrupts = 68
# remove some core peripherals - we'll replace them in the cpu fixup
d.remove(d.NVIC)
# memory and misc periperhals
d.insert(soc.make_peripheral('sram', 0x20000000, 20 << 10, None, 'sram'))
d.insert(
soc.make_peripheral('flash_main', 0x08000000, 64 << 10, None,
'flash main memory'))
d.insert(
soc.make_peripheral('flash_system', 0x1ffff000, 2 << 10, None,
'flash system memory'))
d.insert(
soc.make_peripheral('flash_option', 0x1ffff800, 16, None,
'flash option memory'))
d.insert(
soc.make_peripheral('FLASH_SIZE', 0x1ffff7e0, 2, _flash_size_regset,
'Flash Size'))
d.insert(
soc.make_peripheral('UID', 0x1ffff7e8, 12, _uuid_regset,
'Unique Device ID'))
_calib_fieldset = (
('NOREF', 31, 31, None, None),
('SKEW', 30, 30, None, None),
('TENMS', 23, 0, _TENMS_format, None),
)
_systick_regset = (
('CTRL', 32, 0x00, _ctrl_fieldset,
'(R/W) SysTick Control and Status Register'),
('LOAD', 32, 0x04, None, '(R/W) SysTick Reload Value Register'),
('VAL', 32, 0x08, None, '(R/W) SysTick Current Value Register'),
('CALIB', 32, 0x0c, _calib_fieldset, '(R/ ) SysTick Calibration Register'),
)
systick = soc.make_peripheral('SysTick', SysTick_BASE, 1 << 10,
_systick_regset, 'SysTick')
# -----------------------------------------------------------------------------
# System Control Block
# ACTLR?
_implementor_enumset = (('ARM', 0x41, None), )
_part_number_enumset = (
('CM0+', 0xc60, None),
('CM0', 0xc20, None),
('CM1', 0xc21, None),
('CM3', 0xc23, None),
('CM4', 0xc24, None),
('CM7', 0xc27, None),
def STM32F427xG_fixup(d):
d.soc_name = 'STM32F427xG'
# 1 MiB of flash for G devices
d.insert(
soc.make_peripheral('flash_main', 0x08000000, 1 << 20, None,
'flash main memory'))
)
_calib_fieldset = (
('NOREF', 31, 31, None, None),
('SKEW', 30, 30, None, None),
('TENMS', 23, 0, _TENMS_format, None),
)
_systick_regset = (
('CTRL', 32, 0x00, _ctrl_fieldset, '(R/W) SysTick Control and Status Register'),
('LOAD', 32, 0x04, None, '(R/W) SysTick Reload Value Register'),
('VAL', 32, 0x08, None, '(R/W) SysTick Current Value Register'),
('CALIB', 32, 0x0c, _calib_fieldset, '(R/ ) SysTick Calibration Register'),
)
systick = soc.make_peripheral('SysTick', SysTick_BASE, 1 << 10, _systick_regset, 'SysTick')
# -----------------------------------------------------------------------------
# System Control Block
# ACTLR?
_implementor_enumset = (
('ARM', 0x41, None),
)
_part_number_enumset = (
('CM0+', 0xc60, None),
('CM0', 0xc20, None),
('CM1', 0xc21, None),
('CM3', 0xc23, None),
def make_soc():
s = soc.soc()
s.soc_name = 'esp32'
s.insert(soc.make_peripheral('DPORT', 0x3ff00000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('AES', 0x3ff01000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('RSA', 0x3ff02000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('SHA', 0x3ff03000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('Secure_Boot', 0x3ff04000, 4 << 10, None, ''))
s.insert(
soc.make_peripheral('Cache_MMU_Table', 0x3ff10000, 16 << 10, None, ''))
s.insert(
soc.make_peripheral('PID_Controller', 0x3ff1f000, 4 << 10, None, ''))
s.insert(
soc.make_peripheral('uart0', 0x3ff40000, 4 << 10, _UART_regset,
'uart 0'))
s.insert(soc.make_peripheral('SPI1', 0x3ff42000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('SPI0', 0x3ff43000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('GPIO', 0x3ff44000, 4 << 10, None, ''))
s.insert(
soc.make_peripheral('GPIO_SD', 0x3ff44f00, 4 << 10, None,
'sigma delta'))
s.insert(soc.make_peripheral('FE2', 0x3ff45000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('FE', 0x3ff46000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('FRC_TIMER', 0x3ff47000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('RTCCNTL', 0x3ff48000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('RTCIO', 0x3ff48400, 4 << 10, None, ''))
s.insert(soc.make_peripheral('SENS', 0x3ff48800, 4 << 10, None, ''))
s.insert(soc.make_peripheral('IO_MUX', 0x3ff49000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('RTCMEM0', 0x3ff61000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('RTCMEM1', 0x3ff62000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('RTCMEM2', 0x3ff63000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('HINF', 0x3ff4b000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('UHCI1', 0x3ff4c000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('I2S0', 0x3ff4f000, 4 << 10, None, ''))
s.insert(
soc.make_peripheral('uart1', 0x3ff50000, 4 << 10, _UART_regset,
'uart 1'))
s.insert(soc.make_peripheral('BT', 0x3ff51000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('I2C0', 0x3ff53000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('UHCI0', 0x3ff54000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('SLCHOST', 0x3ff55000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('RMT', 0x3ff56000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('RMTMEM', 0x3ff56800, 4 << 10, None, ''))
s.insert(soc.make_peripheral('PCNT', 0x3ff57000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('SLC', 0x3ff58000, 4 << 10, None, ''))
s.insert(
soc.make_peripheral('ledc', 0x3ff59000, 4 << 10, _LEDC_regset,
'led pwm controller'))
s.insert(
soc.make_peripheral('EFUSE', 0x3ff5a000, 4 << 10, None,
'system configuration'))
s.insert(
soc.make_peripheral('SPI_ENCRYPT', 0x3ff5b000, 4 << 10, None,
'flash encryption'))
s.insert(soc.make_peripheral('PWM', 0x3ff5E000, 4 << 10, None, ''))
s.insert(
soc.make_peripheral('timg0', 0x3ff5F000, 4 << 10, _TIMG_regset,
'timer group 0'))
s.insert(
soc.make_peripheral('timg1', 0x3ff60000, 4 << 10, _TIMG_regset,
'timer group 1'))
s.insert(soc.make_peripheral('SPI2', 0x3ff64000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('SPI3', 0x3ff65000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('SYSCON', 0x3ff66000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('I2C1', 0x3ff67000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('SDMMC', 0x3ff68000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('EMAC', 0x3ff69000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('PWM1', 0x3ff6c000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('I2S1', 0x3ff6d000, 4 << 10, None, ''))
s.insert(
soc.make_peripheral('uart2', 0x3ff6e000, 4 << 10, _UART_regset,
'uart 2'))
s.insert(soc.make_peripheral('PWM2', 0x3ff6f000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('PWM3', 0x3ff70000, 4 << 10, None, ''))
s.insert(soc.make_peripheral('RNG', 0x3ff75000, 4 << 10, None, ''))
# 448 KiB internal ROM
s.insert(
soc.make_peripheral('irom0', 0x40000000, 384 << 10, None,
'internal rom 0'))
s.insert(
soc.make_peripheral('irom1', 0x3ff90000, 64 << 10, None,
'internal rom 1'))
# 520 KiB internal SRAM
s.insert(
soc.make_peripheral('iram0', 0x40070000, 192 << 10, None,
'internal sram 0'))
s.insert(
soc.make_peripheral('iram1_0', 0x3ffe0000, 128 << 10, None,
'internal sram 1 (alias 0)'))
s.insert(
soc.make_peripheral('iram1_1', 0x400a0000, 128 << 10, None,
'internal sram 1 (alias 1)'))
s.insert(
soc.make_peripheral('iram2', 0x3ffae000, 200 << 10, None,
'internal sram 2'))
# RTC Memory
s.insert(
soc.make_peripheral('rtc_fast_0', 0x3ff80000, 8 << 10, None,
'rtc fast ram (alias 0)'))
s.insert(
soc.make_peripheral('rtc_fast_1', 0x400c0000, 8 << 10, None,
'rtc fast ram (alias 1)'))
s.insert(
soc.make_peripheral('rtc_slow', 0x50000000, 8 << 10, None,
'rtc slow ram'))
# approx 16 MiB external SPI flash
s.insert(
soc.make_peripheral('eflash0', 0x3F400000, 4 << 20, None,
'external flash 0'))
s.insert(
soc.make_peripheral('eflash1', 0x400c2000, (11 << 20) + (248 << 10),
None, 'external flash 1'))
# external SRAM
s.insert(
soc.make_peripheral('eram', 0x3F800000, 4 << 20, None, 'external ram'))
return s