コード例 #1
0
    def __init__(self, name='Fpga', description='Fpga Container', **kwargs):

        super().__init__(name=name, description=description, **kwargs)

        #############
        # Add devices
        #############
        self.add(axi.AxiVersion(offset=0x00000000, ))

        self.add(ssi.SsiPrbsTx(offset=0x00040000, ))

        self.add(ssi.SsiPrbsRx(offset=0x00050000, ))

        self.add(rssi.RssiCore(offset=0x00070000, ))

        self.add(udp.UdpEngine(
            offset=0x00078000,
            numSrv=2,
            expand=False,
        ))

        self.add(
            ethPhy.TenGigEthReg(
                offset=0x80000000,
                writeEn=True,
                expand=True,
            ))
コード例 #2
0
    def __init__(self, **kwargs):
        super().__init__(**kwargs)

        self.add(axi.AxiVersion(offset=0x0000, ))

        self.add(ssi.SsiPrbsTx(offset=0x1000, ))

        self.add(ssi.SsiPrbsRx(offset=0x2000, ))
コード例 #3
0
    def __init__(self, expand=False, offset=0x0, **kwargs):

        super().__init__(
            expand=expand,
            offset=0x0,  # This module assume offset 0x0
            **kwargs)

        self.add(axi.AxiVersion(
            offset=AXIL_OFFSETS[7],
            expand=False,
        ))

        self.add(xilinx.Xadc(
            offset=AXIL_OFFSETS[8],
            expand=False,
        ))

        self.add(
            micron.AxiMicronN25Q(
                offset=AXIL_OFFSETS[9],
                addrMode=False,  # Assume 24-bit address support only
                hidden=True,
            ))

        self.add(
            pr.RemoteVariable(
                name='LSST_PWR_CORE_VERSION_C',
                description='See LsstPwrCtrlPkg.vhd for definitions',
                offset=AXIL_OFFSETS[7] + 0x400,  # 0x1C0400
                base=pr.UInt,
                mode='RO',
            ))

        self.add(
            pr.RemoteVariable(
                name='BOARD_ID',
                description='eFuse[7:0] value',
                offset=AXIL_OFFSETS[7] + 0x404,  # 0x1C0404
                base=pr.UInt,
                bitSize=8,
                mode='RO',
            ))

        self.add(
            pr.RemoteVariable(
                name='NUM_LANE_G',
                description='Number of Ethernet lanes',
                offset=AXIL_OFFSETS[7] + 0x408,  # 0x1C0408
                base=pr.UInt,
                mode='RO',
            ))
コード例 #4
0
    def __init__(self,
            ip = '192.168.2.10',
            **kwargs):
        super().__init__(**kwargs)

        # Create the RUDP connection and map SRP to DEST[0]
        self._Rudp = pr.protocols.UdpRssiPack(
            host    = ip,
            port    = 8192,
            packVer = 2,
        )
        self._RudpSrp = self._Rudp.application(0)

        # Connect the SRPv3 streams
        self._srp = rogue.protocols.srp.SrpV3()
        self._RudpSrp == self._srp

        # Add the AxiVersion device
        self.add(axi.AxiVersion(
            description = 'firmware/submodules/surf/python/surf/axi/_AxiVersion.py',
            offset      = (0*0x0001_0000),
            memBase     = self._srp,
        ))

        # Add Jitter cleaner PLL device
        self.add(silabs.Si5345(
            name        = 'Pll[0]',
            description = 'firmware/submodules/surf/python/surf/devices/silabs/_Si5345.py: FMC_HPC',
            offset      = (1*0x0001_0000),
            memBase     = self._srp,
        ))

        self.add(silabs.Si5345(
            name        = 'Pll[1]',
            description = 'firmware/submodules/surf/python/surf/devices/silabs/_Si5345.py: FMC_LPC',
            offset      = (2*0x0001_0000),
            memBase     = self._srp,
        ))

        # Add I2C GPIO device
        self.add(nxp.Pca9506(
            name        = 'Gpio',
            description = 'firmware/submodules/surf/python/surf/devices/nxp/_Pca9506.py',
            offset      = (3*0x0001_0000 + 0*0x0000_0400),
            memBase     = self._srp,
        ))
コード例 #5
0
    def __init__(self, **kwargs):

        if 'description' not in kwargs:
            kwargs['description'] = "HR Gen1 FPGA"

        super(self.__class__, self).__init__(**kwargs)
        ######################################
        # SACI base address and address stride
        ######################################
        saciAddr = 0x01000000
        saciChip = 0x400000

        #############
        # Add devices
        #############
        self.add(axi.AxiVersion(offset=0x00000000, expand=False))
        self.add(xilinx.Xadc(offset=0x00010000, expand=False))
        self.add(
            AtlasChess2Feb.sysReg(name="sysReg",
                                  offset=0x00030000,
                                  expand=False))
        self.add(
            AtlasChess2Feb.memReg(name="memReg",
                                  offset=0x00040000,
                                  expand=True))
        #self.add(AtlasChess2Feb.iobuff(   name="iobuff",    offset=0x00500000,expand=False))
        self.add(
            AtlasChess2Feb.dac(name="dac", offset=0x00100000, expand=False))
        self.add(
            AtlasChess2Feb.chargeInj(name="chargeInj",
                                     offset=0x00330000,
                                     expand=False))

        for i in range(3):
            self.add(
                AtlasChess2Feb.Chess2Array(name='Chess2Ctrl%01i' % (i),
                                           offset=(saciAddr + i * saciChip),
                                           enabled=False,
                                           expand=False))

        self.add(
            AtlasChess2Feb.Chess2Test(name="Chess2Test",
                                      offset=saciAddr + (3 * saciChip),
                                      enabled=False,
                                      expand=False))
コード例 #6
0
ファイル: _fpga.py プロジェクト: mizzihood/dev-board-examples
    def __init__(self,
                 name='Fpga',
                 fpgaType='',
                 commType='',
                 description='Fpga Container',
                 **kwargs):

        super().__init__(name=name, description=description, **kwargs)

        #############
        # Add devices
        #############
        self.add(axi.AxiVersion(
            offset=0x00000000,
            expand=False,
        ))

        if (fpgaType == '7series'):
            self.add(xil.Xadc(
                offset=0x00010000,
                expand=False,
            ))

        if (fpgaType == 'ultrascale'):
            self.add(xil.AxiSysMonUltraScale(
                offset=0x00020000,
                expand=False,
            ))

        self.add(
            MbSharedMem(
                name='MbSharedMem',
                offset=0x00030000,
                size=0x10000,
                expand=False,
            ))

        self.add(ssi.SsiPrbsTx(
            offset=0x00040000,
            expand=False,
        ))

        self.add(ssi.SsiPrbsRx(
            offset=0x00050000,
            expand=False,
        ))

        if (commType == 'eth'):
            self.add(rssi.RssiCore(
                offset=0x00070000,
                expand=False,
            ))

        self.add(
            axi.AxiStreamMonitoring(
                name='AxisMon',
                offset=0x00080000,
                numberLanes=2,
                expand=False,
            ))

        self.add(
            MbSharedMem(
                name='TestEmptyMem',
                offset=0x80000000,
                size=0x80000000,
                expand=False,
            ))
コード例 #7
0
    def __init__(self,
                 name="Top",
                 description="Container for FEB FPGA",
                 dev='/dev/datadev_0',
                 hwType='pcie',
                 ip='10.0.0.1',
                 **kwargs):
        super().__init__(name=name, description=description, **kwargs)

        # File writer
        dataWriter = pr.utilities.fileio.StreamWriter()
        self.add(dataWriter)

        ######################################################################

        if (hwType == 'hsio-dtm') or (hwType == 'rce-dpm'):
            # Create the mmap interface
            rceMap = rogue.hardware.axi.AxiMemMap('/dev/rce_memmap')
            # Add RCE version device
            self.add(rceg3.RceVersion(
                memBase=rceMap,
                expand=False,
            ))
            # Add PGPv3 to the FEB
            self.add(
                pgp.Pgp3AxiL(
                    name='Pgp3Mon',
                    memBase=rceMap,
                    offset=0xA0000000,
                    numVc=1,
                    writeEn=True,
                    expand=False,
                ))
            if (hwType == 'hsio-dtm'):
                # Add PGPv2b to the HSIO FPGA
                self.add(
                    pgp.Pgp2bAxi(
                        name='Pgp2bMon',
                        memBase=rceMap,
                        offset=0xA1000000,
                        expand=False,
                    ))
                # Connect the SRPv0 to PGPv2b.VC[1]
                pgp2bVc1 = rogue.hardware.axi.AxiStreamDma(
                    '/dev/axi_stream_dma_0', 1, True)
                srpV0 = rogue.protocols.srp.SrpV0()
                pr.streamConnectBiDir(srpV0, pgp2bVc1)

        if (hwType == 'pcie'):

            axiMemMap = rogue.hardware.axi.AxiMemMap(dev)

            self.add(
                pcie.AxiPcieCore(
                    memBase=axiMemMap,
                    offset=0x00000000,
                    expand=False,
                ))

            # for i in range(8):
            # self.add(pgp.Pgp3AxiL(
            # memBase         = axiMemMap,
            # name            = ('Pgp3Mon[%d]' % i),
            # offset          = (0x00800000 + i*0x10000),
            # numVc           = 16,
            # writeEn         = True,
            # expand          = False,
            # ))

        ######################################################################

        # Create an empty stream arrays
        configStream = [None] * 4
        dataStream = [None] * 4

        ########################################################################################################################
        # https://github.com/slaclab/rogue/blob/master/include/rogue/hardware/axi/AxiStreamDma.h
        # static boost::shared_ptr<rogue::hardware::axi::AxiStreamDma> create (std::string path, uint32_t dest, bool ssiEnable);
        ########################################################################################################################

        ######################################################################
        # PGPv3.[VC=0] = FEB SRPv3 Register Access
        # PGPv3.[VC=1] = RD53[DPORT=0] Streaming ASIC Configuration Interface
        # PGPv3.[VC=2] = RD53[DPORT=1] Streaming ASIC Configuration Interface
        # PGPv3.[VC=3] = RD53[DPORT=2] Streaming ASIC Configuration Interface
        # PGPv3.[VC=4] = RD53[DPORT=3] Streaming ASIC Configuration Interface
        # PGPv3.[VC=5] = RD53[DPORT=0] Streaming Data Interface
        # PGPv3.[VC=6] = RD53[DPORT=1] Streaming Data Interface
        # PGPv3.[VC=7] = RD53[DPORT=2] Streaming Data Interface
        # PGPv3.[VC=8] = RD53[DPORT=3] Streaming Data Interface
        ######################################################################

        if (hwType == 'simulation'):
            srpStream = pr.interfaces.simulation.StreamSim(host='localhost',
                                                           dest=0,
                                                           uid=12,
                                                           ssi=True)
            for i in range(4):
                configStream[i] = pr.interfaces.simulation.StreamSim(
                    host='localhost', dest=1 + i, uid=12, ssi=True)
                dataStream[i] = pr.interfaces.simulation.StreamSim(
                    host='localhost', dest=5 + i, uid=12, ssi=True)
        elif (hwType == 'eth'):
            rudp = pr.protocols.UdpRssiPack(host=ip, port=8192, packVer=2)
            srpStream = rudp.application(0)
            for i in range(4):
                configStream[i] = rudp.application(1 + i)
                dataStream[i] = rudp.application(5 + i)
        else:
            srpStream = rogue.hardware.axi.AxiStreamDma(dev, 0, True)
            for i in range(4):
                configStream[i] = rogue.hardware.axi.AxiStreamDma(
                    dev, 1 + i, True)
                dataStream[i] = rogue.hardware.axi.AxiStreamDma(
                    dev, 5 + i, True)

        ######################################################################

        # Connect the SRPv3 to PGPv3.VC[0]
        memMap = rogue.protocols.srp.SrpV3()
        pr.streamConnectBiDir(memMap, srpStream)

        for i in range(4):
            # Add data stream to file as channel [i] to dataStream[i]
            pr.streamConnect(dataStream[i], dataWriter.getChannel(i))

        ######################################################################

        # Add devices
        self.add(
            axiVer.AxiVersion(
                name='AxiVersion',
                memBase=memMap,
                offset=0x00000000,
                expand=False,
            ))

        self.add(
            xil.Xadc(
                name='Xadc',
                memBase=memMap,
                offset=0x00010000,
                expand=False,
            ))

        self.add(
            prom.AxiMicronP30(
                name='AxiMicronP30',
                memBase=memMap,
                offset=0x00020000,
                hidden=True,  # Hidden in GUI because indented for scripting
            ))

        self.add(
            common.SysReg(
                name='SysReg',
                description=
                'This device contains system level configuration and status registers',
                memBase=memMap,
                offset=0x00030000,
                expand=False,
            ))

        self.add(
            common.Ntc(
                name='Rd53Ntc',
                description=
                'This device contains the four NTC MAX6682 readout modules',
                memBase=memMap,
                offset=0x00040000,
                expand=False,
            ))

        self.add(
            nxp.Sa56004x(
                name='BoardTemp',
                description=
                'This device monitors the board temperature and FPGA junction temperature',
                memBase=memMap,
                offset=0x00050000,
                expand=False,
            ))

        self.add(
            linear.Ltc4151(
                name='BoardPwr',
                description=
                'This device monitors the board power, input voltage and input current',
                memBase=memMap,
                offset=0x00050400,
                senseRes=20.E-3,  # Units of Ohms
                expand=False,
            ))

        for i in range(4):
            self.add(
                common.RxPhyMon(
                    name=('RxPhyMon[%d]' % i),
                    memBase=memMap,
                    offset=(0x01000000 * (i + 1) + 0x00100000),
                    expand=False,
                ))

        self.add(
            common.Timing(
                name='Timing',
                description=
                'This device monitors the TLU and timing/trigger emulator',
                memBase=memMap,
                offset=0x05000000,
                expand=False,
            ))
コード例 #8
0
# Set base
base = pr.Root(name='simulation', description='Simple RogueSim Example')

# Connect the SRPv3 stream port
srpStream = pr.interfaces.simulation.StreamSim(host='localhost',
                                               dest=0,
                                               uid=1,
                                               ssi=True)
memMap = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir(memMap, srpStream)

# Add devices
base.add(
    axiVer.AxiVersion(
        name='AxiVersion',
        memBase=memMap,
        offset=0x00000000,
        expand=False,
    ))

# Start the system
base.start(
    pollEn=args.pollEn,
    initRead=args.initRead,
    timeout=1.0,
)

# Create GUI
appTop = pr.gui.application(sys.argv)
guiTop = pr.gui.GuiTop(group='rootMesh')
appTop.setStyle('Fusion')
guiTop.addTree(base)
コード例 #9
0
ファイル: SysReg.py プロジェクト: slaclab/dev-board-cryo
    def __init__(self,
                 name="SysReg",
                 description="AmcCarrierCore",
                 rssiNotInterlaved=True,
                 rssiInterlaved=False,
                 enableBsa=True,
                 enableMps=True,
                 expand=False,
                 **kwargs):
        super().__init__(name=name,
                         description=description,
                         expand=expand,
                         **kwargs)

        ##############################
        # Variables
        ##############################
        self.add(axi.AxiVersion(
            offset=0x00000000,
            expand=False,
        ))

        self.add(xilinx.AxiSysMonUltraScale(
            offset=0x02000000,
            expand=False,
        ))

        self.add(IIC(
            offset=0x03000000,
            expand=False,
        ))

        self.add(DevBoardTiming(
            offset=0x04000000,
            expand=False,
        ))

        self.add(LocReg(
            offset=0x07000000,
            expand=False,
        ))

        self.add(
            AmcCarrierBsa(
                offset=0x08000000,
                enableBsa=enableBsa,
                expand=False,
            ))

        self.add(
            udp.UdpEngineClient(
                name="BpUdpCltApp",
                offset=0x09000000,
                description=
                "Backplane UDP Client for Application ASYNC Messaging",
                expand=False,
            ))

        self.add(
            udp.UdpEngineServer(
                name="SwUdpSrv",
                offset=0x09000800,
                description="Backplane UDP Server: Xilinx XVC",
                expand=False,
            ))

        self.add(
            udp.UdpEngineServer(
                name="BpUdpSrvXvc",
                offset=0x09000808,
                description=
                "Backplane UDP Server: FSBL Legacy SRPv0 register access",
                expand=False,
            ))

        self.add(
            rssi.RssiCore(
                name="SwRssiServer",
                offset=0x09010000,
                description="Interleaved RSSI server",
                expand=False,
            ))

        self.add(AxiFanController(
            name="FanController",
            offset=0x0A000000,
        ))
コード例 #10
0
    def __init__(self,
                 name="Fmc",
                 description="FMC Container",
                 simulation=False,
                 fmcFru=False,
                 **kwargs):
        super().__init__(name=name, description=description, **kwargs)

        for i in range(4):
            self.add(
                asic.Ctrl(
                    name=f'Ctrl[{i}]',
                    offset=(0x10000 * i),
                    expand=False,
                ))

        if not (simulation):

            self.add(nxp.Pca9506(
                name='Gpio',
                offset=0x40000,
                expand=False,
            ))

            self.add(ti.Lmk61e2(
                name='Lmk',
                offset=0x40400,
                expand=False,
            ))

            self.add(
                silabs.Si5345(
                    name='Pll',
                    description='This device contains Jitter cleaner PLL',
                    offset=0x80000,
                    expand=False,
                    # hidden      = True, # Hidden in GUI because indented for scripting or YAML load
                ))

        self.add(
            asic.EmuTimingLut(
                name='EmuTimingLut',
                offset=0x90000,
                expand=False,
            ))

        self.add(
            asic.EmuTimingFsm(
                name='EmuTimingFsm',
                offset=0xA0000,
                expand=False,
            ))

        self.add(axi.AxiVersion(
            offset=0xB0000,
            expand=False,
        ))

        if (fmcFru):
            self.add(Fru(
                offset=0xC0000,
                hidden=True,
                expand=False,
            ))
コード例 #11
0
    def __init__(
            self,
            name="ClinkFeb",
            description="ClinkFeb Container",
            serial=None,
            camType=None,
            enI2C=False,  # disabled by default to prevent artificial timeouts due to long I2C access latency
            promLoad=False,
            **kwargs):
        super().__init__(name=name, description=description, **kwargs)

        # Init Variables for only 1 serial/camType per PGP lane
        self._serial = [serial, None]
        self._camType = [camType, None]

        # Add devices
        self.add(
            axi.AxiVersion(
                name='AxiVersion',
                offset=0x00000000,
                expand=False,
            ))

        if promLoad:
            self.add(
                prom.CypressS25Fl(
                    name='CypressS25Fl',
                    offset=0x00001000,
                    hidden=True,  # Hidden in GUI because indented for scripting
                ))

        else:

            self.add(
                nxp.Sa56004x(
                    name='BoardTemp',
                    description=
                    'This device monitors the board temperature and FPGA junction temperature',
                    offset=0x00002000,
                    expand=False,
                    enabled=
                    False,  # enabled=False because I2C are slow transactions and might "log jam" register transaction pipeline
                ))

            self.add(
                linear.Ltc4151(
                    name='BoardPwr',
                    description=
                    'This device monitors the board power, input voltage and input current',
                    offset=0x00002400,
                    senseRes=20.E-3,  # Units of Ohms
                    expand=False,
                    enabled=
                    False,  # enabled=False because I2C are slow transactions and might "log jam" register transaction pipeline
                ))

            self.add(xil.Xadc(
                name='Xadc',
                offset=0x00003000,
                expand=False,
            ))

            for i in range(4):
                self.add(
                    xceiver.Sfp(
                        name=f'Sfp[{i}]',
                        offset=0x00004000 + i * 0x00001000,
                        expand=False,
                        enabled=
                        False,  # enabled=False because I2C are slow transactions and might "log jam" register transaction pipeline
                    ))

            self.add(feb.Sem(
                name='Sem',
                offset=0x00008000,
                expand=False,
            ))

            self.add(
                cl.ClinkTop(
                    offset=0x00100000,
                    serial=self._serial,
                    camType=self._camType,
                    expand=True,
                ))

            self.add(
                feb.ClinkTrigCtrl(
                    name='TrigCtrl[0]',
                    description='Channel A trigger control',
                    offset=0x00200000,
                    expand=True,
                ))

            self.add(
                pgp.Pgp2bAxi(
                    name='PgpMon[0]',
                    offset=0x00400000,
                    statusCountBits=8,
                    errorCountBits=8,
                    writeEn=False,
                    expand=False,
                ))

            self.add(
                pgp.Pgp4AxiL(
                    name='PgpMon[1]',
                    offset=0x00410000,
                    numVc=4,
                    statusCountBits=16,
                    errorCountBits=8,
                    writeEn=False,
                    expand=True,
                ))
コード例 #12
0
    def __init__(
            self,
            name="ClinkFeb",
            description="ClinkFeb Container",
            serial=[None, None],
            camType=[None, None],
            version3=False,  # true = PGPv3, false = PGP2b
            **kwargs):
        super().__init__(name=name, description=description, **kwargs)

        # Add devices
        self.add(
            axi.AxiVersion(
                name='AxiVersion',
                offset=0x00000000,
                expand=False,
            ))

        self.add(
            prom.CypressS25Fl(
                name='CypressS25Fl',
                offset=0x00001000,
                hidden=True,  # Hidden in GUI because indented for scripting
            ))

        self.add(
            nxp.Sa56004x(
                name='BoardTemp',
                description=
                'This device monitors the board temperature and FPGA junction temperature',
                offset=0x00002000,
                expand=False,
            ))

        self.add(
            linear.Ltc4151(
                name='BoardPwr',
                description=
                'This device monitors the board power, input voltage and input current',
                offset=0x00002400,
                senseRes=20.E-3,  # Units of Ohms
                expand=False,
            ))

        self.add(xil.Xadc(
            name='Xadc',
            offset=0x00003000,
            expand=False,
        ))

        self.add(
            cl.ClinkTop(
                offset=0x00100000,
                serial=serial,
                camType=camType,
                expand=False,
            ))

        self.add(
            feb.ClinkTrigCtrl(
                name='TrigCtrl[0]',
                description='Channel A trigger control',
                offset=0x00200000,
                expand=False,
            ))

        self.add(
            feb.ClinkTrigCtrl(
                name='TrigCtrl[1]',
                description='Channel B trigger control',
                offset=0x00200100,
                expand=False,
            ))

        for i in range(2):

            if (version3):
                self.add(
                    pgp.Pgp3AxiL(
                        name=(f'PgpMon[{i}]'),
                        offset=(0x00400000 + i * 0x2000),
                        numVc=4,
                        writeEn=False,
                        expand=False,
                    ))

                # self.add(axi.AxiStreamMonitoring(
                # name        = (f'PgpTxAxisMon[{i}]'),
                # offset      = (0x00400000 + i*0x4000 + 0x4000),
                # numberLanes = 4,
                # expand      = False,
                # ))

                # self.add(axi.AxiStreamMonitoring(
                # name        = (f'PgpRxAxisMon[{i}]'),
                # offset      = (0x00400000 + i*0x4000 + 0x6000),
                # numberLanes = 4,
                # expand      = False,
                # ))

            else:
                self.add(
                    pgp.Pgp2bAxi(
                        name=(f'PgpMon[{i}]'),
                        offset=(0x00400000 + i * 0x6000 + 0 * 0x2000),
                        writeEn=False,
                        expand=False,
                    ))
コード例 #13
0
    def __init__(self,
                 name="AmcCarrierCore",
                 description="AmcCarrierCore",
                 enablePwrI2C=False,
                 enableBsa=True,
                 enableMps=True,
                 numWaveformBuffers=4,
                 enableTpgMini=True,
                 expand=False,
                 **kwargs):
        super().__init__(name=name,
                         description=description,
                         expand=expand,
                         **kwargs)

        ##############################
        # Variables
        ##############################
        self.add(axi.AxiVersion(offset=0x00000000, expand=False))

        self.add(xilinx.AxiSysMonUltraScale(offset=0x01000000, expand=False))

        self.add(
            micron.AxiMicronN25Q(
                name="MicronN25Q",
                offset=0x2000000,
                addrMode=True,
                expand=False,
                hidden=True,
            ))

        self.add(
            microchip.AxiSy56040(offset=0x03000000,
                                 expand=False,
                                 description="\n\
                Timing Crossbar:  https://confluence.slac.stanford.edu/x/m4H7D   \n\
                -----------------------------------------------------------------\n\
                OutputConfig[0] = 0x0: Connects RTM_TIMING_OUT0 to RTM_TIMING_IN0\n\
                OutputConfig[0] = 0x1: Connects RTM_TIMING_OUT0 to FPGA_TIMING_IN\n\
                OutputConfig[0] = 0x2: Connects RTM_TIMING_OUT0 to BP_TIMING_IN\n\
                OutputConfig[0] = 0x3: Connects RTM_TIMING_OUT0 to RTM_TIMING_IN1\n\
                -----------------------------------------------------------------\n\
                OutputConfig[1] = 0x0: Connects FPGA_TIMING_OUT to RTM_TIMING_IN0\n\
                OutputConfig[1] = 0x1: Connects FPGA_TIMING_OUT to FPGA_TIMING_IN\n\
                OutputConfig[1] = 0x2: Connects FPGA_TIMING_OUT to BP_TIMING_IN\n\
                OutputConfig[1] = 0x3: Connects FPGA_TIMING_OUT to RTM_TIMING_IN1 \n\
                -----------------------------------------------------------------\n\
                OutputConfig[2] = 0x0: Connects Backplane DIST0 to RTM_TIMING_IN0\n\
                OutputConfig[2] = 0x1: Connects Backplane DIST0 to FPGA_TIMING_IN\n\
                OutputConfig[2] = 0x2: Connects Backplane DIST0 to BP_TIMING_IN\n\
                OutputConfig[2] = 0x3: Connects Backplane DIST0 to RTM_TIMING_IN1\n\
                -----------------------------------------------------------------\n\
                OutputConfig[3] = 0x0: Connects Backplane DIST1 to RTM_TIMING_IN0\n\
                OutputConfig[3] = 0x1: Connects Backplane DIST1 to FPGA_TIMING_IN\n\
                OutputConfig[3] = 0x2: Connects Backplane DIST1 to BP_TIMING_IN\n\
                OutputConfig[3] = 0x3: Connects Backplane DIST1 to RTM_TIMING_IN1\n\
                -----------------------------------------------------------------\n"
                                 ))

        # self.add(ti.AxiCdcm6208(
        # offset       =  0x05000000,
        # enabled      =  False,
        # hidden       =  True,
        # expand       =  False,
        # ))

        self.add(amcc.AmcCarrierBsi(
            offset=0x07000000,
            expand=False,
        ))

        self.add(
            amcc.AmcCarrierTiming(
                offset=0x08000000,
                expand=False,
                enableTpgMini=enableTpgMini,
            ))

        self.add(
            amcc.AmcCarrierBsa(
                offset=0x09000000,
                enableBsa=enableBsa,
                numWaveformBuffers=numWaveformBuffers,
                expand=False,
            ))

        self.add(
            udp.UdpEngineClient(
                name="BpUdpCltApp",
                offset=0x0A000000,
                description=
                "Backplane UDP Client for Application ASYNC Messaging",
                expand=False,
            ))

        self.add(
            udp.UdpEngineServer(
                name="BpUdpSrvXvc",
                offset=0x0A000800,
                description="Backplane UDP Server: Xilinx XVC",
                expand=False,
            ))

        self.add(
            udp.UdpEngineServer(
                name="BpUdpSrvFsbl",
                offset=0x0A000808,
                description=
                "Backplane UDP Server: FSBL Legacy SRPv0 register access",
                expand=False,
            ))

        self.add(
            udp.UdpEngineServer(
                name="BpUdpSrvRssi[0]",
                offset=0x0A000810,
                description=
                "Backplane UDP Server: Legacy Non-interleaved RSSI for Register access and ASYNC messages",
                expand=False,
            ))

        self.add(
            udp.UdpEngineServer(
                name="BpUdpSrvRssi[1]",
                offset=0x0A000818,
                description=
                "Backplane UDP Server: Legacy Non-interleaved RSSI for bulk data transfer",
                expand=False,
            ))

        self.add(
            udp.UdpEngineServer(
                name="BpUdpSrvRssi[2]",
                offset=0x0A000830,
                description="Backplane UDP Server: Interleaved RSSI",
                expand=False,
            ))

        self.add(
            udp.UdpEngineServer(
                name="BpUdpSrvApp",
                offset=0x0A000820,
                description=
                "Backplane UDP Server for Application ASYNC Messaging",
                expand=False,
            ))

        self.add(
            udp.UdpEngineServer(
                name="BpUdpSrvTiming",
                offset=0x0A000828,
                description="Backplane UDP Server for Timing ASYNC Messaging",
                expand=False,
            ))

        for i in range(2):
            self.add(
                rssi.RssiCore(
                    name=f'SwRssiServer[{i}]',
                    offset=0x0A010000 + (i * 0x1000),
                    description="SwRssiServer Server: %i" % (i),
                    expand=False,
                ))

        self.add(
            rssi.RssiCore(
                name="SwRssiServer[2]",
                offset=0x0A020000,
                description="SwRssiServer Server",
                expand=False,
            ))

        if (enableMps):
            self.add(mps.AppMps(offset=0x0C000000, expand=False))

        if (enablePwrI2C):
            self.add(intel.EM22xx(offset=0x0D000000, expand=False))
コード例 #14
0
    def __init__( self,
        name        = 'Fpga',
        fpgaType    = '',
        commType    = '',
        description = 'Fpga Container',
        **kwargs):

        super().__init__(name=name,description=description, **kwargs)

        self.add(axi.AxiVersion(
            offset = 0x00000000,
            expand = True,
        ))

        if(fpgaType=='7series'):

            self.add(xil.Xadc(
                offset = 0x00010000,
                expand = False,
            ))

        if(fpgaType=='ultrascale'):

            self.add(xil.AxiSysMonUltraScale(
                offset = 0x00020000,
                expand = False,
            ))

        # self.add(MbSharedMem(
            # name   = 'MbSharedMem',
            # offset = 0x00030000,
            # size   = 0x10000,
            # expand = False,
        # ))

        self.add(ssi.SsiPrbsTx(
            offset = 0x00040000,
            expand = False,
        ))

        self.add(ssi.SsiPrbsRx(
            offset = 0x00050000,
            expand = False,
        ))

        if ( commType == 'eth' ):

            self.add(rssi.RssiCore(
                offset = 0x00070000,
                expand = False,
            ))

            # self.add(udp.UdpEngine(
                # offset = 0x00078000,
                # numSrv = 1,
                # expand = False,
            # ))

        self.add(axi.AxiStreamMonAxiL(
            name        = 'AxisMon',
            offset      = 0x00080000,
            numberLanes = 2,
            expand      = False,
        ))
コード例 #15
0
    def __init__(
            self,
            name='Core',
            description='Container for Atlas Atca Link Agg Core registers',
            frontPanelI2C=False,
            **kwargs):

        super().__init__(name=name, description=description, **kwargs)

        # self.add(MyAxiVersion(
        self.add(
            axi.AxiVersion(
                name='AxiVersion',
                offset=0x00000000,
                expand=False,
            ))

        self.add(
            xil.AxiSysMonUltraScale(
                name='SysMon',
                offset=0x00001000,
                expand=False,
            ))

        self.add(
            prom.AxiMicronN25Q(
                name='AxiMicronN25Q',
                offset=0x00002000,
                addrMode=True,  # True = 32-bit Address Mode
                hidden=True,  # Hidden in GUI because indented for scripting
            ))

        self.add(
            AtlasAtcaLinkAgg.Bsi(
                name='Bsi',
                offset=0x00003000,
                expand=False,
            ))

        if frontPanelI2C:

            self.add(
                nxp.Pca9506(
                    name='Pca9506',
                    offset=0x0000A000,
                    expand=False,
                    pollInterval=5,
                ))

            for i in range(4):

                self.add(
                    pr.LinkVariable(
                        name=f'SfpPresent[{i}]',
                        mode='RO',
                        linkedGet=lambda i=i:
                        (~int(self.Pca9506.IP[1].value()) >> (i + 0)) & 0x1,
                        dependencies=[self.Pca9506.IP[1]],
                        hidden=True,
                    ))

                self.add(
                    xceiver.Sff8472(
                        name=f'Sfp[{i}]',
                        offset=0x00004000 + i * 0x00001000,
                        expand=False,
                        enableDeps=[self.SfpPresent[i]],
                    ))

            for i in range(2):

                self.add(
                    pr.LinkVariable(
                        name=f'QsfpPresent[{i}]',
                        mode='RO',
                        linkedGet=lambda i=i:
                        (~int(self.Pca9506.IP[1].value()) >> (i + 4)) & 0x1,
                        dependencies=[self.Pca9506.IP[1]],
                        hidden=True,
                    ))

                self.add(
                    xceiver.Sff8472(
                        name=f'Qsfp[{i}]',
                        offset=0x00008000 + i * 0x00001000,
                        expand=False,
                        enableDeps=[self.QsfpPresent[i]],
                    ))

        self.add(ti.Lmk61e2(
            name='Lmk',
            offset=0x0000B000,
            expand=False,
        ))

        self.add(
            silabs.Si5345Lite(
                name='Pll',
                description='This device contains Jitter cleaner PLL',
                offset=0x00010000,
                expand=False,
            ))
コード例 #16
0
    def __init__(self,
                 name="Top",
                 description="Container for XPM",
                 memBase=0,
                 **kwargs):
        super().__init__(name=name, description=description, **kwargs)

        ######################################################################

        # Add devices
        self.add(
            axi.AxiVersion(
                memBase=memBase,
                offset=0x00000000,
                expand=False,
            ))

        self.add(
            xil.AxiSysMonUltraScale(memBase=memBase,
                                    offset=0x01000000,
                                    expand=False))

        self.add(
            micron.AxiMicronN25Q(
                memBase=memBase,
                name="MicronN25Q",
                offset=0x2000000,
                addrMode=True,
                expand=False,
                hidden=True,
            ))

        self.add(microchip.AxiSy56040(
            memBase = memBase,
            offset       =  0x03000000,
            expand       =  False,
            description  = "\n\
                Timing Crossbar:  https://confluence.slac.stanford.edu/x/m4H7D   \n\
                -----------------------------------------------------------------\n\
                OutputConfig[0] = 0x0: Connects RTM_TIMING_OUT0 to RTM_TIMING_IN0\n\
                OutputConfig[0] = 0x1: Connects RTM_TIMING_OUT0 to FPGA_TIMING_IN\n\
                OutputConfig[0] = 0x2: Connects RTM_TIMING_OUT0 to BP_TIMING_IN\n\
                OutputConfig[0] = 0x3: Connects RTM_TIMING_OUT0 to RTM_TIMING_IN1\n\
                -----------------------------------------------------------------\n\
                OutputConfig[1] = 0x0: Connects FPGA_TIMING_OUT to RTM_TIMING_IN0\n\
                OutputConfig[1] = 0x1: Connects FPGA_TIMING_OUT to FPGA_TIMING_IN\n\
                OutputConfig[1] = 0x2: Connects FPGA_TIMING_OUT to BP_TIMING_IN\n\
                OutputConfig[1] = 0x3: Connects FPGA_TIMING_OUT to RTM_TIMING_IN1 \n\
                -----------------------------------------------------------------\n\
                OutputConfig[2] = 0x0: Connects Backplane DIST0 to RTM_TIMING_IN0\n\
                OutputConfig[2] = 0x1: Connects Backplane DIST0 to FPGA_TIMING_IN\n\
                OutputConfig[2] = 0x2: Connects Backplane DIST0 to BP_TIMING_IN\n\
                OutputConfig[2] = 0x3: Connects Backplane DIST0 to RTM_TIMING_IN1\n\
                -----------------------------------------------------------------\n\
                OutputConfig[3] = 0x0: Connects Backplane DIST1 to RTM_TIMING_IN0\n\
                OutputConfig[3] = 0x1: Connects Backplane DIST1 to FPGA_TIMING_IN\n\
                OutputConfig[3] = 0x2: Connects Backplane DIST1 to BP_TIMING_IN\n\
                OutputConfig[3] = 0x3: Connects Backplane DIST1 to RTM_TIMING_IN1\n\
                -----------------------------------------------------------------\n"\
            ))

        self.add(
            ti.AxiCdcm6208(
                memBase=memBase,
                offset=0x05000000,
                expand=False,
            ))

        self.add(
            xpm.TimingFrameRx(
                memBase=memBase,
                name='UsTiming',
                offset=0x08000000,
            ))

        self.add(
            xpm.TimingFrameRx(
                memBase=memBase,
                name='CuTiming',
                offset=0x08400000,
            ))

        self.add(
            xpm.CuGenerator(
                memBase=memBase,
                name='CuGenerator',
                offset=0x08800000,
            ))

        for i in range(len(Top.mmcmParms)):
            self.add(
                xpm.MmcmPhaseLock(
                    memBase=memBase,
                    name=Top.mmcmParms[i][0],
                    offset=Top.mmcmParms[i][1],
                ))

        hsrParms = [['HSRep0', 0x09000000], ['HSRep1', 0x09010000],
                    ['HSRep2', 0x09020000], ['HSRep3', 0x09030000],
                    ['HSRep4', 0x09040000], ['HSRep5', 0x09050000]]
        for i in range(len(hsrParms)):
            self.add(
                xpm.Ds125br401(
                    memBase=memBase,
                    name=hsrParms[i][0],
                    offset=hsrParms[i][1],
                ))

        self.amcs = []
        for i in range(2):
            amc = xpm.MpsSfpAmc(
                memBase=memBase,
                name='Amc%d' % i,
                offset=0x09000000 + (i + 1) * 0x100000,
            )
            self.add(amc)
            self.amcs.append(amc)

#        self.add(timing.GthRxAlignCheck(
        self.add(
            xpm.GthRxAlignCheck(
                memBase=memBase,
                name='UsGthRxAlign',
                offset=0x0b000000,
            ))

        #        self.add(timing.GthRxAlignCheck(
        self.add(
            xpm.GthRxAlignCheck(
                memBase=memBase,
                name='CuGthRxAlign',
                offset=0x0c000000,
            ))

        self.add(
            xpm.XpmApp(
                memBase=memBase,
                name='XpmApp',
                offset=0x80000000,
            ))

        self.add(
            AxiLiteRingBuffer(
                memBase=memBase,
                name='AxiLiteRingBuffer',
                datawidth=16,
                offset=0x80010000,
            ))

        self.add(
            xpm.XpmSequenceEngine(
                memBase=memBase,
                name='SeqEng_0',
                offset=0x80020000,
            ))

        #        self.add(xpm.CuPhase(
        #            memBase = memBase,
        #            name = 'CuPhase',
        #            offset = 0x80050000,
        #        ))

        self.add(
            xpm.XpmPhase(
                memBase=memBase,
                name='CuToScPhase',
                offset=0x80050000,
            ))